debugging, next snapshot

3d67d687 · Andrey Filippov · 8b1e18d4 · 3d67d687 · 3d67d687 · 3d67d687
Commit 3d67d687 authored May 28, 2014 by Andrey Filippov
13 changed files
--- a/.project
+++ b/.project
@@ -51,7 +51,7 @@
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140522152648076.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140522174846453.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
@@ -61,12 +61,12 @@
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140522152648076.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140522174846453.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140522152648076.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140522174846453.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
@@ -76,7 +76,7 @@
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140522152648076.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140522174846453.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
@@ -86,7 +86,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140522152648076.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140522174846453.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
@@ -96,7 +96,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140522152648076.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140522174846453.log</location>
 		</link>
 		<link>
 			<name>vivado_state/eddr3-opt-phys.dcp</name>
@@ -106,7 +106,7 @@
 		<link>
 			<name>vivado_state/eddr3-place.dcp</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140522152648076.dcp</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140522174846453.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/eddr3-route.dcp</name>
@@ -116,7 +116,7 @@
 		<link>
 			<name>vivado_state/eddr3-synth.dcp</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140522152648076.dcp</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140522174846453.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>
--- a/ddrc_control.v
+++ b/ddrc_control.v
@@ -61,7 +61,11 @@ module  ddrc_control #(
    parameter PAGES_REL_MASK =    'h3ff,  // address mask to set DQM and DQS patterns
    parameter CMDA_EN_REL =       'h022,  // address to enable('h823)/disable('h822) command/address outputs  
    parameter CMDA_EN_REL_MASK =  'h3fe,  // address mask for command/address outputs
-    parameter EXTRA_REL =         'h024,  // address to set extra parameters (currently just inv_clk_div)
+    parameter SDRST_ACT_REL =     'h024,  // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory  
+    parameter SDRST_ACT_REL_MASK ='h3fe,  // address mask for reset DDR3
+    parameter CKE_EN_REL =        'h026,  // address to enable('h827)/disable('h826) CKE signal to memory   
+    parameter CKE_EN_REL_MASK =   'h3fe,  // address mask for command/address outputs
+    parameter EXTRA_REL =         'h028,  // address to set extra parameters (currently just inv_clk_div)
    parameter EXTRA_REL_MASK =    'h3ff   // address mask for extra parameters
 )(
    input                         clk,
@@ -85,7 +89,10 @@ module  ddrc_control #(
    output                        ld_delay, // write dly_data to dly_address, one mclk active pulse
    output                        dly_set,      // transfer (activate) all delays simultaneosly, 1 mclk pulse 
 // control: additional signals
-    output                        cmda_tri,    // tri-state all command and address lines to DDR chip
+    output                        cmda_en,  // tri-state all command and address lines to DDR chip
+    output                        ddr_rst,  // generate DDR3 memory reset signal
+    output                        ddr_cke,  // control DDR3 memory CKE signal
    output                        inv_clk_div, // invert clk_div to ISERDES
    output                 [ 7:0] dqs_pattern, // DQS pattern during write (normally 8'h55)
    output                 [ 7:0] dqm_pattern, // DQM pattern (just for testing, should be 8'h0)
@@ -108,6 +115,12 @@ module  ddrc_control #(
    localparam PAGES_ADDR_MASK =    CONTROL_ADDR_MASK | PAGES_REL_MASK;   // address mask to set DQM and DQS patterns
    localparam CMDA_EN_ADDR =       CONTROL_ADDR |      CMDA_EN_REL;      // address to enable('h823)/disable('h822) command/address outputs  
    localparam CMDA_EN_ADDR_MASK =  CONTROL_ADDR_MASK | CMDA_EN_REL_MASK; // address mask for command/address outputs
+    localparam SDRST_ACT_ADDR =     CONTROL_ADDR |      SDRST_ACT_REL;      // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory    
+    localparam SDRST_ACT_ADDR_MASK =CONTROL_ADDR_MASK | SDRST_ACT_REL_MASK; // address mask for reset DDR3
+    localparam CKE_EN_ADDR =        CONTROL_ADDR |      CKE_EN_REL;       // address to enable('h827)/disable('h826) CKE signal to memory  
+    localparam CKE_EN_ADDR_MASK =   CONTROL_ADDR_MASK | CKE_EN_REL_MASK;  // address mask for CKE
    localparam EXTRA_ADDR =         CONTROL_ADDR |      EXTRA_REL;        // address to set extra parameters (currently just inv_clk_div)
    localparam EXTRA_ADDR_MASK =    CONTROL_ADDR_MASK | EXTRA_REL_MASK;   // address mask for extra parameters
@@ -133,6 +146,9 @@ module  ddrc_control #(
    reg                  [ 1:0] port1_page_r;     // port 1 buffer write page (to be controlled by arbiter later, set to 2'b0)
    reg                  [ 1:0] port1_int_page_r; // port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0) 
    reg                         cmda_en_r;        // enable (tri-state off) all command and address lines to DDR chip
+    reg                         ddr_rst_r;        // generate DDR3 memory reset
+    reg                         ddr_cke_r;         // enable CKE to memory
    reg                         inv_clk_div_r;    // invert clk_div to ISERDES
    assign ld_delay = dly_ld_r;
@@ -141,7 +157,7 @@ module  ddrc_control #(
    assign dly_addr = waddr_fifo_out_r[ 6:0]; //WARNING: [Synth 8-3936] Found unconnected internal register 'waddr_fifo_out_r_reg' and it is trimmed from '12' to '7' bits. [ddrc_control.v:101]
    assign run_addr = wdata_fifo_out_r[10:0];
    assign run_chn =  waddr_fifo_out_r[3:0];
-    assign run_seq =  run_seq_r;
+    assign run_seq =  run_seq_r && !ddr_rst;
    assign busy=busy_r && (start_wburst?(((pre_waddr ^ BUSY_WR_ADDR) & BUSY_WR_ADDR_MASK)==0): selected_busy);
@@ -151,7 +167,9 @@ module  ddrc_control #(
    assign port0_int_page = port0_int_page_r[1:0];
    assign port1_page =     port1_page_r[1:0];
    assign port1_int_page = port1_int_page_r[1:0];
-    assign cmda_tri =       ~cmda_en_r;
+    assign cmda_en =        cmda_en_r;
+    assign ddr_rst=         ddr_rst_r;
+    assign ddr_cke=         ddr_cke_r;
    assign inv_clk_div =    inv_clk_div_r;
    always @ (posedge clk or posedge rst) begin
@@ -202,6 +220,14 @@ module  ddrc_control #(
        else if (fifo_re && (((waddr_fifo_out ^ CMDA_EN_ADDR) & CMDA_EN_ADDR_MASK)==0))
                 cmda_en_r <= waddr_fifo_out[0];
+        if (rst) ddr_rst_r <= 1'b1; // enable DDR3 reset at system reset
+        else if (fifo_re && (((waddr_fifo_out ^ SDRST_ACT_ADDR) & SDRST_ACT_ADDR_MASK)==0))
+                 ddr_rst_r <= waddr_fifo_out[0];
+        if (rst) ddr_cke_r <= 1'b0;
+        else if (fifo_re && (((waddr_fifo_out ^ CKE_EN_ADDR) & CKE_EN_ADDR_MASK)==0))
+                 ddr_cke_r <= waddr_fifo_out[0];
        if (rst) inv_clk_div_r <= 1'b0;
        else if (fifo_re && (((waddr_fifo_out ^ EXTRA_ADDR) & EXTRA_ADDR_MASK)==0))
                 inv_clk_div_r <= wdata_fifo_out[0];

--- a/ddrc_test01.v
+++ b/ddrc_test01.v
@@ -72,12 +72,15 @@ module  ddrc_test01 #(
    parameter PAGES_REL_MASK =      'h3ff,  // address mask to set DQM and DQS patterns
    parameter CMDA_EN_REL =         'h022,  // address to enable('h823)/disable('h822) command/address outputs  
    parameter CMDA_EN_REL_MASK =    'h3fe,  // address mask for command/address outputs
-    parameter EXTRA_REL =           'h024,  // address to set extra parameters (currently just inv_clk_div)
+    parameter SDRST_ACT_REL =       'h024,  // address to activate('h825)/deactivate('h824) active-low reset signal to DDR3 memory  
+    parameter SDRST_ACT_REL_MASK =  'h3fe,  // address mask for reset DDR3
+    parameter CKE_EN_REL =          'h026,  // address to enable('h827)/disable('h826) CKE signal to memory   
+    parameter CKE_EN_REL_MASK =     'h3fe,  // address mask for command/address outputs
+    parameter EXTRA_REL =           'h028,  // address to set extra parameters (currently just inv_clk_div)
    parameter EXTRA_REL_MASK =      'h3ff   // address mask for extra parameters
 )(
    // DDR3 interface
+    output                       SDRST, // DDR3 reset (active low)
    output                       SDCLK, // DDR3 clock differential output, positive
    output                       SDNCLK,// DDR3 clock differential output, negative
    output  [ADDRESS_NUMBER-1:0] SDA,   // output address ports (14:0) for 4Gb device
@@ -99,9 +102,7 @@ module  ddrc_test01 #(
 );
    localparam ADDRESS_NUMBER=15;
 // Source for reset and clock
-(* keep = "true" *)
   wire    [3:0]     fclk;      // PL Clocks [3:0], output
-(* keep = "true" *)
   wire    [3:0]     frst;      // PL Clocks [3:0], output
@@ -110,7 +111,7 @@ module  ddrc_test01 #(
 (* keep = "true" *)
   wire           axi_aclk;    // clock - should be buffered
 //   wire           axi_aresetn; // reset, active low
-(* keep = "true" *)
+(* dont_touch = "true" *)
   wire           axi_rst;     // reset, active high
 // AXI Write Address
   wire   [31:0]  axi_awaddr;  // AWADDR[31:0], input
@@ -209,7 +210,10 @@ module  ddrc_test01 #(
   wire [ 1:0] port1_int_page;// input[1:0] 
 // additional control signals
-   wire        cmda_tri; // input
+   wire        cmda_en; // enable DDR3 memory control and addreee outputs
+   wire        ddr_rst; // generate DDR3 memory reset (active hight)
+   wire        ddr_cke; // control of the DDR3 memory CKE signal
   wire        inv_clk_div; // input
   wire [ 7:0] dqs_pattern; // input[7:0] 8'h55 
   wire [ 7:0] dqm_pattern; // input[7:0] 8'h00
@@ -236,13 +240,26 @@ module  ddrc_test01 #(
 always @ (posedge axi_rst or posedge axi_aclk) begin
    if (axi_rst) select_port0 <= 1'b0;
-    else if (axird_start_burst) select_port0 <= (((axird_pre_araddr[11:10]^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
+    else if (axird_start_burst) select_port0 <= (((axird_pre_araddr^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
    if (axi_rst) select_status <= 1'b0;
-    else if (axird_start_burst) select_status <= (((axird_pre_araddr[11:10]^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
+    else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
 end
+/*   
 // Clock and reset from PS
-BUFG bufg_axi_rst_i  (.O(axi_rst),.I(~frst[0]));
+reg frst_inv;
+always @ (negedge frst[0] or posedge axi_aclk) begin
+    if (!frst[0]) frst_inv <= 1'b1;
+    else          frst_inv <= 1'b0; 
+end
+*/
+`ifndef IVERILOG
+(* dont_touch = "true" *)
+`endif
+ wire frst_inv= ~frst[0];
+//BUFG bufg_axi_rst_i  (.O(axi_rst),.I(~frst[0]));
+BUFG bufg_axi_rst_i  (.O(axi_rst),.I(frst_inv));
 BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
    axibram_write #(
@@ -325,6 +342,10 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .PAGES_REL_MASK    (PAGES_REL_MASK),
        .CMDA_EN_REL       (CMDA_EN_REL),
        .CMDA_EN_REL_MASK  (CMDA_EN_REL_MASK),
+        .SDRST_ACT_REL     (SDRST_ACT_REL),  
+        .SDRST_ACT_REL_MASK(SDRST_ACT_REL_MASK),
+        .CKE_EN_REL        (CKE_EN_REL),   
+        .CKE_EN_REL_MASK   (CKE_EN_REL_MASK),
        .EXTRA_REL         (EXTRA_REL),
        .EXTRA_REL_MASK    (EXTRA_REL_MASK)
    ) ddrc_control_i (
@@ -344,7 +365,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .dly_addr         (dly_addr[6:0]),          // output[6:0] 
        .ld_delay         (ld_delay),               // output
        .dly_set          (set),                    // output
-        .cmda_tri         (cmda_tri),               // output
+        .cmda_en          (cmda_en),                // output
+        .ddr_rst          (ddr_rst),                // output
+        .ddr_cke          (ddr_cke),                // output
        .inv_clk_div      (inv_clk_div),            // output
        .dqs_pattern      (dqs_pattern[7:0]),       // output[7:0] 
        .dqm_pattern      (dqm_pattern[7:0]),       // output[7:0] 
@@ -406,6 +429,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .CMD_PAUSE_BITS   (CMD_PAUSE_BITS),
        .CMD_DONE_BIT     (CMD_DONE_BIT)
    ) ddrc_sequencer_i (
+        .SDRST          (SDRST), // output
        .SDCLK          (SDCLK), // output
        .SDNCLK         (SDNCLK), // output
        .SDA            (SDA[14:0]), // output[14:0] // BUG with localparam - fixed
@@ -437,7 +461,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .run_addr       (run_addr[10:0]), // input[10:0] 
        .run_chn        (run_chn[3:0]), // input[3:0] 
-        .run_seq        (run_seq), // input
+        .run_seq        (run_seq), // input #################### DISABLED ####################
+//        .run_seq        (1'b0 && run_seq), // input #################### DISABLED ####################
 //        .run_done       (run_done), // output
        .run_done       (), // output
        .run_busy       (run_busy), // output
@@ -462,7 +487,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .port1_int_page (port1_int_page[1:0]), // input[1:0] 
        .port1_addr     (axiwr_bram_waddr[7:0]), // input[7:0] 
        .port1_data     (axiwr_bram_wdata[31:0]), // input[31:0] 
-        .cmda_tri       (cmda_tri), // input
+        .cmda_en        (cmda_en), // input
+        .ddr_rst        (ddr_rst), // input
+        .ddr_cke        (ddr_cke), // input
        .inv_clk_div    (inv_clk_div), // input
        .dqs_pattern    (dqs_pattern), // input[7:0] 
        .dqm_pattern    (dqm_pattern) // input[7:0] 

--- a/ddrc_test01.xdc
+++ b/ddrc_test01.xdc
@@ -19,6 +19,10 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
 #################################################################################
+#    output                       SDRST, // output SDRST, active low
+set_property IOSTANDARD SSTL15 [get_ports {SDRST}]
+set_property PACKAGE_PIN J4 [get_ports {SDRST}]
 #    output                       SDCLK, // DDR3 clock differential output, positive
 set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDCLK}]
 set_property PACKAGE_PIN K3 [get_ports {SDCLK}]

--- a/ddrc_test01_testbench.sav
+++ b/ddrc_test01_testbench.sav
 [*]
 [*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI
-[*] Thu May 22 08:13:51 2014
+[*] Wed May 28 04:28:28 2014
 [*]
-[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140522015451433.lxt"
+[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140527222157916.lxt"
-[dumpfile_mtime] "Thu May 22 07:55:55 2014"
+[dumpfile_mtime] "Wed May 28 04:22:46 2014"
-[dumpfile_size] 62511235
+[dumpfile_size] 27032362
 [savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"
-[timestart] 103533370
+[timestart] 104472690
-[size] 1830 1145
+[size] 1920 1180
-[pos] -1 -1
+[pos] -1920 108
-*-11.053656 103539375 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-13.962209 104565000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] ddrc_test01_testbench.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.
+[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.
@@ -21,10 +22,10 @@
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.
 [treeopen] ddrc_test01_testbench.simul_axi_master_wdata_i.
-[sst_width] 305
+[sst_width] 210
-[signals_width] 348
+[signals_width] 368
 [sst_expanded] 1
-[sst_vpaned_height] 646
+[sst_vpaned_height] 820
 @28
 ddrc_test01_testbench.RST[0]
 ddrc_test01_testbench.CLK[0]
@@ -698,8 +699,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dq[15:0
 @28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dqsl[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dqsu[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.iclk[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.iclk_pre[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_a[29:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.in_ba[5:0]
@@ -735,16 +734,14 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dq[
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dqs[7:0]
 @1401200
 -phy_top_i
-@800200
+@c00200
 -mmcm_phase_cntr
 @28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbin[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbout[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfboutb[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkin[0]
-@29
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0[0]
-@28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0b[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1b[0]
@@ -778,7 +775,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_ph
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psincdec[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.pwrdwn[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.rst[0]
-@1000200
+@1401200
 -mmcm_phase_cntr
 @c00200
 -idelay_ctrl_i
@@ -794,8 +791,8 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_
 ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.busy[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.busy_r[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.clk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.cmda_en[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.cmda_en_r[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.cmda_tri[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dly_addr[6:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.dly_data[7:0]
@@ -884,6 +881,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.we[0]
 @c00200
 -phy_cmd_i
 @28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDRST[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.DQSL[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.DQSU[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.NDQSL[0]
@@ -912,6 +910,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.buf_wdata[63:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.buf_wr[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.clk_div[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.clk_in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.cmda_en[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.cmda_tri[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.dly_addr[6:0]
@@ -969,6 +968,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_ps_rdy[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rcw[5:0]
 @28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rcw_in[2:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rdata[63:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rdata_r[63:0]
@@ -1011,6 +1011,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDD[15:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDNCLK[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDODT[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDRAS[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDRST[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDWE[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf1_rdata[63:0]
@@ -1048,11 +1049,17 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd1_data[31:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd1_we[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_addr[9:0]
-@28
+@800028
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
+@28
+(0)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
+(1)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
+(2)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
+@1001200
+-group_end
+@28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_fetch[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_sel[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmda_tri[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.dly_addr[6:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.dly_data[7:0]
@@ -1097,6 +1104,10 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_we[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.ps_out[7:0]
 @28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.ps_rdy[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.ren0[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.ren1[0]
+@28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.rst[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.rst_in[0]
 @22
@@ -1114,6 +1125,71 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.set[0]
 @1401200
 -ddrc_sequencer
+@800200
+-ddr_sequencer_i_selected
+@29
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCLK[0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCKE[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDBA[2:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDA[14:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDRAS[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCAS[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDWE[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.DQSL[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.DQSU[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.NDQSL[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.NDQSU[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDDML[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDDMU[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDD[15:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDODT[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDRST[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.mclk[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_addr[9:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_clk[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_data[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_we[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_addr[9:0]
+@800028
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
+@28
+(0)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
+(1)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
+(2)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
+@1001200
+-group_end
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_fetch[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_cntr[5:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_len[5:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_nop[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_word[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.ren0[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_addr[10:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_busy[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_done[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq_d[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0]
+@1000200
+-ddr_sequencer_i_selected
 @c00200
 -ddrc_test01
 @28
@@ -1205,7 +1281,6 @@ ddrc_test01_testbench.ddrc_test01_i.axiwr_bram_wstb[3:0]
 ddrc_test01_testbench.ddrc_test01_i.axiwr_dev_busy[0]
 ddrc_test01_testbench.ddrc_test01_i.axiwr_dev_ready[0]
 ddrc_test01_testbench.ddrc_test01_i.axiwr_start_burst[0]
-ddrc_test01_testbench.ddrc_test01_i.cmda_tri[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.dly_addr[6:0]
 ddrc_test01_testbench.ddrc_test01_i.dly_data[7:0]
@@ -1348,7 +1423,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.data_out[13:0]
 ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.rst[0]
 @1401200
 -wresp_i
-@800200
+@c00200
 -waddr_i
 @28
 ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.clk[0]
@@ -1374,7 +1449,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wa[3:0]
 @28
 ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.we[0]
 ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wem[0]
-@1000200
+@1401200
 -waddr_i
 @c00200
 -wdata_i
@@ -1410,5 +1485,132 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.we[0]
 ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wem[0]
 @1401200
 -wdata_i
+@c00200
+-axibram_read_i
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.aclk[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.ar_half_full[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.ar_nempty[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.araddr[31:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.araddr_out[12:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arburst[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arburst_out[1:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arid[11:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arid_out[11:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arlen[3:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arlen_out[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arready[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arsize[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arsize_out[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.arvalid[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.bram_raddr[12:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.bram_rclk[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.bram_rdata[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.bram_reg_re_0[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.bram_reg_re_w[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.bram_regen[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.bram_ren[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.dev_ready[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.last_in_burst_0[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.last_in_burst_1[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.last_in_burst_d_w[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.last_in_burst_w[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.next_rd_address_w[12:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.pre_araddr[12:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.pre_last_in_burst_r[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.pre_left_zero_w[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.pre_rid0[11:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.pre_rid[11:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.pre_rvalid_w[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.rburst[1:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.rdata[31:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.read_address[12:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.read_in_progress[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.read_in_progress_d[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.read_in_progress_d_w[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.read_in_progress_or[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.read_in_progress_w[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.read_left[3:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.rid[11:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.rlast[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.rlen[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.rready[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.rresp[1:0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.rst[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.rvalid[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_burst[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_read_burst_0[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_read_burst_1[0]
+ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_read_burst_w[0]
+@1401200
+-axibram_read_i
+@22
+ddrc_test01_testbench.registered_rdata[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.busy[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.locked[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.ps_out[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.ps_rdy[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.rdata[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.run_busy[0]
+ddrc_test01_testbench.ddrc_test01_i.select_port0[0]
+ddrc_test01_testbench.ddrc_test01_i.select_status[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.axird_pre_araddr[12:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.axird_start_burst[0]
+@22
+ddrc_test01_testbench.GLOBAL_WRITE_ID[11:0]
+@c00200
+-cmd0_buf_i
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.data_in[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.data_out[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.raddr[9:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.rclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.regen[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.ren[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.waddr[9:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.wclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.we[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.web[3:0]
+@1401200
+-cmd0_buf_i
+@22
+ddrc_test01_testbench.set_mrs.data[31:0]
+ddrc_test01_testbench.set_mrs.cmd_addr[31:0]
+ddrc_test01_testbench.set_mrs.data[31:0]
+ddrc_test01_testbench.set_mrs.mr0[17:0]
+ddrc_test01_testbench.set_mrs.mr1[17:0]
+ddrc_test01_testbench.set_mrs.mr2[17:0]
+ddrc_test01_testbench.set_mrs.mr3[17:0]
+@28
+ddrc_test01_testbench.set_mrs.reset_dll[0]
 [pattern_trace] 1
 [pattern_trace] 0
--- a/ddrc_test01_testbench.tf
+++ b/ddrc_test01_testbench.tf
@@ -72,14 +72,19 @@ module  ddrc_test01_testbench #(
    parameter PAGES_REL_MASK =      'h3ff,  // address mask to set DQM and DQS patterns
    parameter CMDA_EN_REL =         'h022,  // address to enable('h823)/disable('h822) command/address outputs  
    parameter CMDA_EN_REL_MASK =    'h3fe,  // address mask for command/address outputs
-    parameter EXTRA_REL =           'h024,  // address to set extra parameters (currently just inv_clk_div)
+    parameter SDRST_ACT_REL =       'h024,  // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory  
-    parameter EXTRA_REL_MASK =      'h3ff,   // address mask for extra parameters
+    parameter SDRST_ACT_REL_MASK =  'h3fe,  // address mask for reset DDR3
+    parameter CKE_EN_REL =          'h026,  // address to enable('h827)/disable('h826) CKE signal to memory   
+    parameter CKE_EN_REL_MASK =     'h3fe,  // address mask for command/address outputs
+    parameter EXTRA_REL =           'h028,  // address to set extra parameters (currently just inv_clk_div)
+    parameter EXTRA_REL_MASK =      'h3ff,  // address mask for extra parameters
    // simulation-specific parameters
    parameter integer AXI_RDADDR_LATENCY=2,
    parameter integer AXI_WRADDR_LATENCY=4,
    parameter integer AXI_WRDATA_LATENCY=1,
-    parameter integer AXI_TASK_HOLD=1.0 
+    parameter integer AXI_TASK_HOLD=1.0,
+    parameter integer ADDRESS_NUMBER=15 
 )();
 `ifdef IVERILOG              
 //    $display("IVERILOG is defined");
@@ -90,14 +95,25 @@ module  ddrc_test01_testbench #(
 `endif
 `define DEBUG_WR_SINGLE 1  
  // DDR3 signals
+// SuppressWarnings VEditor
+  wire        SDRST;
+// SuppressWarnings VEditor
  wire        SDCLK;  // output
+// SuppressWarnings VEditor
  wire        SDNCLK; // output
-  wire [14:0] SDA;    // output[14:0] 
+// SuppressWarnings VEditor
+  wire [ADDRESS_NUMBER-1:0] SDA;    // output[14:0] 
+// SuppressWarnings VEditor
  wire [ 2:0] SDBA;   // output[2:0] 
+// SuppressWarnings VEditor
  wire        SDWE;   // output
+// SuppressWarnings VEditor
  wire        SDRAS;  // output
+// SuppressWarnings VEditor
  wire        SDCAS;  // output
+// SuppressWarnings VEditor
  wire        SDCKE;  // output
+// SuppressWarnings VEditor
  wire        SDODT;  // output
  wire [15:0] SDD;    // inout[15:0] 
  wire        SDDML;  // inout
@@ -125,14 +141,18 @@ module  ddrc_test01_testbench #(
  reg [ 3:0] WSTRB_IN_r;
  reg        WLAST_IN_r;
-  wire [ 9:0] SIMUL_AXI_ADDR_W; 
  // SuppressWarnings VEditor : assigned in $readmem() system task
+  wire [ 9:0] SIMUL_AXI_ADDR_W; 
+  // SuppressWarnings VEditor
  wire        SIMUL_AXI_MISMATCH;
+  // SuppressWarnings VEditor
  reg  [31:0] SIMUL_AXI_READ;
+  // SuppressWarnings VEditor
  reg  [ 9:0] SIMUL_AXI_ADDR;
+  // SuppressWarnings VEditor
  reg         SIMUL_AXI_FULL; // some data available
+  reg  [31:0] registered_rdata;
  reg        CLK;
  reg        RST;
@@ -172,7 +192,7 @@ module  ddrc_test01_testbench #(
  wire [3:0]  arlen;
  wire [2:0]  arsize;
  wire [1:0]  arburst;
-  // SuppressWarnings VEditor : assigned in $readmem() system task
+  // SuppressWarnings VEditor : assigned in $readmem(14) system task
  wire [3:0]  arcache;
  // SuppressWarnings VEditor : assigned in $readmem() system task
  wire [2:0]  arprot;
@@ -216,7 +236,6 @@ module  ddrc_test01_testbench #(
  wire        bready;
 always #(CLKIN_PERIOD/2) CLK <= ~CLK;
  initial begin
 `ifdef IVERILOG              
    $display("IVERILOG is defined");
@@ -248,6 +267,26 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
 //    test_axi_1;
    // read memory
 //    test_axi_2;
+    read_status; // ps ready goes false with some delay
+//    read_status;
+    wait_phase_shifter_ready;
+//    repeat (40) begin
+//    read_status;
+//    end
+    enable_cmda(1);
+    repeat (16) @(posedge CLK) ;
+    activate_sdrst(0); // was enabled at system reset
+    repeat (16) @(posedge CLK) ;
+    enable_cke(1);
+    repeat (16) @(posedge CLK) ;
+    set_mrs(1);
+    #100;
+//    $finish;
+    run_sequence(0);
+//#100;
+    $display("finish testbench 0");
+    $finish;
    repeat (512) @(posedge CLK) ;
 #100;
@@ -368,12 +407,17 @@ assign bresp=                              ddrc_test01_i.ps7_i.MAXIGP0BRESP;
        .PAGES_REL_MASK        (PAGES_REL_MASK),
        .CMDA_EN_REL           (CMDA_EN_REL),
        .CMDA_EN_REL_MASK      (CMDA_EN_REL_MASK),
+        .SDRST_ACT_REL         (SDRST_ACT_REL),  
+        .SDRST_ACT_REL_MASK    (SDRST_ACT_REL_MASK),
+        .CKE_EN_REL            (CKE_EN_REL),   
+        .CKE_EN_REL_MASK       (CKE_EN_REL_MASK),
        .EXTRA_REL             (EXTRA_REL),
        .EXTRA_REL_MASK        (EXTRA_REL_MASK)
    ) ddrc_test01_i (
-        .SDCLK   (SDCLK), // output
+        .SDRST   (SDRST), // DDR3 reset (active low)
-        .SDNCLK  (SDNCLK), // output
+        .SDCLK   (SDCLK), // output 
+        .SDNCLK  (SDNCLK), // outputread_and_wait(BASEADDR_STATUS)
        .SDA     (SDA[14:0]), // output[14:0] 
        .SDBA    (SDBA[2:0]), // output[2:0] 
        .SDWE    (SDWE), // output
@@ -492,7 +536,7 @@ simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
    .clk(CLK),
    .reset(RST), //input         reset,
    .delay(B_LAG), //input  [3:0]  delay,
-    .valid(bvalid), // input         valid,
+    .valid(bvalid), // input       ADDRESS_NUMBER+2:0  valid,
    .ready(bready)  //output        ready
    );
@@ -515,8 +559,11 @@ simul_axi_read simul_axi_read_i(
 //  Tasks
 // top simulation tasks
-// base addresses  
+// base addresses 
+// SuppressWarnings VEditor
    localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000  << 2
+// SuppressWarnings VEditor
    localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
    localparam BASEADDR_CMD0 =     CMD0_ADDR << 2;     // 'h0800 << 2 = 'h2000
 //    localparam BASEADDR_CTRL =     CONTROL_ADDR << 2;
@@ -525,14 +572,21 @@ simul_axi_read simul_axi_read_i(
    localparam BASEADDR_DLY_LD =  BASEADDR_CTRL | (DLY_LD_REL <<2);  // 'h080, address to generate delay load
    localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2);  // 'h070, address to generate delay set
    localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2);  // 'h000, address to set sequnecer channel and  run (4 LSB-s - channel)
+// SuppressWarnings VEditor
    localparam BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2); // 'h020, address to set DQM and DQS patterns (16'h0055)
+// SuppressWarnings VEditor
    localparam BASEADDR_PAGES =   BASEADDR_CTRL | (PAGES_REL<<2);    // 'h021, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
    localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2);  // 'h022, address to enable('h823)/disable('h822) command/address outputs  
-    localparam BASEADDR_EXTRA =   BASEADDR_CTRL | (EXTRA_REL<<2);    // 'h024, address to set extra parameters (currently just inv_clk_div)
+    localparam BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2); // address to activate('h825)/deactivate('h824) active-low reset signal to DDR3 memory     
+    localparam BASEADDR_CKE_EN =  BASEADDR_CTRL | (CKE_EN_REL<<2);   //   
+// SuppressWarnings VEditor
+    localparam BASEADDR_EXTRA =   BASEADDR_CTRL | (EXTRA_REL<<2);    // 'h028, address to set extra parameters (currently just inv_clk_div)
    localparam BASEADDRESS_LANE0 = BASEADDR_DLY_LD;  
    localparam BASEADDRESS_LANE1 = BASEADDR_DLY_LD+('h20<<2);  
    localparam BASEADDRESS_CMDA  = BASEADDR_DLY_LD+('h40<<2);
    localparam BASEADDRESS_PHASE = BASEADDR_DLY_LD+('h60<<2);
+    localparam PSHIFTER_RDY_MASK = 'h100;
    localparam DLY_LANE0= 152'h74737271706f6e6d6c7574737271706f6e6d6c; // idelay dqs, idelay dq[7:0, odelay dqm, odelay ddqs, odelay dq[7:0]
@@ -540,7 +594,391 @@ simul_axi_read simul_axi_read_i(
    localparam DLY_CMDA=  256'h5f5e5d5c5b5a59585756555453525150004e4b4c4b4a49484746454443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
 //    localparam DLY_PHASE= 8'h25; // mmcm fine phase shift
    localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
+    task run_sequence;
+        input [7:0] start_addr; // word
+// BASEADDR_RUN_CHN        
+        begin
+            $display("run_sequence 0 @ %t",$time);
+            axi_write_single(BASEADDR_RUN_CHN, {24'h0,start_addr});
+            $display("run_sequence 1 @ %t",$time);
+            #1000; // 90; // 92 - does not work ?
+            $display("run_sequence 2 @ %t",$time);
+        end
+    endtask
+    task enable_cmda;
+        input en;
+        begin
+            if (en) 
+                axi_write_single(BASEADDR_CMDA_EN+4, 0);
+            else 
+                axi_write_single(BASEADDR_CMDA_EN, 0);
+        end
+    endtask
+    task enable_cke;
+        input en;
+        begin
+            if (en) 
+                axi_write_single(BASEADDR_CKE_EN+4, 0);
+            else 
+                axi_write_single(BASEADDR_CKE_EN, 0);
+        //BASEADDR_CMDA_EN
+        end
+    endtask
+    task activate_sdrst;
+        input en;
+        begin
+            if (en) 
+                axi_write_single(BASEADDR_SDRST_ACT+4, 0);
+            else 
+                axi_write_single(BASEADDR_SDRST_ACT, 0);
+        //BASEADDR_CMDA_EN
+        end
+    endtask
+    task set_mrs;
+        input reset_dll;
+//        reg [ADDRESS_NUMBER+2:0] mr0;
+//        reg [ADDRESS_NUMBER+2:0] mr1;
+//        reg [ADDRESS_NUMBER+2:0] mr2;
+//        reg [ADDRESS_NUMBER+2:0] mr3;
+        reg [17:0] mr0;
+        reg [17:0] mr1;
+        reg [17:0] mr2;
+        reg [17:0] mr3;
+        reg [31:0] cmd_addr;
+        reg [31:0] data;
+        begin
+            mr0 <= ddr3_mr0 (
+               1'h0,      //       pd; // precharge power down 0 - dll off (slow exit), 1 - dll on (fast exit) 
+               3'h2,      // [2:0] wr; // write recovery (encode ceil(tWR/tCK)) // 3'b010:  6
+               reset_dll, //       dll_rst; // 1 - dll reset (self clearing bit)
+               4'h2,      // [3:0] cl; // CAS latency: // 0010:  5
+               1'h0,      //       bt; // read burst type: 0 sequential (nibble), 1 - interleaverun_seqd
+               2'h0);       // [1:0] bl; // burst length: // 2'b00 - fixed BL8
+             mr1 <= ddr3_mr1 (
+                1'h0,     //       qoff; // output enable: 0 - DQ, DQS operate in normal mode, 1 - DQ, DQS are disabled
+                1'h0,     //       tdqs; // termination data strobe (for x8 devices) 0 - disabled, 1 - enabled
+                3'h2,     // [2:0] rtt;  // on-die termination resistance: //  3'b010 - RZQ/2 (120 Ohm)
+                1'h0,     //       wlev; // write leveling
+                2'h0,     //       ods;  // output drive strength: //  2'b00 - RZQ/6 - 40 Ohm
+                2'h0,     // [1:0] al;   // additive latency: 2'b00 - disabled (AL=0)
+                1'b0);    //       dll;  // 0 - DLL enabled (normal), 1 - DLL disabled
+             mr2 <= ddr3_mr2 (
+                2'h0,     // [1:0] rtt_wr; // Dynamic ODT : //  2'b00 - disabled, 2'b01 - RZQ/4 = 60 Ohm, 2'b10 - RZQ/2 = 120 Ohm
+                1'h0,     //       srt;    // Self-refresh temperature 0 - normal (0-85C), 1 - extended (<=95C)
+                1'h0,     //       asr;    // Auto self-refresh 0 - disabled (manual), 1 - enabled (auto)
+                3'h0);    // [2:0] cwl;    // CAS write latency:3'b000  5CK (tCK >= 2.5ns), 3'b001  6CK (1.875ns <= tCK < 2.5ns)
+             mr3 <= ddr3_mr3 (
+                1'h0,     //       mpr;    // MPR mode: 0 - normal, 1 - dataflow from MPR
+                2'h0);    // [1:0] mpr_rf; // MPR read function: 2'b00: predefined pattern 0101...
+             cmd_addr <= BASEADDR_CMD0;   
+             wait (~CLK);
+             data <=  encode_seq_word(
+                mr2[14:0],              // [14:0] phy_addr_in;
+                mr2[17:15],             // [ 2:0] phy_bank_in; //TODO: debug!
+                3'b111,                               // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive
+                1'b0,                                 //        phy_odt_in; // may be optimized?
+                1'b1,                                 // phy_cke_in; // may be optimized?
+                1'b0,                                 // phy_sel_in; // first/second half-cycle, oter will be nop (cke+odt applicable to both)
+                1'b0,                                 // phy_dq_en_in;
+                1'b0,                                 // phy_dqs_ddrc_sequenceren_in;
+                1'b0,                                 // phy_dci_en_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+                1'b0,                                 // phy_buf_wr;   // connect to external buffer
+                1'b0);                               // phy_buf_rd;   // connect to external buffer
+             wait (CLK);
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+             wait (~CLK);                
+//             data <= encode_seq_skip(2,0);
+             data <= encode_seq_skip(1,0);  // 6 cycles between mrs commands
+             wait (CLK);                
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+             wait (~CLK);
+             data <=  encode_seq_word(
+                mr3[14:0],              // [14:0] phy_addr_in;
+                mr3[17:15],             // [ 2:0] phy_bank_in; //TODO: debug!
+                3'b111,                               // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive
+                1'b0,                                 //        phy_odt_in; // may be optimized?
+                1'b1,                                 // phy_cke_in; // may be optimized?
+                1'b0,                                 // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both)
+                1'b0,                                 // phy_dq_eddrc_sequencern_in;
+                1'b0,                                 // phy_dqs_en_in;
+                1'b0,                                 // phy_dci_en_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+                1'b0,                                 // phy_buf_wr;   // connect to external buffer
+                1'b0);                               // phy_buf_rd;   // connect to external buffer
+             wait (CLK);                
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+             wait (~CLK);                
+//             data <= encode_seq_skip(2,0); // TODO: function - does not check arguments number
+             data <= encode_seq_skip(0,0); // 5 cycles between mrs commands (next command has phy_sel_in == 1)
+             wait (CLK);                
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+             wait (~CLK);
+             data <=  encode_seq_word(
+                mr1[14:0],              // [14:0] phy_addr_in;
+                mr1[17:15],             // [ 2:0] phy_bank_in; //TODO: debug!
+                3'b111,                               // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive
+                1'b0,                                 //        phy_odt_in; // may be optimized?
+                1'b1,                                 // phy_cke_in; // may be optimized?
+                1'b1,                                 // phy_sel_in == 1 (test); // first/second half-cycle,
+                1'b0,                                 // phy_dq_en_in;
+                1'b0,                                 // phy_dqs_en_in;
+                1'b0,                                 // phy_dci_en_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+                1'b0,                                 // phy_buf_wr;   // connect to external buffer
+                1'b0);                               // phy_buf_rd;   // connect to external buffer
+             wait (CLK);                
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+             wait (~CLK);                
+             data <= encode_seq_skip(2,0); //  7 cycles between mrs commands ( prev. command had phy_sel_in == 1)
+             wait (CLK);                
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+             wait (~CLK);
+             data <=  encode_seq_word(
+                mr0[14:0],              // [14:0] phy_addr_in;
+                mr0[17:15],             // [ 2:0] phy_bank_in; //TODO: debug!
+                3'b111,                               // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive
+                1'b0,                                 //        phy_odt_in; // may be optimized?
+                1'b1,                                 // phy_cke_in; // may be optimized?
+                1'b0,                                 // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both)
+                1'b0,                                 // phy_dq_en_in;
+                1'b0,                                 // phy_dqs_en_in;
+                1'b0,                                 // phy_dci_en_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+                1'b0,                                 // phy_buf_wr;   // connect to external buffer
+                1'b0);                                // phy_buf_rd;   // connect to external buffer
+             wait (CLK);                
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+             wait (~CLK);                
+             data <= encode_seq_skip(10,1);
+             wait (CLK);                
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+// TODO: Function of function does not work - debug             
+/*             
+             axi_write_single(cmd_addr,
+              encode_seq_word(
+                mr2[14:0],              // [14:0] phy_addr_in;
+                mr2[17:15],             // [ 2:0] phy_bank_in; //TODO: debug!
+                3'b111,                               // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive
+                1'b0,                                 //        phy_odt_in; // may be optimized?
+                1'b1,                                 // phy_cke_in; // may be optimized?
+                1'b0,                                 // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both)
+                1'b0,                                 // phy_dq_en_in;
+                1'b0,                                 // phy_dqs_en_in;
+                1'b0,                                 // phy_dci_en_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+                1'b0,                                 // phy_buf_wr;   // connect to external buffer
+                1'b0));                               // phy_buf_rd;   // connect to external buffer
+ */            
+        end
+    endtask
+    function [31:0] encode_seq_word;
+        input               [14:0] phy_addr_in;  // also provides pause length when the command is NOP
+        input               [ 2:0] phy_bank_in;
+        input               [ 2:0] phy_rcw_in; // {ras,cas,we}
+        input                      phy_odt_in; // may be optimized?
+        input                      phy_cke_inv; // invert CKE 
+        input                      phy_sel_in; // fitst/second half-cycle, oter will be nop (cke+odt applicable to both)
+        input                      phy_dq_en_in;
+        input                      phy_dqs_en_in;
+        input                      phy_dci_en_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+        input                      phy_buf_wr;   // connect to external buffer
+        input                      phy_buf_rd;   // connect to external buffer
+        begin
+            encode_seq_word={
+            phy_addr_in[14:0],
+            phy_bank_in[2:0],
+            phy_rcw_in[2:0],      // {ras,cas,we}, positive logic (3'b0 - NOP)
+            phy_odt_in,      // may be optimized?
+            phy_cke_inv,     // invert CKE
+            phy_sel_in,      // first/second half-cycle, other will be nop (cke+odt applicable to both)
+            phy_dq_en_in,    //phy_dq_tri_in,   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
+            phy_dqs_en_in,   //phy_dqs_tri_in,  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
+            phy_dci_en_in,   //phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+            phy_buf_wr,      // connect to external buffer (but only if not paused)
+            phy_buf_rd,      // connect to external buffer (but only if not paused)
+            3'h0      // Reserved for future use
+            };
+        end
+    endfunction
+//    parameter CMD_PAUSE_BITS=       6, // numer of (address) bits to encode pause
+//    parameter CMD_DONE_BIT=         6  // bit number (address) to signal sequence done
+    function [31:0] encode_seq_skip;
+        input [CMD_PAUSE_BITS-1:0] skip;
+        input done;
+        begin
+            encode_seq_skip={
+            {14-CMD_DONE_BIT{1'b0}},
+            done,
+            skip[CMD_PAUSE_BITS-1:0],
+            3'b0, //phy_bank_in[2:0],
+            3'b0, // phy_rcw_in[2:0],      // {ras,cas,we}
+            1'b0, // phy_odt_in,      // may be optimized?
+            1'b0, // phy_cke_in,      // may be optimized?
+            1'b0, // phy_sel_in,      // fitst/second half-cycle, oter will be nop (cke+odt applicable to both)
+            1'b0, // phy_dq_en_in, //phy_dq_tri_in,   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
+            1'b0, // phy_dqs_en_in, //phy_dqs_tri_in,  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
+            1'b0, // phy_dci_en_in, //phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+            1'b0, // phy_buf_wr,   // connect to external buffer (but only if not paused)
+            1'b0, // phy_buf_rd,    // connect to external buffer (but only if not paused)
+            3'h0      // Reserved for future use
+            };
+        end
+    endfunction
+    function [ADDRESS_NUMBER+2:0] ddr3_mr0;
+        input       pd; // precharge power down 0 - dll off (slow exit), 1 - dll on (fast exit) 
+        input [2:0] wr; // write recovery:
+                        // 3'b000: 16
+                        // 3'b001:  5
+                        // 3'b010:  6
+                        // 3'b011:  7
+                        // 3'b100:  8
+                        // 3'b101: 10
+                        // 3'b110: 12
+                        // 3'b111: 14
+        input       dll_rst; // 1 - dll reset (self clearing bit)
+        input [3:0] cl; // CAS latency:
+                        // 0000: reserved                   
+                        // 0010:  5                   
+                        // 0100:  6                   
+                        // 0110:  7                 
+                        // 1000:  8                 
+                        // 1010:  9                 
+                        // 1100: 10                   
+                        // 1110: 11                   
+                        // 0001: 12                  
+                        // 0011: 13                  
+                        // 0101: 14
+        input       bt; // read burst type: 0 sequential (nibble), 1 - interleaved
+        input [1:0] bl; // burst length:
+                        // 2'b00 - fixed BL8
+                        // 2'b01 - 4 or 8 on-the-fly by A12                                     
+                        // 2'b10 - fixed BL4 (chop)
+                        // 2'b11 - reserved
+        begin
+          ddr3_mr0 = {
+              3'b0,
+              {ADDRESS_NUMBER-13{1'b0}},
+              pd,       // MR0.12 
+              wr,       // MR0.11_9
+              dll_rst,  // MR0.8
+              1'b0,     // MR0.7
+              cl[3:1],  // MR0.6_4
+              bt,       // MR0.3
+              cl[0],    // MR0.2
+              bl[1:0]}; // MR0.1_0
+        end
+    endfunction
+    function [ADDRESS_NUMBER+2:0] ddr3_mr1;
+        input       qoff; // output enable: 0 - DQ, DQS operate in normal mode, 1 - DQ, DQS are disabled
+        input       tdqs; // termination data strobe (for x8 devices) 0 - disabled, 1 - enabled
+        input [2:0] rtt;  // on-die termination resistance:
+                          //  3'b000 - disabled
+                          //  3'b001 - RZQ/4 (60 Ohm)
+                          //  3'b010 - RZQ/2 (120 Ohm)
+                          //  3'b011 - RZQ/6 (40 Ohm)
+                          //  3'b100 - RZQ/12(20 Ohm)
+                          //  3'b101 - RZQ/8 (30 Ohm)
+                          //  3'b11x - reserved
+        input       wlev; // write leveling
+        input [1:0] ods;  // output drive strength:
+                          //  2'b00 - RZQ/6 - 40 Ohm
+                          //  2'b01 - RZQ/7 - 34 Ohm
+                          //  2'b1x - reserved
+        input [1:0] al;   // additive latency:
+                          //  2'b00 - disabled (AL=0)
+                          //  2'b01 - AL=CL-1;
+                          //  2'b10 - AL=CL-2
+                          //  2'b11 - reserved
+        input       dll;  // 0 - DLL enabled (normal), 1 - DLL disabled
+        begin
+            ddr3_mr1 = {
+              3'h1,
+              {ADDRESS_NUMBER-13{1'b0}},
+              qoff,       // MR1.12 
+              tdqs,       // MR1.11
+              1'b0,       // MR1.10
+              rtt[2],     // MR1.9
+              1'b0,       // MR1.8
+              wlev,       // MR1.7 
+              rtt[1],     // MR1.6 
+              ods[1],     // MR1.5 
+              al[1:0],    // MR1.4_3 
+              rtt[0],     // MR1.2 
+              ods[0],     // MR1.1 
+              dll};       // MR1.0 
+        end                            
+    endfunction
+    function [ADDRESS_NUMBER+2:0] ddr3_mr2;
+        input [1:0] rtt_wr; // Dynamic ODT :
+                            //  2'b00 - disabled
+                            //  2'b01 - RZQ/4 = 60 Ohm
+                            //  2'b10 - RZQ/2 = 120 Ohm
+                            //  2'b11 - reserved
+        input       srt;    // Self-refresh temperature 0 - normal (0-85C), 1 - extended (<=95C)
+        input       asr;    // Auto self-refresh 0 - disabled (manual), 1 - enabled (auto)
+        input [2:0] cwl;    // CAS write latency:
+                            //  3'b000  5CK (           tCK >= 2.5ns)  
+                            //  3'b001  6CK (1.875ns <= tCK < 2.5ns)  
+                            //  3'b010  7CK (1.5ns   <= tCK < 1.875ns)  
+                            //  3'b011  8CK (1.25ns  <= tCK < 1.5ns)  
+                            //  3'b100  9CK (1.071ns <= tCK < 1.25ns)  
+                            //  3'b101 10CK (0.938ns <= tCK < 1.071ns)  
+                            //  3'b11x reserved  
+        begin
+            ddr3_mr2 = {
+              3'h2,
+              {ADDRESS_NUMBER-11{1'b0}},
+              rtt_wr[1:0], // MR2.10_9
+              1'b0,        // MR2.8
+              srt,         // MR2.7
+              asr,         // MR2.6
+              cwl[2:0],    // MR2.5_3
+              3'b0};       // MR2.2_0 
+        end                            
+    endfunction
+    function [ADDRESS_NUMBER+2:0] ddr3_mr3;
+        input       mpr;    // MPR mode: 0 - normal, 1 - dataflow from MPR
+        input [1:0] mpr_rf; // MPR read function:
+                            //  2'b00: predefined pattern 0101...
+                            //  2'b1x, 2'bx1 - reserved
+        begin
+            ddr3_mr3 = {
+              3'h3,
+              {ADDRESS_NUMBER-3{1'b0}},
+              mpr,          // MR3.2
+              mpr_rf[1:0]}; // MR3.1_0 
+        end                            
+    endfunction
+    reg [7:0] target_phase=0;
 // initialize delays
    task axi_set_delays;
@@ -565,11 +1003,60 @@ simul_axi_read simul_axi_read_i(
        input [PHASE_WIDTH-1:0] phase;
        begin
            axi_write_single(BASEADDRESS_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase});
+            target_phase <= phase;
+        end
+    endtask
+/*
+    assign rdata={21'b0,run_busy,locked,ps_rdy,ps_out[7:0]};
+*/    
+    task wait_phase_shifter_ready;
+        begin
+            read_status;
+            while (((registered_rdata & PSHIFTER_RDY_MASK) == 0) || (((registered_rdata ^ {24'h0,target_phase}) & 'hff) != 0)) read_status;
        end
    endtask
+    task read_status;
+        begin
+            read_and_wait(BASEADDR_STATUS);
+        end    
+    endtask
+/*
+   // read memory
+    task test_axi_2;
+        integer i; //,j;
+        begin
+            axi_set_rd_lag(0);
+            for (i=0;i<1024;i=i+16) begin
+                axi_read_addr(
+                    i,    // id
+                    i<<2, // addr
+                    4'hf, // len
+                    1     // burst type - increment
+                );
+                if ((i==256) || (i==384)) begin
+                    repeat (512) @(posedge CLK) ;
+                end
+                if (( i & 'h7f)==0) begin
+                  if (( i & 'h80)==0) axi_set_rd_lag(1);
+                  else axi_set_rd_lag(0);
+                end
+            end
+//            assign aaa=bbb; // task internals were not parsed
+        end
+    endtask    task read_status;
+        begin
+            read_and_wait(BASEADDR_STATUS);
+        end    
+    endtask
+*/
+// Low-level tasks 
-// Low-level tasks     
    task axi_set_rd_lag;
        input [3:0] lag;
        begin
@@ -587,6 +1074,23 @@ simul_axi_read simul_axi_read_i(
    endtask
    reg [11:0] GLOBAL_WRITE_ID=0;
+    reg [11:0] GLOBAL_READ_ID=0;
+    task read_and_wait;
+    input [31:0] address;
+    begin
+        axi_read_addr(
+            GLOBAL_READ_ID,    // id
+            address & 32'hfffffffc, // addr
+            4'h0, // len - single
+            1     // burst type - increment
+            );
+        GLOBAL_READ_ID <= GLOBAL_READ_ID+1;
+        wait (!CLK && rvalid && rready);
+        wait (CLK);
+        registered_rdata <= rdata;
+    end
+    endtask
    task axi_write_single; // address in bytes, not words
        input [31:0] address;
@@ -681,7 +1185,7 @@ simul_axi_read simul_axi_read_i(
            #0.1;
        end
    endtask
+// SuppressWarnings VEditor - not yet used
    task axi_write_data;
        input [11:0] id;
        input [31:0] data;
@@ -704,7 +1208,10 @@ simul_axi_read simul_axi_read_i(
        end
    endtask
-    task axi_read_addr;
+    task axi_read_addr;`ifndef IVERILOG
+(* dont_touch = "true" *)
+`endif
        input [11:0] id;
        input [31:0] addr;
        input [ 3:0] len;

--- a/phy/cmd_addr.v
+++ b/phy/cmd_addr.v
@@ -56,7 +56,7 @@ reg  [2*ADDRESS_NUMBER-1:0] in_a_r=0;
 reg  [5:0] in_ba_r=0;
 reg  [1:0] in_we_r=2'h3, in_ras_r=2'h3, in_cas_r=2'h3, in_cke_r=2'h3, in_odt_r=2'h0;
 //reg  [1:0] in_tri_r=2'h0; // or tri-state on reset?
-reg  in_tri_r=1'b0; // or tri-state on reset?
+reg  in_tri_r=1'b1; // or tri-state on reset?
 // Preventing register duplication
 (* keep = "true" *) reg  [7:0] dly_data_r=0; 
 (* keep = "true" *) reg        set_r=0;
@@ -78,7 +78,7 @@ always @ (posedge clk_div or posedge rst) begin
        in_a_r <= 0; in_ba_r <= 6'b0;
        in_we_r <= 2'h3; in_ras_r <= 2'h3; in_cas_r <= 2'h3; in_cke_r <= 2'h3; in_odt_r <= 2'h0;
 //        in_tri_r <= 2'h0; // or tri-state on reset?
-        in_tri_r <= 1'b0; // or tri-state on reset?
+        in_tri_r <= 1'b1; // or tri-state on reset?
        dly_data_r<=8'b0;set_r<=1'b0;
        ld_dly_cmd <= 8'b0; ld_dly_addr <= 0;
    end else begin

--- a/phy/ddrc_sequencer.v
+++ b/phy/ddrc_sequencer.v
@@ -47,6 +47,7 @@ module  ddrc_sequencer   #(
    parameter CMD_DONE_BIT=         6
 )(
    // DDR3 interface
+    output                       SDRST, // DDR3 reset (active low)
    output                       SDCLK, // DDR3 clock differential output, positive
    output                       SDNCLK,// DDR3 clock differential output, negative
    output  [ADDRESS_NUMBER-1:0] SDA,   // output address ports (14:0) for 4Gb device
@@ -81,7 +82,7 @@ module  ddrc_sequencer   #(
 // Controller run interface, posedge mclk
    input               [10:0]   run_addr, // controller sequencer start address (0..11'h3ff - cmd0, 11'h400..11'h7ff - cmd1)
    input                [3:0]   run_chn,  // data channel to use
-    input                        run_seq,  // start controller sequence 
+    input                        run_seq,  // start controller sequence (will and with !ddr_rst for stable mclk)
    output                       run_done, // controller sequence finished
    output                       run_busy, // controller sequence in progress  
 // inteface to control I/O delays and mmcm
@@ -108,7 +109,9 @@ module  ddrc_sequencer   #(
    input                [7:0]   port1_addr,
    input               [31:0]   port1_data,
    // extras
-    input                        cmda_tri, // tristate command and address lines // not likely to be used
+    input                        cmda_en, // enable (!tristate) command and address lines // not likely to be used
+    input                        ddr_rst, // generate reset to DDR3 memory (active high)
+    input                        ddr_cke, // DDR clock enable , XOR-ed with command bit
    input                        inv_clk_div,
    input                 [7:0]  dqs_pattern, // 8'h55
    input                 [7:0]  dqm_pattern  // 8'h00
@@ -153,14 +156,16 @@ module  ddrc_sequencer   #(
    assign run_done=sequence_done;
    assign run_busy=cmd_busy[0]; //earliest
    assign  pause=cmd_fetch? (phy_cmd_nop && (pause_len != 0)): (cmd_busy[2] && (pause_cntr[CMD_PAUSE_BITS-1:1]!=0));
-    assign phy_cmd_word = phy_cmd_word?phy_cmd1_word:phy_cmd0_word;
+/// debugging
+    assign phy_cmd_word = cmd_sel?phy_cmd1_word:phy_cmd0_word; // TODO: hangs even with 0-s in phy_cmd
+///    assign phy_cmd_word = phy_cmd_word?0:0;
-    assign buf_rdata[63:0] = ({64{buf_sel_1hot[1]}} & buf1_rdata[63:0]); // ORR with other read channels terms   
+    assign buf_rdata[63:0] = ({64{buf_sel_1hot[1]}} & buf1_rdata[63:0]); // ORed with other read channels terms   
    always @ (posedge mclk or posedge rst) begin
        if (rst)                cmd_busy <= 0;
        else if (sequence_done) cmd_busy <= 0;
-        else cmd_busy <= {cmd_busy[1:0],run_seq}; 
+        else cmd_busy <= {cmd_busy[1:0],run_seq | cmd_busy[0]}; 
        // Pause counter
        if (rst)                           pause_cntr <= 0;
        else if (!cmd_busy[1])             pause_cntr <= 0; // not needed?
@@ -169,22 +174,22 @@ module  ddrc_sequencer   #(
        // Fetch - command data valid
        if (rst) cmd_fetch <= 0;
        else     cmd_fetch <= cmd_busy[0] && !pause;
-        // Command read adderss
+        // Command read address
        if (rst)                        cmd_addr <= 0;
        else  if (run_seq)              cmd_addr <= run_addr[9:0];
        else if (cmd_busy[0] && !pause) cmd_addr <= cmd_addr + 1;
        // command bank select (0 - "manual" (software programmed sequences), 1 - "auto" (normal block r/w)
        if (rst)            cmd_sel <= 0;
        else  if (run_seq)  cmd_sel <= run_addr[10];
        if (rst)            buf_page <= 0;
        else  if (run_seq)  case (run_chn)
            4'h0:    buf_page <= port0_int_page;
            4'h1:    buf_page <= port1_int_page;
-            // Add other channles later
+            // Add other channels later
            default: buf_page <= 2'bxx; 
        endcase
        if (rst)            buf_sel_1hot <= 0;
        else buf_sel_1hot <= {
            (run_chn_d==4'hf)?1'b1:1'b0,
@@ -206,6 +211,12 @@ module  ddrc_sequencer   #(
        if (rst)                   buf_raddr <= 9'h0;
        else if (run_seq_d)        buf_raddr <= {buf_page,7'h0};
        else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge
+        if (rst) run_chn_d <= 0;
+        else     run_chn_d <= run_chn;
+        if (rst) run_seq_d <= 0;
+        else run_seq_d <= run_seq;
    end
    // re-register buffer write address to match DDR3 data
    always @ (negedge mclk) begin
@@ -213,21 +224,19 @@ module  ddrc_sequencer   #(
        buf_wr_negedge <= buf_wr;
        buf_wdata_negedge <= buf_wdata;
    end
-    always @ (posedge mclk) begin
-        run_chn_d <= run_chn;
-        run_seq_d <= run_seq;
-    end
 // Command sequence memories:
 // Command sequence memory 0 ("manual"):
+    wire ren0=!cmd_sel && cmd_busy[0] && !pause; // cmd_busy - multibit
+    wire ren1= cmd_sel && cmd_busy[0] && !pause;
    ram_1kx32_1kx32 #(
-        .REGISTERS(1) // register output
+        .REGISTERS(1) // (0) // register output
    ) cmd0_buf_i (
        .rclk     (mclk), // input
-        .raddr    (cmd_addr), // input[9:0] 
+        .raddr    (cmd_addr), // input[9:0]
-        .ren      (!cmd_sel && cmd_busy && !pause), // input
+///        .ren      (!cmd_sel && cmd_busy && !pause), // input
-        .regen    (!cmd_sel && cmd_busy && !pause), // input
+///        .regen    (!cmd_sel && cmd_busy && !pause), // input
+        .ren      (ren0), // input TODO: verify cmd_busy[0] is correct (was cmd_busy )
+        .regen    (ren0), // input
        .data_out (phy_cmd0_word), // output[31:0] 
        .wclk     (cmd0_clk), // input
        .waddr    (cmd0_addr), // input[9:0] 
@@ -238,12 +247,14 @@ module  ddrc_sequencer   #(
 // Command sequence memory 0 ("manual"):
    ram_1kx32_1kx32 #(
-        .REGISTERS(1) // register output
+        .REGISTERS(1) // (0) // register output
    ) cmd1_buf_i (
        .rclk     (mclk), // input
-        .raddr    (cmd_addr), // input[9:0] 
+        .raddr    (cmd_addr), // input[9:0]
-        .ren      ( cmd_sel && cmd_busy && !pause), // input
+///        .ren      ( cmd_sel && cmd_busy && !pause), // input
-        .regen    ( cmd_sel && cmd_busy && !pause), // input
+///        .regen    ( cmd_sel && cmd_busy && !pause), // input
+        .ren      ( ren1), // input
+        .regen    ( ren1), // input
        .data_out (phy_cmd1_word), // output[31:0] 
        .wclk     (cmd1_clk), // input
        .waddr    (cmd1_addr), // input[9:0] 
@@ -302,7 +313,8 @@ module  ddrc_sequencer   #(
        .CLKFBOUT_DIV_REF      (CLKFBOUT_DIV_REF),
        .DIVCLK_DIVIDE         (DIVCLK_DIVIDE),
        .CLKFBOUT_PHASE        (CLKFBOUT_PHASE),
-        .SDCLK_PHASE           (SDCLK_PHASE),
+        .SDCLK_PHASE           (SDCLK_PHASE),/// debugging
        .CLK_PHASE             (CLK_PHASE),
        .CLK_DIV_PHASE         (CLK_DIV_PHASE),
        .MCLK_PHASE            (MCLK_PHASE),
@@ -314,6 +326,7 @@ module  ddrc_sequencer   #(
        .CMD_DONE_BIT          (CMD_DONE_BIT)    // bit number (address) to signal sequence done
    ) phy_cmd_i (
+        .SDRST               (SDRST), // output ****************
        .SDCLK               (SDCLK), // output
        .SDNCLK              (SDNCLK), // output
        .SDA                 (SDA[ADDRESS_NUMBER-1:0]), // output[14:0] 
@@ -339,8 +352,10 @@ module  ddrc_sequencer   #(
        .set                 (set), // input
        .locked              (locked), // output
        .ps_rdy              (ps_rdy), // output
-        .ps_out              (ps_out[7:0]), // output[7:0] 
+        .ps_out              (ps_out[7:0]), // output[7:0]
-        .phy_cmd_word        (phy_cmd_word[31:0]), // input[35:0]
+/// debugging
+//        .phy_cmd_word        (32'h0), //phy_cmd_word[31:0]), // input[31:0]
+        .phy_cmd_word        (phy_cmd_word[31:0]), // input[31:0]
        .phy_cmd_nop         (phy_cmd_nop), // output
        .pause_len           (pause_len),     // output  [CMD_PAUSE_BITS-1:0]
        .sequence_done       (sequence_done), // output
@@ -349,7 +364,9 @@ module  ddrc_sequencer   #(
        .buf_rdata           (buf_rdata[63:0]), // input[63:0] 
        .buf_wr              (buf_wr), // output
        .buf_rd              (buf_rd), // output
-        .cmda_tri            (cmda_tri), // input
+        .cmda_en             (cmda_en), // input
+        .ddr_rst             (ddr_rst), // input ***************
+        .ddr_cke             (ddr_cke), // input ***************
        .inv_clk_div         (inv_clk_div), // input
        .dqs_pattern         (dqs_pattern), // input[7:0] 
        .dqm_pattern         (dqm_pattern) // input[7:0] 

--- a/phy/phy_cmd.v
+++ b/phy/phy_cmd.v
@@ -49,9 +49,10 @@ module  phy_cmd#(
    parameter CMD_DONE_BIT=         6  // bit number (address) to signal sequence done
 )(
    // DDR3 interface
+    output                       SDRST, // DDR3 reset (active low)
    output                       SDCLK, // DDR3 clock differential output, positive
    output                       SDNCLK,// DDR3 clock differential output, negative
-    output  [ADDRESS_NUMBER-1:0] SDA,   // output address ports (14:0) for 4Gb device
+    output  [ADDRESS_NUMBER-1:0] SDA,   // output address ports (14:0) for 4Gb deviceencode_seq_word
    output                 [2:0] SDBA,  // output bank address ports
    output                       SDWE,  // output WE port
    output                       SDRAS, // output RAS port
@@ -91,7 +92,10 @@ module  phy_cmd#(
    output                       buf_wr,    // write buffer (next cycle!)
    output                       buf_rd,     // read buffer  (ready next cycle)
    // extras
-    input                        cmda_tri, // tristate command and address lines // not likely to be used
+//    input                        cmda_tri, // tristate command and address lines // not likely to be used
+    input                        cmda_en, // tristate command and address lines // not likely to be used
+    input                        ddr_rst, // generate reset to DDR3 memory (active high)
+    input                        ddr_cke, // DDR clock enable , XOR-ed with command bit
    input                        inv_clk_div,
    input                 [7:0]  dqs_pattern, // 8'h55
    input                 [7:0]  dqm_pattern  // 8'h00
@@ -104,16 +108,22 @@ module  phy_cmd#(
 // Decoding phy_cmd[35:0] into individual fields;
    wire    [ADDRESS_NUMBER-1:0] phy_addr_in;  // also provides pause length when the command is NOP
    wire                  [ 2:0] phy_bank_in;
-    wire                  [ 2:0] phy_rcw_in; // {ras,cas,we}
+    wire                  [ 2:0] phy_rcw_pos; // positive lof=gic for RAS, CAS, WE (0 - NOP)
+    wire                  [ 2:0]   phy_rcw_in; // {ras,cas,we}
    wire                         phy_odt_in; // may be optimized?
+    wire                         phy_cke_dis; // command bit 0: enable CKE, 1 - disable CKE 
    wire                         phy_cke_in; // may be optimized?
-    wire                         phy_sel_in; // fitst/second half-cycle, oter will be nop (cke+odt applicable to both)
+    wire                         phy_sel_in; // first/second half-cycle, oter will be nop (cke+odt applicable to both)
-    wire                         phy_dq_tri_in;   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
+    wire                         phy_dq_en_in;
-    wire                         phy_dqs_tri_in;  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
+    wire                         phy_dqs_en_in;
-    wire                         phy_dci_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+    wire                           phy_dq_tri_in;   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
-//    wire                  [ 6:0] phy_buf_addr; // connect to extrenal buffer
+    wire                           phy_dqs_tri_in;  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
+    wire                         phy_dci_en_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+    wire                           phy_dci_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
    wire                         phy_buf_wr;   // connect to extrenal buffer
    wire                         phy_buf_rd;   // connect to extrenal buffer
+    wire                         cmda_tri;
 //    wire                         clk;
    wire                         clk_div;
@@ -127,7 +137,7 @@ module  phy_cmd#(
    wire                  [ 5:0] phy_bank;
    wire                  [ 5:0] phy_rcw; // {ras,cas,we}
    wire                   [1:0] phy_odt; // may be optimized?
-    wire                   [1:0] phy_cke; // may be optimized?
+    wire                   [1:0] phy_cke; // may be optphy_dqs_tri_inimized?
    wire                   [7:0] phy_dq_tri;   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
    wire                   [7:0] phy_dqs_tri;  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
    wire                         phy_dci_dis_dq; 
@@ -148,20 +158,25 @@ module  phy_cmd#(
    assign {
        phy_addr_in,
        phy_bank_in,
-        phy_rcw_in,      // {ras,cas,we}
+        phy_rcw_pos,      // {ras,cas,we}
        phy_odt_in,      // may be optimized?
-        phy_cke_in,      // may be optimized?
+        phy_cke_dis,     // disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
        phy_sel_in,      // fitst/second half-cycle, oter will be nop (cke+odt applicable to both)
-        phy_dq_tri_in,   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
+        phy_dq_en_in, //phy_dq_tri_in,   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
-        phy_dqs_tri_in,  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
+        phy_dqs_en_in, //phy_dqs_tri_in,  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
-        phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+        phy_dci_en_in, //phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
 //        phy_buf_addr, // connect to external buffer (is it needed? maybe just autoincrement?)
        phy_buf_wr,   // connect to external buffer (but only if not paused)
        phy_buf_rd,    // connect to external buffer (but only if not paused)
        phy_spare      // Reserved for future use
-    } = phy_cmd_word;
+    } =  phy_cmd_word;
-    assign phy_cmd_nop=   (phy_rcw_in==0);
+    assign phy_cke_in=     phy_cke_dis ^ ddr_cke;
-    assign sequence_done= (phy_rcw_in==0) && phy_addr_in[CMD_DONE_BIT];
+    assign phy_dq_tri_in= ~phy_dq_en_in;
+    assign phy_dqs_tri_in=~phy_dqs_en_in;
+    assign phy_dci_in=    ~phy_dci_en_in;
+    assign phy_rcw_in=    ~phy_rcw_pos;
+    assign phy_cmd_nop=   (phy_rcw_pos==0);
+    assign sequence_done= phy_cmd_nop && phy_addr_in[CMD_DONE_BIT];
    assign pause_len=      phy_addr_in[CMD_PAUSE_BITS-1:0];
 //    assign buf_addr = phy_buf_addr;
@@ -170,7 +185,7 @@ module  phy_cmd#(
    assign  phy_addr=   {phy_addr_in,phy_addr_in};       // also provides pause length when the command is NOP
    assign  phy_bank=   {phy_bank_in,phy_bank_in};
-    assign  phy_rcw=    {phy_sel_in?phy_rcw_in:3'h0, phy_sel_in?3'h0:phy_rcw_in}; // {ras,cas,we}
+    assign  phy_rcw=    {phy_sel_in?phy_rcw_in:3'h7, phy_sel_in?3'h7:phy_rcw_in}; // {ras,cas,we}
    assign  phy_odt=    {phy_odt_in,phy_odt_in};         // may be optimized?
    assign  phy_cke=    {phy_cke_in,phy_cke_in};         // may be optimized?
@@ -189,6 +204,8 @@ module  phy_cmd#(
    assign buf_wdata[63:0] = phy_rdata_r[63:0];
+    assign cmda_tri=!cmda_en;
    always @ (posedge mclk) begin
        dqs_tri_prev <= phy_dqs_tri_in;
        dq_tri_prev  <= phy_dq_tri_in;
@@ -274,6 +291,7 @@ phy_rdata
        .SS_MODE          (SS_MODE),
        .SS_MOD_PERIOD    (SS_MOD_PERIOD)
    ) phy_top_i (
+        .ddr3_nrst       (SDRST), // output
        .ddr3_clk        (SDCLK), // output
        .ddr3_nclk       (SDNCLK), // output
        .ddr3_a          (SDA[ADDRESS_NUMBER-1:0]), // output[14:0] 
@@ -295,7 +313,9 @@ phy_rdata
        .clk             (), // output
        .clk_div         (clk_div), // output
        .mclk            (mclk), // output
-        .rst_in          (rst_in), // input
+        .rst_in          (rst_in),   // input
+        .ddr_rst         (ddr_rst),  // input
        .in_a            (phy_addr[2*ADDRESS_NUMBER-1:0]), // input[29:0] 
        .in_ba           (phy_bank[5:0]), // input[5:0] 
        .in_we           ({phy_rcw[3],phy_rcw[0]}), // input[1:0] 

--- a/phy/phy_top.v
+++ b/phy/phy_top.v
@@ -52,6 +52,7 @@ module  phy_top #(
    parameter SS_MODE =      "CENTER_HIGH",
    parameter SS_MOD_PERIOD =       10000
 )(
+    output                       ddr3_nrst, // output NRST port
    output                       ddr3_clk, // DDR3 clock differential output, positive
    output                       ddr3_nclk,// DDR3 clock differential output, negative
    output  [ADDRESS_NUMBER-1:0] ddr3_a,   // output address ports (14:0) for 4Gb device
@@ -74,8 +75,8 @@ module  phy_top #(
    output                       clk,      // free-running system clock, same frequency as iclk (shared for R/W),     BUFR output
    output                       clk_div,  // free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output
    output                       mclk,     // same as clk_div, through separate BUFG and static phase adjust
-    input                        rst_in,      // reset delays/serdes
+    input                        rst_in,   // reset delays/serdes
+    input                        ddr_rst,  // active high - generate NRST to memory 
    input [2*ADDRESS_NUMBER-1:0] in_a,     // input address, 2 bits per signal (first, second) (29:0) for 4Gb device
    input                  [5:0] in_ba,    // input bank address, 2 bits per signal (first, second)
    input                  [1:0] in_we,    // input WE, 2 bits (first, second)
@@ -119,6 +120,19 @@ module  phy_top #(
  wire  clk_ref; // 200MHz/300Mhz to calibrate I/O delays            
  wire locked_mmcm,locked_pll, dly_ready;
  assign locked=locked_mmcm && locked_pll && dly_ready; // both PLL ready, I/O delay calibrated
+/* memory reset */
+    obuf #(
+        .CAPACITANCE("DONT_CARE"),
+        .DRIVE(12),
+        .IOSTANDARD(IOSTANDARD_CMDA),
+        .SLEW("SLOW")
+    ) obuf_i (
+        .O(ddr3_nrst), // output
+        .I(~ddr_rst)   // input
+    );
  cmd_addr #(
    .IODELAY_GRP(IODELAY_GRP),
    .IOSTANDARD(IOSTANDARD_CMDA),

--- a/util_modules/fifo_cross_clocks.v
+++ b/util_modules/fifo_cross_clocks.v
@@ -65,9 +65,10 @@ module fifo_cross_clocks
    // False positive in nempty can only happen if
    // a) it is transitioning from empty to non-empty due to we pulse
    // b) it is transitioning to overrun - too bad already
-    // false negative - OK, just wait fro the next rclk 
+    // false negative - OK, just wait for the next rclk 
 //    assign nempty=waddr_gray_rclk != raddr_gray;
-    assign nempty=waddr_gray_rclk[3:0] != raddr_gray[3:0];
+//    assign nempty=waddr_gray_rclk[3:0] != raddr_gray[3:0];
+    assign nempty= (waddr_gray_rclk[3:0] ^ raddr_gray[3:0]) != 4'b0;
    assign data_out=ram[raddr];
    always @ (posedge  wclk or posedge rst) begin
        if (rst)     waddr <= 0;

--- a/wrap/obuf.v
+++ b/wrap/obuf.v
+/*******************************************************************************
+ * Module: obuf
+ * Date:2014-05-27  
+ * Author: Andrey Filippov
+ * Description: Wrapper for OBUF primitive
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * obuf.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  obuf.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+module  obuf # (
+    parameter CAPACITANCE="DONT_CARE",
+    parameter DRIVE = 12,
+    parameter IOSTANDARD = "DEFAULT",
+    parameter SLEW = "SLOW"
+) (
+    output O,
+    input I
+);
+    OBUF #(
+        .CAPACITANCE(CAPACITANCE),
+        .DRIVE(DRIVE),
+        .IOSTANDARD(IOSTANDARD),
+        .SLEW(SLEW)
+    ) OBUF_i (
+        .O(O), // output 
+        .I(I) // input 
+    );
+endmodule
--- a/wrap/oddr_ds.v
+++ b/wrap/oddr_ds.v
@@ -21,11 +21,11 @@
 `timescale 1ns/1ps
 module  oddr_ds # (
-        parameter CAPACITANCE ="DONT_CARE",
+        parameter CAPACITANCE =  "DONT_CARE",
-        parameter IOSTANDARD = "DIFF_SSTL15",
+        parameter IOSTANDARD =   "DIFF_SSTL15",
-        parameter SLEW =       "SLOW",
+        parameter SLEW =         "SLOW",
        parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
-        parameter INIT          = 1'b0,
+        parameter INIT         = 1'b0,
        parameter SRTYPE = "SYNC"
 )(
    input  clk,