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Commit 3bff174e authored by Andrey Filippov's avatar Andrey Filippov
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debugging with debug ring

parent ed32ff53
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Showing with 430 additions and 67 deletions
.project
View file @ 3bff174e
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150904164653967.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150904164653967.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150904164653967.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150904164653967.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150904164653967.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150904164653967.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150904164653967.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150904164653967.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......@@ -107,32 +107,32 @@
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150904164653967.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150903211518672.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150904164653967.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150903211518672.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150904164653967.dcp</location>
</link>
<link>
<name>vivado_state/x393-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150903211518672.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150904164653967.dcp</location>
</link>
<link>
<name>vivado_state/x393-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150903211518672.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150904164653967.dcp</location>
</link>
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150903211518672.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150904164653967.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.iverilog.prefs
View file @ 3bff174e
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->
eclipse.preferences.version=1
iverilog_100_TopModulesOther=glbl<-@\#\#@->
iverilog_101_TopModulesOther=glbl<-@\#\#@->
......@@ -6,6 +6,8 @@ iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
iverilog_103_ExtraFiles=glbl.v<-@\#\#@->
iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_109_ShowNoProblem=true
iverilog_110_ShowWarnings=false
iverilog_113_SaveLogsSimulator=true
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
......
compressor_jp/compressor393.v
View file @ 3bff174e
......@@ -242,6 +242,13 @@ module compressor393 # (
);
`ifdef DEBUG_RING
localparam DEBUG_RING_LENGTH = 4;
wire [DEBUG_RING_LENGTH:0] debug_ring; // TODO: adjust number of bits
assign debug_do = debug_ring[0];
assign debug_ring[DEBUG_RING_LENGTH] = debug_di;
`endif
wire [47:0] status_ad_mux;
wire [5:0] status_rq_mux;
wire [5:0] status_start_mux;
......@@ -368,6 +375,9 @@ module compressor393 # (
.CMPRS_CORING_BITS (CMPRS_CORING_BITS),
.CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS),
.CMPRS_TIMEOUT (CMPRS_TIMEOUT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) jp_channel_i (
// .rst (rst), // input
.xclk (xclk), // input
......@@ -417,6 +427,12 @@ module compressor393 # (
.fifo_flush (fifo_flush[i]), // output
.flush_hclk (flush_hclk[i]), // output
.fifo_count (fifo_count[8* i +: 8]) // output[7:0]
`ifdef DEBUG_RING
,.debug_do (debug_ring[i]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[i+1]) // input
`endif
);
end
endgenerate
......
compressor_jp/jp_channel.v
View file @ 3bff174e
......@@ -94,7 +94,9 @@ module jp_channel#(
parameter CMPRS_TIMEOUT_BITS= 12,
parameter CMPRS_TIMEOUT= 1000 // mclk cycles
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 //SuppressThisWarning VEditor - not used
`endif
)(
// input rst, // global reset
......@@ -171,7 +173,16 @@ module jp_channel#(
output flush_hclk, // output before writing last chunk - use it to suspend AFI to have
// last burst marked as the last one (otherwise last may be empty if frame had %4==0 chunks)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used
input debug_di // input from the debug ring
`endif
);
`ifdef DEBUG_RING
assign debug_do = debug_di; // just temporarily to short-circuit the ring
`endif
localparam CMPRS_ADDR = CMPRS_GROUP_ADDR + CMPRS_NUMBER * CMPRS_BASE_INC;
localparam CMPRS_STATUS_REG_ADDR = CMPRS_STATUS_REG_BASE + CMPRS_NUMBER * CMPRS_STATUS_REG_INC;
localparam CMPRS_HIFREQ_REG_ADDR = CMPRS_HIFREQ_REG_BASE + CMPRS_NUMBER * CMPRS_HIFREQ_REG_INC;
......
fpga_version.vh
View file @ 3bff174e
parameter FPGA_VERSION = 32'h0393000f;
\ No newline at end of file
parameter FPGA_VERSION = 32'h03930011;
\ No newline at end of file
py393/vrlg.py
View file @ 3bff174e
......@@ -119,8 +119,6 @@ def restore_default(vname=None):
#### PyDev predefines
#### PyDev predefines
SS_EN__RAW = str
CLKIN_PERIOD_PCLK = int
SENSI2C_STATUS_REG_REL__TYPE = str
......@@ -194,7 +192,8 @@ RTC_MHZ = int
SENS_LENS_C_MASK = int
MCONTR_PHY_16BIT_EXTRA = int
HIST_SAXI_EN__TYPE = str
MCONTR_PHY_16BIT_PATTERNS_TRI = int
DEBUG_READ_REG_ADDR__TYPE = str
DEBUG_LOAD__RAW = str
WINDOW_Y0__RAW = str
CMPRS_STATUS_CNTRL = int
CLK_STATUS_REG_ADDR__RAW = str
......@@ -211,6 +210,7 @@ MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
RTC_SET_STATUS__TYPE = str
CMPRS_CBIT_QBANK_BITS__RAW = str
FFCLK0_IBUF_DELAY_VALUE__RAW = str
DEBUG_READ_REG_ADDR = int
WINDOW_HEIGHT = int
CAMSYNC_TRIG_DELAY0__RAW = str
MCONTR_SENS_STATUS_INC__RAW = str
......@@ -221,6 +221,7 @@ CLKFBOUT_MULT = int
RTC_STATUS_REG_ADDR__RAW = str
SENS_LENS_C_MASK__RAW = str
NUM_CYCLES_11__TYPE = str
DEBUG_ADDR__TYPE = str
CMPRS_CBIT_QBANK_BITS__TYPE = str
SENS_GAMMA_MODE_TRIG = int
RTC_SET_USEC = int
......@@ -245,6 +246,7 @@ CLKFBOUT_MULT_SYNC__TYPE = str
MAX_TILE_HEIGHT__RAW = str
BUF_IPCLK2X_SENS3__TYPE = str
IBUF_LOW_PWR = str
DEBUG_CMD_LATENCY = int
CMD_DONE_BIT = int
NUM_CYCLES_31 = int
NUM_CYCLES_30 = int
......@@ -257,6 +259,7 @@ MCONTR_CMPRS_STATUS_BASE__RAW = str
SENS_LENS_RADDR__TYPE = str
CAMSYNC_PRE_MAGIC__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
DEBUG_LOAD = int
FFCLK0_DQS_BIAS = str
CMPRS_JP4DIFF__TYPE = str
LOGGER_CONF_DBG__RAW = str
......@@ -414,6 +417,7 @@ CMPRS_CBIT_DCSUB_BITS__TYPE = str
AXI_RD_ADDR_BITS__TYPE = str
CAMSYNC_CHN_EN_BIT__TYPE = str
CMDFRAMESEQ_ADDR_BASE__RAW = str
DEBUG_ADDR__RAW = str
CONTROL_ADDR__RAW = str
SENSI2C_CMD_RESET = int
CMPRS_FRMT_MBCM1_BITS__TYPE = str
......@@ -446,7 +450,7 @@ FRAME_HEIGHT_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int
CLKFBOUT_MULT_SYNC = int
DLY_CMDA_ODELAY = long
SENS_LENS_C = int
GPIO_PORTEN__RAW = str
MCONTR_ARBIT_ADDR_MASK = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_WINDOW_WH = int
......@@ -526,7 +530,6 @@ CMPRS_HIFREQ_REG_BASE__TYPE = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
DQTRI_LAST__TYPE = str
LD_DLY_LANE1_ODELAY__TYPE = str
DLY_DQ_ODELAY = long
BUF_IPCLK_SENS1__TYPE = str
FFCLK0_IFD_DELAY_VALUE__TYPE = str
......@@ -544,7 +547,6 @@ NUM_CYCLES_16 = int
NUM_CYCLES_15 = int
NUM_CYCLES_21__TYPE = str
CMPRS_CBIT_BAYER = int
GPIO_PORTEN__RAW = str
SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int
CLKFBOUT_DIV_REF__RAW = str
......@@ -591,6 +593,7 @@ MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str
SENS_REFCLK_FREQUENCY__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
DEBUG_ADDR = int
MULT_SAXI_ADV_WR__RAW = str
LOGGER_PAGE_GPS = int
HIST_SAXI_MODE_ADDR_MASK = int
......@@ -612,6 +615,7 @@ CMPRS_CBIT_CMODE_JP4__RAW = str
DFLT_DQM_PATTERN__RAW = str
GPIO_SET_STATUS__RAW = str
SENS_JTAG_TCK = int
DEBUG_STATUS_REG_ADDR__TYPE = str
REFRESH_OFFSET__TYPE = str
SENS_CTRL_ARST__RAW = str
CMPRS_CBIT_DCSUB__TYPE = str
......@@ -649,6 +653,7 @@ BUF_CLK1X_PCLK2X__TYPE = str
FFCLK1_IFD_DELAY_VALUE__TYPE = str
MCNTRL_TILED_CHN4_ADDR = int
MCONTR_SENS_INC__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__TYPE = str
LOGGER_MASK__RAW = str
IBUF_LOW_PWR__RAW = str
DLY_CMDA_ODELAY__TYPE = str
......@@ -786,6 +791,7 @@ AFI_LO_ADDR64__RAW = str
BUF_IPCLK_SENS1__RAW = str
MCNTRL_SCANLINE_STARTADDR__RAW = str
SENSI2C_STATUS_REG_BASE__TYPE = str
DEBUG_LOAD__TYPE = str
MCONTR_PHY_16BIT_WBUF_DELAY = int
DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
TILE_HEIGHT__RAW = str
......@@ -872,6 +878,7 @@ T_RFC__RAW = str
WBUF_DLY_DFLT__TYPE = str
PXD_SLEW__TYPE = str
SENSI2C_REL_RADDR__RAW = str
DEBUG_SET_STATUS__RAW = str
MCONTR_RD_MASK__RAW = str
LOGGER_CONF_EN = int
FFCLK0_CAPACITANCE = str
......@@ -910,6 +917,7 @@ MULT_SAXI_BSLOG1__RAW = str
CLKFBOUT_MULT_PCLK__RAW = str
MCONTR_SENS_STATUS_INC__TYPE = str
CAMSYNC_TRIG_DELAY0__TYPE = str
SENSI2C_STATUS_REG_INC = int
CLKFBOUT_PHASE__TYPE = str
MCNTRL_TILED_WINDOW_WH = int
CMDFRAMESEQ_MASK = int
......@@ -994,6 +1002,7 @@ LAST_FRAME_BITS__TYPE = str
CLK_MASK__RAW = str
DLY_DM_ODELAY = long
MEMBRIDGE_STATUS_CNTRL__RAW = str
DEBUG_SHIFT_DATA = int
MEMBRIDGE_STATUS_REG = int
CMPRS_CBIT_CMODE_JPEG18__RAW = str
IPCLK2X_PHASE = float
......@@ -1057,6 +1066,7 @@ FFCLK0_CAPACITANCE__RAW = str
CMDFRAMESEQ_ABS = int
CMPRS_MONO8 = int
MULT_SAXI_ADDR__RAW = str
DEBUG_CMD_LATENCY__TYPE = str
FFCLK1_IBUF_DELAY_VALUE__TYPE = str
TILED_KEEP_OPEN = int
MCNTRL_SCANLINE_MASK__RAW = str
......@@ -1118,7 +1128,7 @@ NUM_CYCLES_29__TYPE = str
RTC_SET_SEC__TYPE = str
CAMSYNC_ADDR = int
RTC_SET_CORR__TYPE = str
DLY_LANE1_IDELAY__TYPE = str
PHASE_WIDTH__RAW = str
SLEW_DQ__RAW = str
CMPRS_CBIT_CMODE_JPEG20__RAW = str
FFCLK0_IBUF_DELAY_VALUE = str
......@@ -1210,7 +1220,7 @@ MCNTRL_SCANLINE_STARTADDR = int
CONTROL_ADDR = int
DQSTRI_FIRST__TYPE = str
MULT_SAXI_HALF_BRAM_IN__TYPE = str
SENSI2C_CMD_SDA = int
DEBUG_SET_STATUS = int
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
STATUS_ADDR = int
CLKOUT_DIV_XCLK = int
......@@ -1261,12 +1271,13 @@ SENS_JTAG_PROG = int
MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
FFCLK0_IOSTANDARD = str
SENS_GAMMA_ADDR_MASK__RAW = str
PHASE_WIDTH__RAW = str
DLY_LANE1_IDELAY__TYPE = str
SENS_LENS_BY_MASK = int
DEBUG_MASK__RAW = str
MEMBRIDGE_ADDR__RAW = str
CMPRS_COLOR_SATURATION__RAW = str
AXI_RD_ADDR_BITS = int
CMPRS_CBIT_CMODE_JP46DC__TYPE = str
LD_DLY_LANE1_ODELAY__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
TEST01_START_FRAME__TYPE = str
SENSI2C_CMD_SCL_WIDTH__TYPE = str
......@@ -1359,6 +1370,7 @@ SENSOR_FIFO_DELAY__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str
IDELAY_VALUE__TYPE = str
CMPRS_CBIT_CMODE_JP4DC__TYPE = str
SENSI2C_CMD_SDA = int
PICKLE__TYPE = str
SENSOR_MODE_WIDTH__TYPE = str
MCONTR_LINTILE_WRITE__RAW = str
......@@ -1523,7 +1535,7 @@ HISTOGRAM_LEFT_TOP__RAW = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__TYPE = str
LOGGER_STATUS_REG_ADDR = int
CMDSEQMUX_ADDR__TYPE = str
SENSI2C_STATUS_REG_INC = int
DEBUG_STATUS_REG_ADDR = int
SENS_JTAG_TDI__TYPE = str
SENS_GAMMA_MODE_PAGE = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
......@@ -1568,6 +1580,7 @@ MULT_SAXI_CNTRL_MASK__TYPE = str
SENS_PCLK_PERIOD__TYPE = str
INITIALIZE_OFFSET__RAW = str
CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str
CMPRS_AFIMUX_RST__RAW = str
SENSI2C_CMD_BYTES_PBITS = int
CAMSYNC_TRIG_DST__RAW = str
......@@ -1609,6 +1622,7 @@ NUM_FRAME_BITS = int
LOGGER_STATUS_REG_ADDR__RAW = str
CMPRS_CBIT_FRAMES_BITS__RAW = str
MCNTRL_TILED_MASK__TYPE = str
DEBUG_MASK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN = int
CMPRS_FRMT_LMARG__TYPE = str
SENSIO_JTAG = int
......@@ -1648,6 +1662,7 @@ SENS_LENS_AX__RAW = str
CMPRS_JP4DIFF__RAW = str
SENS_SS_MODE__RAW = str
CAMSYNC_SNDEN_BIT__TYPE = str
DEBUG_CMD_LATENCY__RAW = str
CMPRS_CBIT_CMODE__TYPE = str
LOGGER_STATUS_MASK = int
DFLT_DQ_TRI_ON_PATTERN__RAW = str
......@@ -1822,6 +1837,7 @@ CAMSYNC_TRIG_DELAY2__RAW = str
MCNTRL_TEST01_CHN4_MODE__RAW = str
DLY_CMDA__TYPE = str
CLKFBOUT_MULT__TYPE = str
DEBUG_MASK = int
MCONTR_PHY_0BIT_CMDA_EN__RAW = str
IDELAY_VALUE = int
DQSTRI_LAST__TYPE = str
......@@ -1889,10 +1905,12 @@ SENSIO_STATUS_REG_REL__TYPE = str
MCNTRL_SCANLINE_MODE = int
DLY_LANE0_IDELAY = long
MCNTRL_PS_CMD = int
DEBUG_SHIFT_DATA__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
STATUS_2LSB_SHFT__RAW = str
STATUS_MSB_RSHFT__RAW = str
SLEW_CMDA__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI = int
GPIO_SLEW = str
MCONTR_TOP_STATUS_REG_ADDR__RAW = str
DFLT_DQS_TRI_ON_PATTERN = int
......@@ -1905,6 +1923,7 @@ SENSOR_CHN_EN_BIT__RAW = str
SENS_SS_MODE__TYPE = str
CAMSYNC_TRIG_SRC__TYPE = str
LOGGER_CONF_IMU__TYPE = str
DEBUG_READ_REG_ADDR__RAW = str
PHASE_CLK2X_XCLK__RAW = str
SS_EN = str
CLKFBOUT_MULT_XCLK = int
......@@ -1922,6 +1941,7 @@ NUM_CYCLES_11__RAW = str
FFCLK1_CAPACITANCE__RAW = str
SENSI2C_DRIVE__RAW = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENS_LENS_C = int
SENSOR_CTRL_ADDR_MASK__RAW = str
DFLT_CHN_EN__RAW = str
NUM_CYCLES_LOW_BIT = int
......@@ -2018,6 +2038,7 @@ MCONTR_TOP_16BIT_REFRESH_PERIOD = int
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
STATUS_SEQ_SHFT__TYPE = str
MCONTR_CMPRS_BASE = int
DEBUG_SET_STATUS__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
RTC_SEC_USEC_ADDR__RAW = str
MCNTRL_PS_ADDR = int
......@@ -2062,6 +2083,7 @@ MULT_SAXI_MASK__RAW = str
MCONTR_CMPRS_STATUS_BASE__TYPE = str
NUM_CYCLES_10__RAW = str
SENS_LENS_FAT0_OUT__TYPE = str
DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str
SENS_NUM_SUBCHN = int
MCONTR_BUF0_WR_ADDR__TYPE = str
......
py393/x393_sens_cmprs.py
View file @ 3bff174e
......@@ -46,6 +46,7 @@ import x393_utils
import time
import vrlg
from verilog_utils import hx
PAGE_SIZE = 4096
......@@ -529,6 +530,8 @@ class X393SensCmprs(object):
print ("circbuf end = 0x%x"%(circbuf_end))
print ("memory buffer end = 0x%x"%(mem_end))
self.program_status_debug (3,0)
if sensor_mask & 3: # Need mower for sesns1 and sens 2
if verbose >0 :
print ("===================== Sensor power setup: sensor ports 0 and 1 =========================")
......@@ -669,3 +672,98 @@ class X393SensCmprs(object):
for chn in sensors:
self.x393Sensor.print_status_sensor_io (num_sensor = chn)
self.x393Sensor.print_status_sensor_i2c (num_sensor = chn)
### Debug network methods
def program_status_debug( self,
mode, # input [1:0] mode;
seq_num): # input [5:0] seq_num;
"""
Set status generation mode for selected sensor port i2c control
@param mode - status generation mode:
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
self.x393_axi_tasks.program_status (vrlg.DEBUG_ADDR ,
vrlg.DEBUG_SET_STATUS,
mode,
seq_num)
def debug_read_ring(self,
num32 = 32):
"""
Read serial debug ring
@param num32 - number of 32-bit words to read
@return - list of the 32-bit words read
"""
maxTimeout = 2.0 # sec
endTime=time.time() + maxTimeout
result = []
# load all shift registers from sources
self.x393_axi_tasks.write_control_register(vrlg.DEBUG_ADDR + vrlg.DEBUG_LOAD, 0);
for _ in range (num32):
seq_num = (self.x393_axi_tasks.read_status(vrlg.DEBUG_STATUS_REG_ADDR) >> vrlg.STATUS_SEQ_SHFT) & 0x3f;
self.x393_axi_tasks.write_control_register(vrlg.DEBUG_ADDR + vrlg.DEBUG_SHIFT_DATA, 0);
while seq_num == (self.x393_axi_tasks.read_status(vrlg.DEBUG_STATUS_REG_ADDR) >> vrlg.STATUS_SEQ_SHFT) & 0x3f:
if time.time() > endTime:
return None
result.append(self.x393_axi_tasks.read_status(vrlg.DEBUG_READ_REG_ADDR))
return result
def print_debug( self,
num32 = 32):
"""
Read and print serial debug ring as a sequence of 32-bit numbers
@param num32 - number of 32-bit words to read
@return - list of the 32-bit words read
"""
status = self.debug_read_ring(num32)
numPerLine = 8
for i,d in enumerate (status):
if ( i % numPerLine) == 0:
print ("\n%2x: "%(i), end="")
print("%s "%(hx(d,8)), end = "")
print()
"""
tasks related to debug ring
task debug_read_ring;
input integer num32;
reg [5:0] seq_num;
integer i;
begin
// load all shift registers from sources
write_control_register(DEBUG_ADDR + DEBUG_LOAD, 0);
for (i = 0; i < num32; i = i+1 ) begin
read_status(DEBUG_STATUS_REG_ADDR);
seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20) &'h3f; // &'h30;
write_control_register(DEBUG_ADDR + DEBUG_SHIFT_DATA, 0);
while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20) &'h3f) == seq_num) begin
read_status(DEBUG_STATUS_REG_ADDR);
end
read_status(DEBUG_READ_REG_ADDR);
DEBUG_ADDRESS = i;
DEBUG_DATA = registered_rdata;
end
end
endtask
`ifdef DEBUG_RING
task program_status_debug;
input [1:0] mode;
input [5:0] seq_num;
begin
program_status (DEBUG_ADDR,
DEBUG_SET_STATUS,
mode,
seq_num);
end
endtask
"""
\ No newline at end of file
sensor/sens_histogram.v
View file @ 3bff174e
......@@ -27,6 +27,9 @@ module sens_histogram #(
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
parameter [1:0] XOR_HIST_BAYER = 2'b00// 11 // invert bayer setting
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 // SuppressThisWarning VEditor - not used
`endif
)(
// input rst,
......@@ -50,7 +53,16 @@ module sens_histogram #(
input cmd_stb, // strobe (with first byte) for the command a/d
input monochrome // tie to 0 to reduce hardware
,output debug_mclk
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used
input debug_di // input from the debug ring
`endif
);
`ifdef DEBUG_RING
// assign debug_do = debug_di;
`endif
localparam PXD_2X_LATENCY = 2;
reg hist_bank_pclk;
......@@ -348,6 +360,25 @@ module sens_histogram #(
end
`ifdef DEBUG_RING
debug_slave #(
.SHIFT_WIDTH (64),
.READ_WIDTH (64),
.WRITE_WIDTH (32),
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
) debug_slave_i (
.mclk (mclk), // input
.mrst (mrst), // input
.debug_di (debug_di), // input
.debug_sl (debug_sl), // input
.debug_do (debug_do), // output
.rd_data ({height_m1[15:0], vcntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
.wr_data (), // output[31:0] - not used
.stb () // output - not used
);
`endif
pulse_cross_clock pulse_cross_clock_debug_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
......@@ -646,9 +677,16 @@ module sens_histogram_dummy(
output hist_rq,
output [31:0] hist_do,
output hist_dv
`ifdef DEBUG_RING
, output debug_do,
input debug_di
`endif
);
assign hist_rq = 0;
assign hist_do = 0;
assign hist_dv = 0;
`ifdef DEBUG_RING
assign debug_do = debug_di;
`endif
endmodule
\ No newline at end of file
sensor/sensor_channel.v
View file @ 3bff174e
......@@ -195,6 +195,9 @@ module sensor_channel#(
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
`endif
) (
// input rst,
......@@ -239,8 +242,21 @@ module sensor_channel#(
output [1:0] hist_chn, // output[1:0] histogram (sub) channel, valid with request and transfer
output hist_dvalid, // output data valid - active when sending a burst
output [31:0] hist_data // output[31:0] histogram data
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load
input debug_di // input from the debug ring
`endif
);
`ifdef DEBUG_RING
localparam DEBUG_RING_LENGTH = 4; // for now - just connect the histogram(s) module(s)
wire [DEBUG_RING_LENGTH:0] debug_ring; // TODO: adjust number of bits
assign debug_do = debug_ring[0];
assign debug_ring[DEBUG_RING_LENGTH] = debug_di;
`endif
localparam HIST_MONOCHROME = 1'b0; // TODO:make it configurable (at expense of extra hardware)
......@@ -757,6 +773,9 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
.mrst (mrst), // input
......@@ -778,14 +797,30 @@ module sensor_channel#(
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[0])
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[1]) // input
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
.hist_rq(hist_rq[0]), // output
.hist_do(hist_do0), // output[31:0]
.hist_dv(hist_dv[0]) // output
.hist_rq (hist_rq[0]), // output
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_di (debug_ring[1]) // input
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[0] = debug_ring[1]; // just bypass
// assign tmp1 = debug_ring[1]; // just bypass
//`endif
endgenerate
generate
if (HISTOGRAM_ADDR1 >=0)
sens_histogram #(
......@@ -794,6 +829,9 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
.mrst (mrst), // input
......@@ -815,13 +853,26 @@ module sensor_channel#(
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[1])
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[2]) // input
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
.hist_rq(hist_rq[1]), // output
.hist_do(hist_do1), // output[31:0]
.hist_dv(hist_dv[1]) // output
.hist_rq (hist_rq[1]), // output
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_di (debug_ring[2]) // input
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[1] = debug_ring[2]; // just bypass
//`endif
endgenerate
generate
if (HISTOGRAM_ADDR2 >=0)
......@@ -831,6 +882,9 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
.mrst (mrst), // input
......@@ -852,13 +906,25 @@ module sensor_channel#(
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[2])
`ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[3]) // input
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
.hist_rq(hist_rq[2]), // output
.hist_do(hist_do2), // output[31:0]
.hist_dv(hist_dv[2]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output
.debug_di (debug_ring[3]) // input
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[2] = debug_ring[3]; // just bypass
//`endif
endgenerate
generate
if (HISTOGRAM_ADDR3 >=0)
......@@ -868,6 +934,9 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
.mrst (mrst), // input
......@@ -889,13 +958,25 @@ module sensor_channel#(
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[3])
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[4]) // input
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
.hist_rq(hist_rq[3]), // output
.hist_do(hist_do3), // output[31:0]
.hist_dv(hist_dv[3]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_di (debug_ring[4]) // input
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[3] = debug_ring[4]; // just bypass
//`endif
endgenerate
sens_histogram_mux sens_histogram_mux_i (
......
sensor/sensors393.v
View file @ 3bff174e
......@@ -314,6 +314,15 @@ module sensors393 #(
`endif
);
`ifdef DEBUG_RING
localparam DEBUG_RING_LENGTH = 4;
wire [DEBUG_RING_LENGTH:0] debug_ring; // TODO: adjust number of bits
assign debug_do = debug_ring[0];
assign debug_ring[DEBUG_RING_LENGTH] = debug_di;
`endif
wire [1:0] idelay_ctrl_rdy; // need to connect outputs to prevent optimizing out
assign idelay_rdy = &idelay_ctrl_rdy;
reg [7:0] cmd_ad;
......@@ -477,6 +486,9 @@ module sensors393 #(
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sensor_channel_i (
// .rst (rst), // input
.pclk (pclk), // input
......@@ -514,6 +526,11 @@ module sensors393 #(
.hist_chn (hist_chn[2 * i +: 2]), // output[1:0]
.hist_dvalid (hist_dvalid[i]), // output
.hist_data (hist_data[i * 32 +: 32])// output[31:0]
`ifdef DEBUG_RING
,.debug_do (debug_ring[i]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[i+1]) // input
`endif
);
sensor_membuf #(
......
system_defines.vh
View file @ 3bff174e
......@@ -2,7 +2,7 @@
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define PRELOAD_BRAMS
`define DEBUG_RING
`define DEBUG_RING 1
// Enviroment-dependent options
`ifdef IVERILOG
`define SIMULATION
......
util_modules/debug_master.v
View file @ 3bff174e
......@@ -50,7 +50,7 @@ module debug_master #(
wire cmd_we;
reg [31:0] data_sr;
reg tgl;
reg [ 5:0] cntr;
reg [ 6:0] cntr;
reg ld_r;
reg cmd; //command stae (0 - idle)
reg [DEBUG_CMD_LATENCY : 0] cmd_reg;
......@@ -59,6 +59,7 @@ module debug_master #(
wire shift32_w = cmd_we && (cmd_a == DEBUG_SHIFT_DATA);
wire load_w = cmd_we && (cmd_a == DEBUG_LOAD);
wire cmd_reg_dly = cmd_reg[DEBUG_CMD_LATENCY];
wire shift_done;
assign debug_sl = cmd_reg[0];
assign debug_do = data_sr[0];
......@@ -68,8 +69,8 @@ module debug_master #(
else ld_r <= load_w;
if (mrst) cntr <= 0;
else if (shift32_w) cntr <= 6'h21;
else if (cntr[5]) cntr <= cntr + 1;
else if (shift32_w) cntr <= 7'h41;
else if (cntr[6]) cntr <= cntr + 1;
if (mrst) cmd_reg <= 0;
else cmd_reg <= {cmd_reg[DEBUG_CMD_LATENCY - 1 : 0], load_w | ld_r | cntr[0]};
......@@ -81,10 +82,21 @@ module debug_master #(
else if (cmd && !cmd_reg_dly) data_sr <= {debug_di, data_sr[31:1]};
if (mrst) tgl <= 0;
else tgl <= tgl & (&cntr); // When counter == 63 - toggle tgl to initiate status send
else tgl <= tgl ^ shift_done; // When counter == 127 - toggle tgl to initiate status send
end
dly_16 #(
.WIDTH(1)
) dly_16_i (
.clk (mclk), // input
.rst (1'b0), // input
.dly (DEBUG_CMD_LATENCY+1), // input[3:0]
.din (&cntr), // input[0:0]
.dout (shift_done) // output[0:0]
);
cmd_deser #(
.ADDR (DEBUG_ADDR),
.ADDR_MASK (DEBUG_MASK),
......
util_modules/debug_slave.v
View file @ 3bff174e
......@@ -54,7 +54,7 @@ module debug_slave#(
if (mrst) cmd <= 0;
else cmd <= cmd_reg_dly & ~cmd;
if (cmd && !cmd_reg_dly) data_sr <= {debug_di, data_sr[31:1]};
if (cmd && !cmd_reg_dly) data_sr <= {debug_di, data_sr[SHIFT_WIDTH - 1 :1]};
else if (cmd && cmd_reg_dly) data_sr <= ext_rdata[SHIFT_WIDTH - 1 : 0];
end
......
x393.v
View file @ 3bff174e
......@@ -316,9 +316,9 @@ module x393 #(
wire status_debug_rq; // Other status request
wire status_debug_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
localparam DEBUG_RING_LENGTH = 10;
localparam DEBUG_RING_LENGTH = 2; // increase here, insert new after master
wire [DEBUG_RING_LENGTH-1:0] debug_ring; // TODO: adjust number of bits
wire [DEBUG_RING_LENGTH:0] debug_ring; // TODO: adjust number of bits
wire debug_sl; // debug shift/load: 0 - idle, (1,0) - shift, (1,1) - load
`endif
// Insert register layer if needed
......@@ -910,11 +910,15 @@ assign axi_grst = axi_rst_pre;
.db_in10 (status_clocks_ad), // input[7:0]
.rq_in10 (status_clocks_rq), // input
.start_in10(status_clocks_start), // output
`ifdef DEBUG_RING
.db_in11 (status_debug_ad), // input[7:0]
.rq_in11 (status_debug_rq), // input
.start_in11(status_debug_start), // output
`else
.db_in11 (8'b0), // input[7:0]
.rq_in11 (1'b0), // input
.start_in11(), // output
`endif
.db_in12 (8'b0), // input[7:0]
.rq_in12 (1'b0), // input
.start_in12(), // output
......@@ -1609,9 +1613,9 @@ assign axi_grst = axi_rst_pre;
.saxi_bid (saxi0_bid), // input[5:0]
.saxi_bresp (saxi0_bresp) // input[1:0]
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[0]) // input
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[1]) // input
`endif
);
......@@ -1841,9 +1845,9 @@ assign axi_grst = axi_rst_pre;
.afi1_wacount (afi2_wacount), // input[5:0]
.afi1_wrissuecap1en (afi2_wrissuecap1en) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[DEBUG_RING_LENGTH-1]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[1]) // input
,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[2]) // input
`endif
);
......@@ -2201,9 +2205,9 @@ assign axi_grst = axi_rst_pre;
.status_ad (status_debug_ad), // output[7:0]
.status_rq (status_debug_rq), // output
.status_start (status_debug_start), // input
.debug_do (debug_ring[0]), // output
.debug_do (debug_ring[2]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[DEBUG_RING_LENGTH-1]) // input
.debug_di (debug_ring[0]) // DEBUG_RING_LENGTH-1]) // input
);
`endif
......
x393_testbench02.tf
View file @ 3bff174e
......@@ -568,7 +568,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
// integer SCANLINE_CUR_Y;
wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
reg [31:0] DEBUG_DATA;
integer DEBUG_ADDRESS;
//NUM_XFER_BITS=6
// localparam SCANLINE_PAGES_PER_ROW= (WINDOW_WIDTH>>NUM_XFER_BITS)+((WINDOW_WIDTH[NUM_XFER_BITS-1:0]==0)?0:1);
......@@ -902,6 +903,14 @@ assign #10 gpio_pins[9] = gpio_pins[8];
`endif
`ifdef TEST_SENSOR
`ifdef DEBUG_RING
TEST_TITLE = "DEBUG_STATUS";
$display("===================== TEST_%s =========================",TEST_TITLE);
program_status_debug (
3, // input [1:0] mode;
0); // input [5:0] seq_num;
`endif
TEST_TITLE = "GPIO";
$display("===================== TEST_%s =========================",TEST_TITLE);
......@@ -1028,8 +1037,11 @@ assign #10 gpio_pins[9] = gpio_pins[8];
$display("===================== TEST_%s =========================",TEST_TITLE);
axi_get_delays;
`endif
`ifdef DEBUG_RING
TEST_TITLE = "READING DEBUG DATA";
$display("===================== TEST_%s =========================",TEST_TITLE);
debug_read_ring (32); // read 32 of 32-bit words
`endif
TEST_TITLE = "ALL_DONE";
$display("===================== TEST_%s =========================",TEST_TITLE);
#20000;
......@@ -1039,6 +1051,11 @@ assign #10 gpio_pins[9] = gpio_pins[8];
TEST_TITLE = "WAITING 80usec more";
$display("===================== TEST_%s =========================",TEST_TITLE);
#80000;
`ifdef DEBUG_RING
TEST_TITLE = "READING DEBUG DATA AGAIN";
$display("===================== TEST_%s =========================",TEST_TITLE);
debug_read_ring (32); // read 32 of 32-bit words
`endif
$finish;
end
// protect from never end
......@@ -3981,6 +3998,49 @@ task afi_mux_chn_start_length;
end
endtask
// tasks related to debug ring
`ifdef DEBUG_RING
task program_status_debug;
input [1:0] mode;
input [5:0] seq_num;
begin
program_status (DEBUG_ADDR,
DEBUG_SET_STATUS,
mode,
seq_num);
end
endtask
task debug_read_ring;
input integer num32;
reg [5:0] seq_num;
integer i;
begin
// load all shift registers from sources
write_contol_register(DEBUG_ADDR + DEBUG_LOAD, 0);
for (i = 0; i < num32; i = i+1 ) begin
read_status(DEBUG_STATUS_REG_ADDR);
seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20) &'h3f; // &'h30;
write_contol_register(DEBUG_ADDR + DEBUG_SHIFT_DATA, 0);
while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20) &'h3f) == seq_num) begin
read_status(DEBUG_STATUS_REG_ADDR);
end
read_status(DEBUG_READ_REG_ADDR);
DEBUG_ADDRESS = i;
DEBUG_DATA = registered_rdata;
end
end
endtask
`endif
/*
reg [31:0] DEBUG_DATA;
integer DEBUG_ADDRESS;
*/
`include "includes/tasks_tests_memory.vh" // SuppressThisWarning VEditor - may be unused
`include "includes/x393_tasks_afi.vh" // SuppressThisWarning VEditor - may be unused
`include "includes/x393_tasks_mcntrl_en_dis_priority.vh"
......@@ -3991,5 +4051,7 @@ endtask
`include "includes/x393_tasks_status.vh"
`include "includes/x393_tasks01.vh"
`include "includes/x393_mcontr_encode_cmd.vh"
endmodule
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