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x393
Commit 36912bd3 authored by Andrey Filippov's avatar Andrey Filippov
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implemented telemetry on/off, updated mode bits. FPGA version 0393012e

parent c4db5df9
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fpga_version.vh
View file @ 36912bd3
...@@ -35,7 +35,8 @@ ...@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h0393012d; // debugging - working sync parameter FPGA_VERSION = 32'h0393012e; // re-arranged control bits, added telemetry on/off
// parameter FPGA_VERSION = 32'h0393012d; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012c; // debugging - working sync // parameter FPGA_VERSION = 32'h0393012c; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012b; // debugging // parameter FPGA_VERSION = 32'h0393012b; // debugging
// parameter FPGA_VERSION = 32'h0393012a; // debugging // parameter FPGA_VERSION = 32'h0393012a; // debugging
......
includes/x393_parameters.vh
View file @ 36912bd3
...@@ -554,22 +554,25 @@ ...@@ -554,22 +554,25 @@
parameter VOSPI_MCLK_BITS = 2, parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6, parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2, parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8, parameter VOSPI_OUT_EN = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2, parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12, parameter VOSPI_OUT_EN_SINGL = 10,
parameter VOSPI_RESET_ERR = 13, parameter VOSPI_RESET_ERR = 11,
parameter VOSPI_SPI_CLK = 14, parameter VOSPI_SPI_CLK = 12,
parameter VOSPI_SPI_CLK_BITS = 2, parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16, parameter VOSPI_SEGM0_OK = 14,
parameter VOSPI_GPIO_BITS = 8, parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_VSYNC = 24, parameter VOSPI_VSYNC = 16,
parameter VOSPI_VSYNC_BITS = 2, parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync parameter VOSPI_NORESYNC = 18, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2, parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_DBG_SRC = 28, parameter VOSPI_TELEMETRY = 20,
parameter VOSPI_TELEMETRY_BITS = 2,
parameter VOSPI_GPIO = 22,
parameter VOSPI_GPIO_BITS = 6,
parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4, parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80, parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2, parameter VOSPI_PACKETS_PER_LINE = 2,
......
py393/vrlg.py
View file @ 36912bd3
...@@ -122,6 +122,7 @@ def restore_default(vname=None): ...@@ -122,6 +122,7 @@ def restore_default(vname=None):
SS_EN__RAW = str SS_EN__RAW = str
CLKIN_PERIOD_PCLK = int CLKIN_PERIOD_PCLK = int
SENSI2C_STATUS_REG_REL__TYPE = str SENSI2C_STATUS_REG_REL__TYPE = str
VOSPI_TELEMETRY__TYPE = str
SENSI2C_CMD_RUN_PBITS__RAW = str SENSI2C_CMD_RUN_PBITS__RAW = str
XOR_HIST_BAYER__TYPE = str XOR_HIST_BAYER__TYPE = str
HIST_SAXI_AWCACHE__RAW = str HIST_SAXI_AWCACHE__RAW = str
...@@ -331,6 +332,7 @@ SENS_JTAG_PGMEN__RAW = str ...@@ -331,6 +332,7 @@ SENS_JTAG_PGMEN__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
MCONTR_BUF3_RD_ADDR__TYPE = str MCONTR_BUF3_RD_ADDR__TYPE = str
LOGGER_CONF_EN_BITS__TYPE = str LOGGER_CONF_EN_BITS__TYPE = str
VOSPI_TELEMETRY_BITS__TYPE = str
CLKIN_PERIOD_PCLK__RAW = str CLKIN_PERIOD_PCLK__RAW = str
HISPI_DQS_BIAS__TYPE = str HISPI_DQS_BIAS__TYPE = str
MULTICLK_DIV_DLYREF__TYPE = str MULTICLK_DIV_DLYREF__TYPE = str
...@@ -441,6 +443,7 @@ LOGGER_CONF_MSG_BITS__TYPE = str ...@@ -441,6 +443,7 @@ LOGGER_CONF_MSG_BITS__TYPE = str
LOGGER_ADDR = int LOGGER_ADDR = int
MCONTR_PHY_0BIT_DCI_RST__RAW = str MCONTR_PHY_0BIT_DCI_RST__RAW = str
REFCLK_FREQUENCY__RAW = str REFCLK_FREQUENCY__RAW = str
VOSPI_TELEMETRY_BITS__RAW = str
LOGGER_BIT_HALF_PERIOD__RAW = str LOGGER_BIT_HALF_PERIOD__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str
DLY_DQ_ODELAY__TYPE = str DLY_DQ_ODELAY__TYPE = str
...@@ -532,6 +535,7 @@ MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int ...@@ -532,6 +535,7 @@ MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_WINDOW_WH = int MCNTRL_SCANLINE_WINDOW_WH = int
WBUF_DLY_WLV__RAW = str WBUF_DLY_WLV__RAW = str
SIMULATE_CMPRS_CMODE3__RAW = str SIMULATE_CMPRS_CMODE3__RAW = str
VOSPI_TELEMETRY__RAW = str
TABLE_HUFFMAN_INDEX = int TABLE_HUFFMAN_INDEX = int
VOSPI_HACT_TO_HACT_EOF__RAW = str VOSPI_HACT_TO_HACT_EOF__RAW = str
MCNTRL_TILED_FRAME_LAST = int MCNTRL_TILED_FRAME_LAST = int
...@@ -1005,6 +1009,7 @@ MULTICLK_BUF_AXIHP = str ...@@ -1005,6 +1009,7 @@ MULTICLK_BUF_AXIHP = str
FRAME_WIDTH_BITS = int FRAME_WIDTH_BITS = int
READ_PATTERN_OFFSET__TYPE = str READ_PATTERN_OFFSET__TYPE = str
SENS_CTRL_RST_MMCM = int SENS_CTRL_RST_MMCM = int
VOSPI_TELEMETRY_BITS = int
VOSPI_PACKET_LAST = int VOSPI_PACKET_LAST = int
MCONTR_CMD_WR_ADDR = int MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str SENSI2C_TBL_DLY_BITS__RAW = str
...@@ -1486,6 +1491,7 @@ TILE_HEIGHT__RAW = str ...@@ -1486,6 +1491,7 @@ TILE_HEIGHT__RAW = str
SCANLINE_STARTY = int SCANLINE_STARTY = int
SCANLINE_STARTX = int SCANLINE_STARTX = int
SIMULATE_CMPRS_CMODE1__RAW = str SIMULATE_CMPRS_CMODE1__RAW = str
GPIO_DRIVE__TYPE = str
FFCLK0_DIFF_TERM__TYPE = str FFCLK0_DIFF_TERM__TYPE = str
HISPI_UNTUNED_SPLIT__TYPE = str HISPI_UNTUNED_SPLIT__TYPE = str
LD_DLY_CMDA__TYPE = str LD_DLY_CMDA__TYPE = str
...@@ -2420,7 +2426,7 @@ DFLT_CHN_EN__RAW = str ...@@ -2420,7 +2426,7 @@ DFLT_CHN_EN__RAW = str
NUM_CYCLES_LOW_BIT = int NUM_CYCLES_LOW_BIT = int
READ_BLOCK_OFFSET = int READ_BLOCK_OFFSET = int
RSEL__RAW = str RSEL__RAW = str
GPIO_DRIVE__TYPE = str VOSPI_TELEMETRY = int
LWIR_FRAME_DELAY__RAW = str LWIR_FRAME_DELAY__RAW = str
VOSPI_SEGM0_OK_BITS__TYPE = str VOSPI_SEGM0_OK_BITS__TYPE = str
SDCLK_PHASE__TYPE = str SDCLK_PHASE__TYPE = str
......
py393/x393_export_c.py
View file @ 36912bd3
...@@ -2133,23 +2133,27 @@ class X393ExportC(object): ...@@ -2133,23 +2133,27 @@ class X393ExportC(object):
dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor")) dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value")) dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable")) dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"))
dw.append(("segm_zero", vrlg.VOSPI_SEGM0_OK, 1, 0, "OK to input segment 0 (invalid, valid are 1,2,3,4)"))
dw.append(("segm_zero_set",vrlg.VOSPI_SEGM0_OK + 1, 1, 0, "Enable setting of segm_zero"))
dw.append(("out_en", vrlg.VOSPI_OUT_EN, 1, 0, "Enable output sensor data to memory")) dw.append(("out_en", vrlg.VOSPI_OUT_EN, 1, 0, "Enable output sensor data to memory"))
dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory")) dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory")) dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
dw.append(("reset_err", vrlg.VOSPI_RESET_ERR, 1, 0, "Reset CRC and synchronization error status bits")) dw.append(("reset_err", vrlg.VOSPI_RESET_ERR, 1, 0, "Reset CRC and synchronization error status bits"))
dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)")) dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value")) dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input")) dw.append(("segm_zero", vrlg.VOSPI_SEGM0_OK, 1, 0, "OK to input segment 0 (invalid, valid are 1,2,3,4)"))
dw.append(("gpio1", vrlg.VOSPI_GPIO+2, 2, 0, "Output control for GPIO1: 0 - nop, 1 - set low, 2 - set high, 3 - input")) dw.append(("segm_zero_set",vrlg.VOSPI_SEGM0_OK + 1, 1, 0, "Enable setting of segm_zero"))
dw.append(("gpio2", vrlg.VOSPI_GPIO+4, 2, 0, "Output control for GPIO2: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio3", vrlg.VOSPI_GPIO+6, 2, 0, "Output control for GPIO3: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("vsync_use", vrlg.VOSPI_VSYNC, 1, 0, "Wait for the VSYNC (GPIO3). Should be enabled via i2c")) dw.append(("vsync_use", vrlg.VOSPI_VSYNC, 1, 0, "Wait for the VSYNC (GPIO3). Should be enabled via i2c"))
dw.append(("vsync_use_set",vrlg.VOSPI_VSYNC+1, 1, 0, "Enable vsync_use set/reset")) dw.append(("vsync_use_set",vrlg.VOSPI_VSYNC+1, 1, 0, "Enable vsync_use set/reset"))
dw.append(("noresync", vrlg.VOSPI_NORESYNC, 1, 0, "Disable re-synchronization by discard packets")) dw.append(("noresync", vrlg.VOSPI_NORESYNC, 1, 0, "Disable re-synchronization by discard packets"))
dw.append(("noresync_set", vrlg.VOSPI_NORESYNC+1, 1, 0, "Enable noresync set/reset")) dw.append(("noresync_set", vrlg.VOSPI_NORESYNC+1, 1, 0, "Enable noresync set/reset"))
dw.append(("dbg_src", vrlg.VOSPI_DBG_SRC, 3, 0, "Hardware debug source:0-running,1-vsync_rdy[0],2-vsync_rdy[1],3-discard_segment,4-in_busy,5-out_busy,6-hact,7-sof")) dw.append(("telemetry", vrlg.VOSPI_TELEMETRY, 1, 0, "Receive telemetry (will hang if not enabled in Lepton)"))
dw.append(("telemetry_set",vrlg.VOSPI_TELEMETRY+1, 1, 0, "Enable telemetry set/reset"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio1", vrlg.VOSPI_GPIO+2, 2, 0, "Output control for GPIO1: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio2", vrlg.VOSPI_GPIO+4, 2, 0, "Output control for GPIO2: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
# dw.append(("gpio3", vrlg.VOSPI_GPIO+6, 2, 0, "Output control for GPIO3: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("dbg_src", vrlg.VOSPI_DBG_SRC, 3, 0, " Hardware debug source:0-running,1-will_sync,2-vsync_rdy[1],3-discard_segment,4-in_busy,5-out_busy,6-hact,7-sof"))
dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src")) dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src"))
return dw return dw
......
py393/x393_sensor.py
View file @ 36912bd3
...@@ -466,9 +466,11 @@ class X393Sensor(object): ...@@ -466,9 +466,11 @@ class X393Sensor(object):
gpio0 = None, gpio0 = None,
gpio1 = None, gpio1 = None,
gpio2 = None, gpio2 = None,
gpio3 = None, # gpio3 = None,
telemetry = None,
vsync_use = None, vsync_use = None,
noresync = None, noresync = None,
dbg_src = None): dbg_src = None):
""" """
Combine sensor I/O control parameters into a control word Combine sensor I/O control parameters into a control word
...@@ -484,11 +486,11 @@ class X393Sensor(object): ...@@ -484,11 +486,11 @@ class X393Sensor(object):
@param gpio0 = Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input @param gpio0 = Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input @param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input @param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio3 = Output control for GPIO0: 3 - nop, 1 - set low, 2 - set high, 3 - input @param telemetry = Enable (1) /disable (0) telemetry data lines (should be set in the sensor too, or it will hang)
@param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment @param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment
@param noresync = Disable resynchronization by discard packets @param noresync = Disable resynchronization by discard packets
@param dbg_src = source of the hardware debug output: 0 - dbg_running @param dbg_src = source of the hardware debug output: 0 - dbg_running
1 - vsync_rdy[0] 1 - will_sync
2 - vsync_rdy[1] 2 - vsync_rdy[1]
3 - discard_segment 3 - discard_segment
4 - in_busy 4 - in_busy
...@@ -522,8 +524,12 @@ class X393Sensor(object): ...@@ -522,8 +524,12 @@ class X393Sensor(object):
rslt |= (gpio1 & 3) << (vrlg.VOSPI_GPIO + 2) rslt |= (gpio1 & 3) << (vrlg.VOSPI_GPIO + 2)
if not gpio2 is None: if not gpio2 is None:
rslt |= (gpio2 & 3) << (vrlg.VOSPI_GPIO + 4) rslt |= (gpio2 & 3) << (vrlg.VOSPI_GPIO + 4)
if not gpio3 is None:
rslt |= (gpio3 & 3) << (vrlg.VOSPI_GPIO + 6) # if not gpio3 is None:
# rslt |= (gpio3 & 3) << (vrlg.VOSPI_GPIO + 6)
if not telemetry is None:
rslt |= (2,3)[telemetry] << vrlg.VOSPI_TELEMETRY
if not vsync_use is None: if not vsync_use is None:
rslt |= (2,3)[vsync_use] << vrlg.VOSPI_VSYNC rslt |= (2,3)[vsync_use] << vrlg.VOSPI_VSYNC
if not noresync is None: if not noresync is None:
...@@ -1074,7 +1080,8 @@ class X393Sensor(object): ...@@ -1074,7 +1080,8 @@ class X393Sensor(object):
gpio0 = None, gpio0 = None,
gpio1 = None, gpio1 = None,
gpio2 = None, gpio2 = None,
gpio3 = None, # gpio3 = None,
telemetry = None,
vsync_use = None, vsync_use = None,
noresync = None, noresync = None,
dbg_src = None): dbg_src = None):
...@@ -1093,7 +1100,7 @@ class X393Sensor(object): ...@@ -1093,7 +1100,7 @@ class X393Sensor(object):
@param gpio0 = Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input @param gpio0 = Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input @param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input @param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio3 = Output control for GPIO0: 3 - nop, 1 - set low, 2 - set high, 3 - input @param telemetry = Enable (1) /disable (0) telemetry data lines (should be set in the sensor too, or it will hang)
@param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment @param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment
@param noresync = Disable resynchronization by discard packets @param noresync = Disable resynchronization by discard packets
@param dbg_src = source of the hardware debug output: 0 - dbg_running @param dbg_src = source of the hardware debug output: 0 - dbg_running
...@@ -1121,7 +1128,8 @@ class X393Sensor(object): ...@@ -1121,7 +1128,8 @@ class X393Sensor(object):
gpio0 = gpio0, gpio0 = gpio0,
gpio1 = gpio1, gpio1 = gpio1,
gpio2 = gpio2, gpio2 = gpio2,
gpio3 = gpio3, # gpio3 = gpio3,
telemetry = telemetry,
vsync_use = vsync_use, vsync_use = vsync_use,
noresync = noresync, noresync = noresync,
dbg_src = dbg_src) dbg_src = dbg_src)
...@@ -1141,7 +1149,8 @@ class X393Sensor(object): ...@@ -1141,7 +1149,8 @@ class X393Sensor(object):
gpio0 = gpio0, gpio0 = gpio0,
gpio1 = gpio1, gpio1 = gpio1,
gpio2 = gpio2, gpio2 = gpio2,
gpio3 = gpio3, # gpio3 = gpio3,
telemetry = telemetry,
vsync_use = vsync_use, vsync_use = vsync_use,
noresync = noresync, noresync = noresync,
dbg_src = dbg_src) dbg_src = dbg_src)
......
sensor/sens_lepton3.v
View file @ 36912bd3
...@@ -113,20 +113,22 @@ module sens_lepton3 #( ...@@ -113,20 +113,22 @@ module sens_lepton3 #(
parameter VOSPI_MCLK_BITS = 2, parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6, parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2, parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8, parameter VOSPI_OUT_EN = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2, parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12, parameter VOSPI_OUT_EN_SINGL = 10,
parameter VOSPI_RESET_ERR = 13, parameter VOSPI_RESET_ERR = 11,
parameter VOSPI_SPI_CLK = 14, parameter VOSPI_SPI_CLK = 12,
parameter VOSPI_SPI_CLK_BITS = 2, parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16, parameter VOSPI_SEGM0_OK = 14,
parameter VOSPI_GPIO_BITS = 8, parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_VSYNC = 24, parameter VOSPI_VSYNC = 16,
parameter VOSPI_VSYNC_BITS = 2, parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync parameter VOSPI_NORESYNC = 18, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2, parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_TELEMETRY = 20,
parameter VOSPI_TELEMETRY_BITS = 2,
parameter VOSPI_GPIO = 22,
parameter VOSPI_GPIO_BITS = 6,
parameter VOSPI_DBG_SRC = 28, // source of the debug output parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4, parameter VOSPI_DBG_SRC_BITS = 4,
...@@ -226,6 +228,7 @@ module sens_lepton3 #( ...@@ -226,6 +228,7 @@ module sens_lepton3 #(
reg spi_clk_en_mclk; reg spi_clk_en_mclk;
reg vsync_use_mclk; reg vsync_use_mclk;
reg noresync_mclk; reg noresync_mclk;
reg use_telemetry_mclk;
wire [ 3:0] gpio_out; // only [3] may be used wire [ 3:0] gpio_out; // only [3] may be used
wire [ 3:0] gpio_en; // none currently used wire [ 3:0] gpio_en; // none currently used
...@@ -240,6 +243,7 @@ module sens_lepton3 #( ...@@ -240,6 +243,7 @@ module sens_lepton3 #(
reg [ 1:0] spi_clk_en_pclk; reg [ 1:0] spi_clk_en_pclk;
reg [ 1:0] vsync_use_pclk; reg [ 1:0] vsync_use_pclk;
reg [ 1:0] noresync_pclk; reg [ 1:0] noresync_pclk;
reg [ 1:0] use_telemetry_pclk;
reg [ 1:0] vsync_pclk; reg [ 1:0] vsync_pclk;
wire vsync; wire vsync;
...@@ -355,6 +359,10 @@ module sens_lepton3 #( ...@@ -355,6 +359,10 @@ module sens_lepton3 #(
if (mrst) noresync_mclk <= 0; if (mrst) noresync_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_NORESYNC + VOSPI_NORESYNC_BITS - 1]) noresync_mclk <= data_r[VOSPI_NORESYNC]; else if (set_ctrl_r && data_r[VOSPI_NORESYNC + VOSPI_NORESYNC_BITS - 1]) noresync_mclk <= data_r[VOSPI_NORESYNC];
if (mrst) use_telemetry_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_TELEMETRY + VOSPI_TELEMETRY_BITS - 1]) use_telemetry_mclk <= data_r[VOSPI_TELEMETRY];
if (mrst) dbg_sel <= 0; if (mrst) dbg_sel <= 0;
else if (set_ctrl_r && data_r[VOSPI_DBG_SRC + VOSPI_DBG_SRC_BITS - 1]) dbg_sel <= data_r[VOSPI_DBG_SRC +: VOSPI_DBG_SRC_BITS-1]; else if (set_ctrl_r && data_r[VOSPI_DBG_SRC + VOSPI_DBG_SRC_BITS - 1]) dbg_sel <= data_r[VOSPI_DBG_SRC +: VOSPI_DBG_SRC_BITS-1];
...@@ -371,6 +379,7 @@ module sens_lepton3 #( ...@@ -371,6 +379,7 @@ module sens_lepton3 #(
spi_clk_en_pclk[1:0] <= {spi_clk_en_pclk[0], spi_clk_en_mclk}; spi_clk_en_pclk[1:0] <= {spi_clk_en_pclk[0], spi_clk_en_mclk};
vsync_use_pclk[1:0] <= {vsync_use_pclk[0], vsync_use_mclk}; vsync_use_pclk[1:0] <= {vsync_use_pclk[0], vsync_use_mclk};
noresync_pclk[1:0] <= {noresync_pclk[0], noresync_mclk}; noresync_pclk[1:0] <= {noresync_pclk[0], noresync_mclk};
use_telemetry_pclk[1:0] <= {use_telemetry_pclk[0], use_telemetry_mclk};
vsync_pclk[1:0] <= {vsync_pclk[0], vsync}; vsync_pclk[1:0] <= {vsync_pclk[0], vsync};
...@@ -505,15 +514,30 @@ module sens_lepton3 #( ...@@ -505,15 +514,30 @@ module sens_lepton3 #(
.IOSTANDARD (VOSPI_IOSTANDARD), .IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW) .SLEW (VOSPI_SLEW)
) gpio_i ( ) gpio_i (
.O (gpio_in[i]), // output - currently not used .O (gpio_in[i]), // output
.IO (gpio[i]), // inout I/O pad .IO (gpio[i]), // inout I/O pad
.I (gpio_out[i]), // input .I (gpio_out[i]), // input
.T (!gpio_en[i]) // input - always on .T (!gpio_en[i]) // input
); );
end end
endgenerate endgenerate
// No control bits left for GPIO[3] - it is hard-wired as input VSYNC (start of segment)
iobuf #(
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) gpio3_i (
.O (gpio_in[3]), // output
.IO (gpio[3]), // inout I/O pad
.I (1'b0), // input
.T (1'b1) // input - always off
);
// for debug/test alive // for debug/test alive
iobuf #( // lwir_mrst iobuf #( // lwir_mrst
.DRIVE (VOSPI_DRIVE), .DRIVE (VOSPI_DRIVE),
...@@ -675,6 +699,7 @@ module sens_lepton3 #( ...@@ -675,6 +699,7 @@ module sens_lepton3 #(
.vsync (vsync_pclk[1]), // input .vsync (vsync_pclk[1]), // input
.vsync_use (vsync_use_pclk[1]),// input .vsync_use (vsync_use_pclk[1]),// input
.resync_disable (noresync_pclk[1]), // input .resync_disable (noresync_pclk[1]), // input
.use_telemetry (use_telemetry_pclk[1]), // input
.spi_clken (spi_clken), // output .spi_clken (spi_clken), // output
.spi_cs (spi_cs_int), // output .spi_cs (spi_cs_int), // output
.miso (spi_miso_int), // input .miso (spi_miso_int), // input
......
sensor/sensor_channel.v
View file @ 36912bd3
...@@ -246,22 +246,25 @@ module sensor_channel#( ...@@ -246,22 +246,25 @@ module sensor_channel#(
parameter VOSPI_MCLK_BITS = 2, parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6, parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2, parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8, parameter VOSPI_OUT_EN = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2, parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12, parameter VOSPI_OUT_EN_SINGL = 10,
parameter VOSPI_RESET_ERR = 13, parameter VOSPI_RESET_ERR = 11,
parameter VOSPI_SPI_CLK = 14, parameter VOSPI_SPI_CLK = 12,
parameter VOSPI_SPI_CLK_BITS = 2, parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16, parameter VOSPI_SEGM0_OK = 14,
parameter VOSPI_GPIO_BITS = 8, parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_VSYNC = 24, parameter VOSPI_VSYNC = 16,
parameter VOSPI_VSYNC_BITS = 2, parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync parameter VOSPI_NORESYNC = 18, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2, parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_TELEMETRY = 20,
parameter VOSPI_TELEMETRY_BITS = 2,
parameter VOSPI_GPIO = 22,
parameter VOSPI_GPIO_BITS = 6,
parameter VOSPI_DBG_SRC = 28, // source of the debug output parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4, parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80, parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2, parameter VOSPI_PACKETS_PER_LINE = 2,
...@@ -1060,22 +1063,25 @@ module sensor_channel#( ...@@ -1060,22 +1063,25 @@ module sensor_channel#(
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2, .VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6, .VOSPI_EN (VOSPI_EN), // 6,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2, .VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 8, .VOSPI_OUT_EN (VOSPI_OUT_EN), // 8,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2, .VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12, .VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 10,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13, .VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 11,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14, .VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 12,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2, .VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16, .VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 14,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8, .VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_VSYNC (VOSPI_VSYNC), // 24, .VOSPI_VSYNC (VOSPI_VSYNC), // 16,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2, .VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26, .VOSPI_NORESYNC (VOSPI_NORESYNC), // 18, // disable re-sync
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2, .VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output .VOSPI_TELEMETRY (VOSPI_TELEMETRY), // 20,
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4, .VOSPI_TELEMETRY_BITS (VOSPI_TELEMETRY_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 22,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 6,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80, .VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1, .VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2, .VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
......
sensor/sensors393.v
View file @ 36912bd3
...@@ -242,22 +242,25 @@ module sensors393 #( ...@@ -242,22 +242,25 @@ module sensors393 #(
parameter VOSPI_MCLK_BITS = 2, parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6, parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2, parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8, parameter VOSPI_OUT_EN = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2, parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12, parameter VOSPI_OUT_EN_SINGL = 10,
parameter VOSPI_RESET_ERR = 13, parameter VOSPI_RESET_ERR = 11,
parameter VOSPI_SPI_CLK = 14, parameter VOSPI_SPI_CLK = 12,
parameter VOSPI_SPI_CLK_BITS = 2, parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16, parameter VOSPI_SEGM0_OK = 14,
parameter VOSPI_GPIO_BITS = 8, parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_VSYNC = 24, parameter VOSPI_VSYNC = 16,
parameter VOSPI_VSYNC_BITS = 2, parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync parameter VOSPI_NORESYNC = 18, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2, parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_TELEMETRY = 20,
parameter VOSPI_TELEMETRY_BITS = 2,
parameter VOSPI_GPIO = 22,
parameter VOSPI_GPIO_BITS = 6,
parameter VOSPI_DBG_SRC = 28, // source of the debug output parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4, parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80, parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2, parameter VOSPI_PACKETS_PER_LINE = 2,
...@@ -723,22 +726,25 @@ module sensors393 #( ...@@ -723,22 +726,25 @@ module sensors393 #(
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2, .VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6, .VOSPI_EN (VOSPI_EN), // 6,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2, .VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 8, .VOSPI_OUT_EN (VOSPI_OUT_EN), // 8,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2, .VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12, .VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 10,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13, .VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 11,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14, .VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 12,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2, .VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16, .VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 14,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8, .VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_VSYNC (VOSPI_VSYNC), // 24, .VOSPI_VSYNC (VOSPI_VSYNC), // 16,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2, .VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26, .VOSPI_NORESYNC (VOSPI_NORESYNC), // 18, // disable re-sync
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2, .VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output .VOSPI_TELEMETRY (VOSPI_TELEMETRY), // 20,
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4, .VOSPI_TELEMETRY_BITS (VOSPI_TELEMETRY_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 22,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 6,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80, .VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1, .VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2, .VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
......
sensor/vospi_packet_80.v
View file @ 36912bd3
...@@ -101,7 +101,7 @@ module vospi_packet_80#( ...@@ -101,7 +101,7 @@ module vospi_packet_80#(
// assign dmask = den_r ? 16'hffff: (wcntr[0]?16'h0: 16'h0fff); // assign dmask = den_r ? 16'hffff: (wcntr[0]?16'h0: 16'h0fff);
assign dmask = packet_header[1] ? (packet_header[0] ? 16'h0fff: 16'h0) : 16'hffff ; assign dmask = packet_header[1] ? (packet_header[0] ? 16'h0fff: 16'h0) : 16'hffff ;
assign crc_err = packet_end[2] && (crc_r != crc_w); assign crc_err = packet_end[2] && (crc_r != crc_w) && !packet_invalid_r; // discard packets have 16'hffff in CRC field, do not record error
assign sync_err = packet_end[2] && sync_err_r; assign sync_err = packet_end[2] && sync_err_r;
......
sensor/vospi_segment_61.v
View file @ 36912bd3
...@@ -61,7 +61,7 @@ module vospi_segment_61#( ...@@ -61,7 +61,7 @@ module vospi_segment_61#(
input vsync, // from GPIO[3], 70 usec on, period ~10ms (should be re-sampled to pclk input vsync, // from GPIO[3], 70 usec on, period ~10ms (should be re-sampled to pclk
input vsync_use, // if set - wait for vsync to read a segment input vsync_use, // if set - wait for vsync to read a segment
input resync_disable, // disable re-synchronizing packets using discard signature @pclk input resync_disable, // disable re-synchronizing packets using discard signature @pclk
// input use_telemetry, // use 61- packets per segment (last segment = 60), 0 - 60 packets input use_telemetry, // use 61- packets per segment (last segment = 60), 0 - 60 packets
// runs a single frame // runs a single frame
// SPI signals // SPI signals
output spi_clken, // enable clock on spi_clk output spi_clken, // enable clock on spi_clk
...@@ -85,8 +85,16 @@ module vospi_segment_61#( ...@@ -85,8 +85,16 @@ module vospi_segment_61#(
output dbg_will_sync, output dbg_will_sync,
output [ 4:0] dbg_state output [ 4:0] dbg_state
); );
localparam VOSPI_PACKET_LAST_NOTEL = VOSPI_PACKET_LAST -1;
localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) * localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) *
(VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1); (VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1);
localparam VOSPI_PACKETS_FRAME_NOTEL = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) *
(VOSPI_PACKET_LAST_NOTEL - VOSPI_PACKET_FIRST + 1);
localparam VOSPI_LINE_WIDTH = VOSPI_PACKET_WORDS * VOSPI_PACKETS_PER_LINE; localparam VOSPI_LINE_WIDTH = VOSPI_PACKET_WORDS * VOSPI_PACKETS_PER_LINE;
// save fifo write pointer, write packet full index (in the frame) // save fifo write pointer, write packet full index (in the frame)
...@@ -144,7 +152,7 @@ module vospi_segment_61#( ...@@ -144,7 +152,7 @@ module vospi_segment_61#(
assign crc_err = packet_done && packet_crc_err; // crc_err_r; assign crc_err = packet_done && packet_crc_err; // crc_err_r;
assign sync_err = packet_done && packet_sync_err; // crc_err_r; assign sync_err = packet_done && packet_sync_err; // crc_err_r;
assign segment_done_w = segment_running && packet_done && (packet_id[11:0] == VOSPI_PACKET_LAST) ; assign segment_done_w = segment_running && packet_done && (packet_id[11:0] == (use_telemetry?VOSPI_PACKET_LAST:VOSPI_PACKET_LAST_NOTEL)) ;
assign id = segment_id_r; assign id = segment_id_r;
assign frame_in_done = segment_done_w && last_segment_in; assign frame_in_done = segment_done_w && last_segment_in;
...@@ -257,12 +265,12 @@ module vospi_segment_61#( ...@@ -257,12 +265,12 @@ module vospi_segment_61#(
// wire sync_end; // wire sync_end;
wire will_sync; wire will_sync;
// wire [ 4:0] dbg_state; // wire [ 4:0] dbg_state;
wire [7:0] packets_frame = use_telemetry?VOSPI_PACKETS_FRAME:VOSPI_PACKETS_FRAME_NOTEL;
assign start_out_frame_w = segment_good && is_first_segment_w && out_request; assign start_out_frame_w = segment_good && is_first_segment_w && out_request;
assign packets_avail = {1'b0,full_packet_verified} - {1'b0,full_packet_out} - VOSPI_PACKETS_PER_LINE; assign packets_avail = {1'b0,full_packet_verified} - {1'b0,full_packet_out} - VOSPI_PACKETS_PER_LINE;
// assign frame_out_done_w = packet_out_done && (full_packet_out == (VOSPI_PACKETS_FRAME - 1)); // assign frame_out_done_w = hact_end_w && (full_packet_out == (VOSPI_PACKETS_FRAME - VOSPI_PACKETS_PER_LINE));
assign frame_out_done_w = hact_end_w && (full_packet_out == (VOSPI_PACKETS_FRAME - VOSPI_PACKETS_PER_LINE)); assign frame_out_done_w = hact_end_w && (full_packet_out == (packets_frame - VOSPI_PACKETS_PER_LINE));
assign frame_dav = !packets_avail[8] || out_pending; assign frame_dav = !packets_avail[8] || out_pending;
assign hact_start_w = out_frame && (duration_cntr == 0) && !hact_r[0] && frame_dav; assign hact_start_w = out_frame && (duration_cntr == 0) && !hact_r[0] && frame_dav;
......
x393.v
View file @ 36912bd3
...@@ -1843,6 +1843,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1843,6 +1843,7 @@ assign axi_grst = axi_rst_pre;
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR), .VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.VOSPI_IOSTANDARD (VOSPI_IOSTANDARD), .VOSPI_IOSTANDARD (VOSPI_IOSTANDARD),
.VOSPI_SLEW (VOSPI_SLEW), .VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0, .VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2, .VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2, .VOSPI_PWDN (VOSPI_PWDN), // 2,
...@@ -1851,22 +1852,25 @@ assign axi_grst = axi_rst_pre; ...@@ -1851,22 +1852,25 @@ assign axi_grst = axi_rst_pre;
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2, .VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6, .VOSPI_EN (VOSPI_EN), // 6,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2, .VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 8, .VOSPI_OUT_EN (VOSPI_OUT_EN), // 8,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2, .VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12, .VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 10,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13, .VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 11,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14, .VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 12,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2, .VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16, .VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 14,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8, .VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_VSYNC (VOSPI_VSYNC), // 24, .VOSPI_VSYNC (VOSPI_VSYNC), // 16,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2, .VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26, .VOSPI_NORESYNC (VOSPI_NORESYNC), // 18, // disable re-sync
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2, .VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output .VOSPI_TELEMETRY (VOSPI_TELEMETRY), // 20,
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4, .VOSPI_TELEMETRY_BITS (VOSPI_TELEMETRY_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 22,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 6,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80, .VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1, .VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2, .VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
......
x393_vospi.bit
View file @ 36912bd3
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x393_vospi.timing_summary_impl
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x393_vospi_utilization.report
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu Apr 25 19:12:25 2019 | Date : Fri Apr 26 13:14:46 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS | Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_vospi_utilization.report | Command : report_utilization -file vivado_build/x393_vospi_utilization.report
| Design : x393 | Design : x393
...@@ -31,13 +31,13 @@ Table of Contents ...@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+ +----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+ +----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 42007 | 0 | 78600 | 53.44 | | Slice LUTs | 42027 | 0 | 78600 | 53.47 |
| LUT as Logic | 38653 | 0 | 78600 | 49.18 | | LUT as Logic | 38670 | 0 | 78600 | 49.20 |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 | | LUT as Memory | 3357 | 0 | 26600 | 12.62 |
| LUT as Distributed RAM | 2802 | 0 | | | | LUT as Distributed RAM | 2802 | 0 | | |
| LUT as Shift Register | 552 | 0 | | | | LUT as Shift Register | 555 | 0 | | |
| Slice Registers | 54028 | 0 | 157200 | 34.37 | | Slice Registers | 54031 | 0 | 157200 | 34.37 |
| Register as Flip Flop | 54028 | 0 | 157200 | 34.37 | | Register as Flip Flop | 54031 | 0 | 157200 | 34.37 |
| Register as Latch | 0 | 0 | 157200 | 0.00 | | Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 34 | 0 | 39300 | 0.09 | | F7 Muxes | 34 | 0 | 39300 | 0.09 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 | | F8 Muxes | 0 | 0 | 19650 | 0.00 |
...@@ -59,7 +59,7 @@ Table of Contents ...@@ -59,7 +59,7 @@ Table of Contents
| 8 | Yes | - | Set | | 8 | Yes | - | Set |
| 672 | Yes | - | Reset | | 672 | Yes | - | Reset |
| 1025 | Yes | Set | - | | 1025 | Yes | Set | - |
| 52323 | Yes | Reset | - | | 52326 | Yes | Reset | - |
+-------+--------------+-------------+--------------+ +-------+--------------+-------------+--------------+
...@@ -69,27 +69,27 @@ Table of Contents ...@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+ +-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+ +-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16758 | 0 | 19650 | 85.28 | | Slice | 16731 | 0 | 19650 | 85.15 |
| SLICEL | 11056 | 0 | | | | SLICEL | 11080 | 0 | | |
| SLICEM | 5702 | 0 | | | | SLICEM | 5651 | 0 | | |
| LUT as Logic | 38653 | 0 | 78600 | 49.18 | | LUT as Logic | 38670 | 0 | 78600 | 49.20 |
| using O5 output only | 4 | | | | | using O5 output only | 3 | | | |
| using O6 output only | 30042 | | | | | using O6 output only | 30067 | | | |
| using O5 and O6 | 8607 | | | | | using O5 and O6 | 8600 | | | |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 | | LUT as Memory | 3357 | 0 | 26600 | 12.62 |
| LUT as Distributed RAM | 2802 | 0 | | | | LUT as Distributed RAM | 2802 | 0 | | |
| using O5 output only | 2 | | | | | using O5 output only | 2 | | | |
| using O6 output only | 84 | | | | | using O6 output only | 84 | | | |
| using O5 and O6 | 2716 | | | | | using O5 and O6 | 2716 | | | |
| LUT as Shift Register | 552 | 0 | | | | LUT as Shift Register | 555 | 0 | | |
| using O5 output only | 284 | | | | | using O5 output only | 292 | | | |
| using O6 output only | 216 | | | | | using O6 output only | 214 | | | |
| using O5 and O6 | 52 | | | | | using O5 and O6 | 49 | | | |
| LUT Flip Flop Pairs | 24321 | 0 | 78600 | 30.94 | | LUT Flip Flop Pairs | 24382 | 0 | 78600 | 31.02 |
| fully used LUT-FF pairs | 4523 | | | | | fully used LUT-FF pairs | 4517 | | | |
| LUT-FF pairs with one unused LUT output | 17611 | | | | | LUT-FF pairs with one unused LUT output | 17666 | | | |
| LUT-FF pairs with one unused Flip Flop | 17555 | | | | | LUT-FF pairs with one unused Flip Flop | 17598 | | | |
| Unique Control Sets | 4740 | | | | | Unique Control Sets | 4737 | | | |
+-------------------------------------------+-------+-------+-----------+-------+ +-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets. * Note: Review the Control Sets Report for more information regarding control sets.
...@@ -196,15 +196,15 @@ Table of Contents ...@@ -196,15 +196,15 @@ Table of Contents
+------------------------+-------+----------------------+ +------------------------+-------+----------------------+
| Ref Name | Used | Functional Category | | Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+ +------------------------+-------+----------------------+
| FDRE | 52323 | Flop & Latch | | FDRE | 52326 | Flop & Latch |
| LUT3 | 11324 | LUT | | LUT3 | 11339 | LUT |
| LUT6 | 10228 | LUT | | LUT6 | 10220 | LUT |
| LUT2 | 8361 | LUT | | LUT2 | 8365 | LUT |
| LUT4 | 7952 | LUT | | LUT4 | 7941 | LUT |
| LUT5 | 7803 | LUT | | LUT5 | 7821 | LUT |
| RAMD32 | 4126 | Distributed Memory | | RAMD32 | 4126 | Distributed Memory |
| CARRY4 | 2725 | CarryLogic | | CARRY4 | 2733 | CarryLogic |
| LUT1 | 1592 | LUT | | LUT1 | 1584 | LUT |
| RAMS32 | 1392 | Distributed Memory | | RAMS32 | 1392 | Distributed Memory |
| FDSE | 1025 | Flop & Latch | | FDSE | 1025 | Flop & Latch |
| FDCE | 672 | Flop & Latch | | FDCE | 672 | Flop & Latch |
......
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