// registers may be inserted before byte_ad and ad_stb
.byte_ad(byte_ad),// output[7:0]
.ad_stb(ad_stb)// output
);
//MEMCLK
wire[63:0]gpio_in;
assigngpio_in={
frst[3]?{
16'b0,
1'b1,// 1
1'b0,//MEMCLK, // 1/0? - external clock
1'b0,//
1'b0,//
frst[1],// 0 (follows)
fclk[1:0],// 2'bXX (toggle)
axird_dev_busy,// 0
4'b0,// 4'b0
4'b0,// 4'b0
tmp_debug[7:4],// 4'b0111 -> 4'bx00x
// dly_addr[1], 0
// dly_addr[0], 0
// clkin_stopped_mmcm, 0
// clkfb_stopped_mmcm, 0
tmp_debug[3:0],// 4'b1100 -> 4'bxx00
// ddr_rst, 1 1 4000609c -> 0 , 40006098 -> 1
// rst_in, 0 0
// dci_rst, 0 1
// dly_rst 0 1
phy_locked_mmcm,// 1 1
phy_locked_pll,// 1 1
phy_dci_ready,// 1 0
phy_dly_ready,// 1 0
locked_mmcm,// 1 1
locked_pll,// 1 1
dci_ready,// 1 0
dly_ready// 1 0
}:{
waddr_wcount[3:0],
waddr_rcount[3:0],
waddr_num_in_fifo[3:0],
wdata_wcount[3:0],
wdata_rcount[3:0],
wdata_num_in_fifo[3:0],
wresp_wcount[3:0],
wresp_rcount[3:0],
wresp_num_in_fifo[3:0],
wleft[3:0],
wlength[3:0],
wlen_in_dbg[3:0]
},
//ps_out[7:4], // 4'b0 input[7:0] 4'b0
//ps_out[3:0], // 4'b0 input[7:0] 4'b0
1'b0,
waddr_under_r,
wdata_under_r,
wresp_under_r,
1'b0,
waddr_over_r,
wdata_over_r,
wresp_over_r,// ???
run_busy,// input // 0
locked,// input // 1
ps_rdy,// input // 1
axi_arready,// 1
axi_awready,// 1
axi_wready,// 1 - sometimes gets stuck with 0 (axi_awready==1) ? TODO: Add timeout
fifo_rst,// fclk[0], // 0/1
axi_rst_pre//axi_rst // 0
};
axibram_write#(
.ADDRESS_BITS(AXI_WR_ADDR_BITS)
)axibram_write_i(//SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
