Commit 2d984f96 authored by Andrey Filippov's avatar Andrey Filippov

Annotated and cleaned up signal output in simulation wave viewer

parent 2e520be5
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sun Dec 31 05:57:37 2017
[*] Wed Jan 3 23:47:04 2018
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_06-20171230225640461.fst"
[dumpfile_mtime] "Sun Dec 31 05:56:44 2017"
[dumpfile_size] 1539177
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_06-20171230225821093.fst"
[dumpfile_mtime] "Sun Dec 31 05:58:25 2017"
[dumpfile_size] 1479844
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_06.sav"
[timestart] 0
[size] 1824 1171
[pos] 0 0
*-21.247999 5735000 4825000 5405000 6875000 6955000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[size] 1710 1114
[pos] 21 13
*-21.247999 7445000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_06.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.dsp_fold_cs_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_b_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_g_i.
[treeopen] mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.phase_rotator0_i.
[sst_width] 283
[signals_width] 321
[sst_width] 249
[signals_width] 298
[sst_expanded] 1
[sst_vpaned_height] 343
[sst_vpaned_height] 325
@22
mclt_test_06.PAGE
@28
mclt_test_06.CLK
mclt_test_06.START
@c00201
-top_details
@28
mclt_test_06.LATE
mclt_test_06.PRE_BUSY
mclt_test_06.pending
mclt_test_06.pre_busy3
mclt_test_06.start3
@420
mclt_test_06.n
@28
mclt_test_06.PIX_COPY_PAGE3
mclt_test_06.PIX_RE3D
@c00022
mclt_test_06.PIX_ADDR103[10:0]
@28
(0)mclt_test_06.PIX_ADDR103[10:0]
(1)mclt_test_06.PIX_ADDR103[10:0]
(2)mclt_test_06.PIX_ADDR103[10:0]
(3)mclt_test_06.PIX_ADDR103[10:0]
(4)mclt_test_06.PIX_ADDR103[10:0]
(5)mclt_test_06.PIX_ADDR103[10:0]
(6)mclt_test_06.PIX_ADDR103[10:0]
(7)mclt_test_06.PIX_ADDR103[10:0]
(8)mclt_test_06.PIX_ADDR103[10:0]
(9)mclt_test_06.PIX_ADDR103[10:0]
(10)mclt_test_06.PIX_ADDR103[10:0]
@1401200
-group_end
@22
mclt_test_06.PIX_D3[15:0]
@200
-
@1401201
-top_details
mclt_test_06.START
@c00022
mclt_test_06.wnd_a_w[7:0]
@28
......@@ -132,45 +98,10 @@ mclt_test_06.jav_pix_in_now_d[15:0]
-group_end
@420
mclt_test_06.diff1
@c00200
-mclt
@28
mclt_test_06.mclt16x16_bayer3_i.set_inv_checker
mclt_test_06.mclt16x16_bayer3_i.set_valid_odd
mclt_test_06.mclt16x16_bayer3_i.set_top_left
mclt_test_06.mclt16x16_bayer3_i.set_x_shft
mclt_test_06.mclt16x16_bayer3_i.set_y_shft
@22
mclt_test_06.mclt16x16_bayer3_i.color_wa[1:0]
@28
mclt_test_06.mclt16x16_bayer3_i.inv_checker
mclt_test_06.mclt16x16_bayer3_i.start
(1)mclt_test_06.mclt16x16_bayer3_i.copy_regs[1:0]
(0)mclt_test_06.mclt16x16_bayer3_i.copy_regs[1:0]
@22
mclt_test_06.mclt16x16_bayer3_i.regs_wa[1:0]
@28
mclt_test_06.mclt16x16_bayer3_i.inv_checker_rf_ram_reg
mclt_test_06.mclt16x16_bayer3_i.valid_odd_rf_ram_reg
@22
mclt_test_06.mclt16x16_bayer3_i.x_shft_rf_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.y_shft_rf_ram_reg[6:0]
@28
(1)mclt_test_06.mclt16x16_bayer3_i.start_block_r[1:0]
(0)mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0]
(1)mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0]
mclt_test_06.mclt16x16_bayer3_i.inv_checker_ram_reg
mclt_test_06.mclt16x16_bayer3_i.valid_odd_ram_reg
@22
mclt_test_06.mclt16x16_bayer3_i.top_left_ram_reg[7:0]
mclt_test_06.mclt16x16_bayer3_i.x_shft_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.y_shft_ram_reg[6:0]
mclt_test_06.n4
@200
-
@1401200
-mclt
-Folder output match
@420
mclt_test_06.n4
mclt_test_06.p4
@c08022
mclt_test_06.cntr4
......@@ -214,10 +145,11 @@ mclt_test_06.data_dtt_in[24:0]
mclt_test_06.java_data_dtt_in[24:0]
@8420
mclt_test_06.diff4
@200
-
@420
mclt_test_06.n5
@200
-DTT input match
@420
mclt_test_06.p5
@22
mclt_test_06.page5[3:0]
......@@ -244,6 +176,82 @@ mclt_test_06.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
-group_end
@22
mclt_test_06.mclt16x16_bayer3_i.dtt_r_data[24:0]
@28
mclt_test_06.dtt_pre_last_out_g
@200
-DTT output match
@22
mclt_test_06.dtt_rd_data_r[24:0]
mclt_test_06.dtt_rd_data_b[24:0]
mclt_test_06.dtt_rd_data_g[24:0]
mclt_test_06.java_dtt_rd_data_rd[24:0]
mclt_test_06.java_dtt_rd_data_bd[24:0]
mclt_test_06.java_dtt_rd_data_gd[24:0]
@28
mclt_test_06.dtt_rd_regen_rv
mclt_test_06.dtt_rd_regen_bv
mclt_test_06.dtt_rd_regen_gv
@8420
mclt_test_06.diff6r
mclt_test_06.diff6b
mclt_test_06.diff6g
@200
-Rotators output match
@28
mclt_test_06.pre_first_out_r
@8022
mclt_test_06.out_addr_r[8:0]
@22
mclt_test_06.dout_r[24:0]
mclt_test_06.java_dout_r[24:0]
mclt_test_06.dout_b[24:0]
@8022
mclt_test_06.out_addr_b[8:0]
mclt_test_06.out_addr_g[8:0]
@22
mclt_test_06.dout_g[24:0]
mclt_test_06.java_dout_g[24:0]
@8420
mclt_test_06.diff7r
mclt_test_06.diff7b
mclt_test_06.diff7g
@200
-
@c00200
-top_details
@28
mclt_test_06.LATE
mclt_test_06.PRE_BUSY
mclt_test_06.pending
mclt_test_06.pre_busy3
mclt_test_06.start3
@420
mclt_test_06.n
@28
mclt_test_06.PIX_COPY_PAGE3
mclt_test_06.PIX_RE3D
@c00022
mclt_test_06.PIX_ADDR103[10:0]
@28
(0)mclt_test_06.PIX_ADDR103[10:0]
(1)mclt_test_06.PIX_ADDR103[10:0]
(2)mclt_test_06.PIX_ADDR103[10:0]
(3)mclt_test_06.PIX_ADDR103[10:0]
(4)mclt_test_06.PIX_ADDR103[10:0]
(5)mclt_test_06.PIX_ADDR103[10:0]
(6)mclt_test_06.PIX_ADDR103[10:0]
(7)mclt_test_06.PIX_ADDR103[10:0]
(8)mclt_test_06.PIX_ADDR103[10:0]
(9)mclt_test_06.PIX_ADDR103[10:0]
(10)mclt_test_06.PIX_ADDR103[10:0]
@1401200
-group_end
@22
mclt_test_06.PIX_D3[15:0]
@200
-
@1401200
-top_details
@c00200
-tmp
@28
......@@ -263,18 +271,8 @@ mclt_test_06.ROT_RAM_PAGE[3:0]
@28
mclt_test_06.dtt_pre_last_out_r
mclt_test_06.dtt_pre_last_out_g
@c00022
mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
@28
(0)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(1)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(2)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(3)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(4)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(5)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(6)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(7)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
(8)mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
@c00200
-mclt_test_06.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre
@1401200
-group_end
@c00022
......@@ -292,45 +290,6 @@ mclt_test_06.DTT_OUT_RAM_CNTR[5:0]
mclt_test_06.dtt_rd_ra_g[7:0]
@200
-
@1401200
-tmp
@28
mclt_test_06.dtt_pre_last_out_g
@22
mclt_test_06.dtt_rd_data_r[24:0]
mclt_test_06.dtt_rd_data_b[24:0]
mclt_test_06.dtt_rd_data_g[24:0]
mclt_test_06.java_dtt_rd_data_rd[24:0]
mclt_test_06.java_dtt_rd_data_bd[24:0]
mclt_test_06.java_dtt_rd_data_gd[24:0]
@28
mclt_test_06.dtt_rd_regen_rv
mclt_test_06.dtt_rd_regen_bv
mclt_test_06.dtt_rd_regen_gv
@8420
mclt_test_06.diff6r
mclt_test_06.diff6b
mclt_test_06.diff6g
@200
-
@22
mclt_test_06.out_addr_r[8:0]
mclt_test_06.dout_r[24:0]
mclt_test_06.java_dout_r[24:0]
@28
mclt_test_06.pre_first_out_r
@22
mclt_test_06.dout_b[24:0]
mclt_test_06.out_addr_b[8:0]
mclt_test_06.out_addr_g[8:0]
mclt_test_06.dout_g[24:0]
mclt_test_06.java_dout_g[24:0]
@8420
mclt_test_06.diff7r
mclt_test_06.diff7b
mclt_test_06.diff7g
@200
-
@420
mclt_test_06.n7r
@22
......@@ -343,6 +302,45 @@ mclt_test_06.cntr7b[7:0]
mclt_test_06.n7g
@22
mclt_test_06.cntr7g[7:0]
@1401200
-tmp
@c00200
-mclt
@28
mclt_test_06.mclt16x16_bayer3_i.set_inv_checker
mclt_test_06.mclt16x16_bayer3_i.set_valid_odd
mclt_test_06.mclt16x16_bayer3_i.set_top_left
mclt_test_06.mclt16x16_bayer3_i.set_x_shft
mclt_test_06.mclt16x16_bayer3_i.set_y_shft
@22
mclt_test_06.mclt16x16_bayer3_i.color_wa[1:0]
@28
mclt_test_06.mclt16x16_bayer3_i.inv_checker
mclt_test_06.mclt16x16_bayer3_i.start
(1)mclt_test_06.mclt16x16_bayer3_i.copy_regs[1:0]
(0)mclt_test_06.mclt16x16_bayer3_i.copy_regs[1:0]
@22
mclt_test_06.mclt16x16_bayer3_i.regs_wa[1:0]
@28
mclt_test_06.mclt16x16_bayer3_i.inv_checker_rf_ram_reg
mclt_test_06.mclt16x16_bayer3_i.valid_odd_rf_ram_reg
@22
mclt_test_06.mclt16x16_bayer3_i.x_shft_rf_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.y_shft_rf_ram_reg[6:0]
@28
(1)mclt_test_06.mclt16x16_bayer3_i.start_block_r[1:0]
(0)mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0]
(1)mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0]
mclt_test_06.mclt16x16_bayer3_i.inv_checker_ram_reg
mclt_test_06.mclt16x16_bayer3_i.valid_odd_ram_reg
@22
mclt_test_06.mclt16x16_bayer3_i.top_left_ram_reg[7:0]
mclt_test_06.mclt16x16_bayer3_i.x_shft_ram_reg[6:0]
mclt_test_06.mclt16x16_bayer3_i.y_shft_ram_reg[6:0]
@200
-
@1401200
-mclt
@c00200
-mclt16x16
@28
......@@ -490,7 +488,6 @@ mclt_test_06.mclt16x16_bayer3_i.set_inv_checker
mclt_test_06.mclt16x16_bayer3_i.in_cntr[7:0]
@28
mclt_test_06.mclt16x16_bayer3_i.inv_checker_rf_ram_reg
mclt_test_06.mclt16x16_bayer3_i.page
@22
mclt_test_06.mclt16x16_bayer3_i.regs_wa[1:0]
@200
......
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