working on DSP-based 8x8 DCT implementing Chen algorithm

2d4c00bf · Andrey Filippov · c4619853 · 2d4c00bf · 2d4c00bf · 2d4c00bf
Commit 2d4c00bf authored Jun 12, 2016 by Andrey Filippov
12 changed files
--- a/compressor_jp/jp_channel.v
+++ b/compressor_jp/jp_channel.v
@@ -991,6 +991,39 @@ module  jp_channel#(
        .dv                 (),  // not used: output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
        .d_out              (dct_out)              // output[12:0] 
    );
+    
+    /* New DCT, now in passive mode */
+    // TODO: enforce minimal pause (when not butted together)
+    wire        dct_last_in_debug;
+    wire        dct_pre_first_out_debug;
+    wire        dct_dv_debug;
+    wire [12:0] dct_dout_debug;
+    
+    dct2d8x8_chen #(
+        .INPUT_WIDTH      (10),
+        .OUTPUT_WIDTH     (13),
+        .STAGE1_SAFE_BITS (3),
+        .STAGE2_SAFE_BITS (3),
+        .TRANSPOSE_WIDTH  (16),
+        .TRIM_STAGE_1     (0),
+        .TRIM_STAGE_2     (2),
+        .DSP_WIDTH        (24),
+        .DSP_OUT_WIDTH    (24),
+        .DSP_B_WIDTH      (18),
+        .DSP_A_WIDTH      (25),
+        .DSP_P_WIDTH      (48),
+        .DSP_M_WIDTH      (43)
+    ) dct2d8x8_chen_i (
+        .clk           (xclk),                    // input
+        .rst           (!frame_en),               // input
+        .start         (dct_start),               // input
+        .xin           (yc_nodc),                 // input[9:0] signed 
+        .last_in       (dct_last_in_debug),       // output reg 
+        .pre_first_out (dct_pre_first_out_debug), // output
+        .dv            (dct_dv_debug),            // output
+        .d_out         (dct_dout_debug)           // output[12:0] signed 
+    );
+    
 `endif    
    
    wire          quant_start;

--- a/dsp/dct1d_chen.v
+++ b/dsp/dct1d_chen.v
@@ -40,18 +40,19 @@

 module  dct1d_chen#(
    parameter WIDTH = 24,
-    parameter OUT_WIDTH = 24,
-    parameter B_WIDTH = 18,
-    parameter A_WIDTH = 25,
-    parameter P_WIDTH = 48,
-    parameter M_WIDTH = 43, // actual multiplier width (== (A_WIDTH +B_WIDTH)
-    parameter COS_1_16 = 128553, // (1<<17) * cos(1*pi/16)
-    parameter COS_2_16 = 121095, // (2<<17) * cos(1*pi/16)
-    parameter COS_3_16 = 108982, // (3<<17) * cos(1*pi/16)
-    parameter COS_4_16 =  92682, // (4<<17) * cos(1*pi/16)
-    parameter COS_5_16 =  72820, // (5<<17) * cos(1*pi/16)
-    parameter COS_6_16 =  50159, // (6<<17) * cos(1*pi/16)
-    parameter COS_7_16 =  25570  // (7<<17) * cos(1*pi/16)
+    parameter OUT_WIDTH =   24,
+    parameter B_WIDTH =     18,
+    parameter A_WIDTH =     25,
+    parameter P_WIDTH =     48,
+    parameter M_WIDTH =     43, // actual multiplier width (== (A_WIDTH +B_WIDTH)
+    parameter COSINE_SHIFT= 17,
+    parameter COS_1_16 =    128553, // (1<<17) * cos(1*pi/16)
+    parameter COS_2_16 =    121095, // (2<<17) * cos(1*pi/16)
+    parameter COS_3_16 =    108982, // (3<<17) * cos(1*pi/16)
+    parameter COS_4_16 =    92682, // (4<<17) * cos(1*pi/16)
+    parameter COS_5_16 =    72820, // (5<<17) * cos(1*pi/16)
+    parameter COS_6_16 =    50159, // (6<<17) * cos(1*pi/16)
+    parameter COS_7_16 =    25570  // (7<<17) * cos(1*pi/16)
 )(
    input                          clk,
    input                          rst,
@@ -59,8 +60,9 @@ module  dct1d_chen#(
    input  [2 * WIDTH -1:0]        d10_32_76_54, // Concatenated input data {x[1],x[0]}/{x[3],x[2]}/ {x[7],x[6]}/{x[5],x[4]}
    input                          start,      // {x[1],x[0]} available next after start,  {x[3],x[2]} - second next, then {x[7],x[6]} and {x[5],x[4]} 
    output [WIDTH -1:0]            dout,
-    output                         pre2_start_out // 2 clock cycle before F4 output, full dout sequence
+    output reg                     pre2_start_out, // 2 clock cycle before F4 output, full dout sequence
                                             // start_out-X-F4-X-F2-X-F6-F5-F0-F3-X-F1-X-F7
+    output reg                     en_out    // valid at the same time slot as pre2_start_out (goes active with pre2_start_out)                                      
 );
    reg    signed [B_WIDTH-1:0] dsp_ma_bin;
    wire                        dsp_ma_ceb1_1;     // load b1 register
@@ -74,7 +76,7 @@ module  dct1d_chen#(
    wire                        dsp_ma_sela_1;
    wire                        dsp_ma_en_a_1;      // 0: +/- D, 1: A or A +/- D 
    wire                        dsp_ma_en_d_1;      // 0: A, 1: D  or A +/- D 
-    wire                        dsp_ma_sub_d_1;     // 1 when  - D, 0 - all other
+    wire                        dsp_ma_sub_a_1;     //
    wire                        dsp_ma_neg_m_1;    // 1 - negate multiplier result
    wire                        dsp_ma_accum_1;    // 0 - use multiplier result, 1 add to accumulator
    wire   signed [P_WIDTH-1:0] dsp_ma_p_1;
@@ -125,8 +127,8 @@ module  dct1d_chen#(
    
    wire                        simd_cea01;
    wire                        simd_cea23;
-    wire                        simd_ceaf45; // first stage A registers CE
-    wire                        simd_ceas45; // second stage A registers CE
+    wire                        simd_cea45; // first stage A registers CE
+//    wire                        simd_ceas45; // second stage A registers CE
    wire                        simd_ceb01;
    wire                        simd_ceb23;
    wire                        simd_ceb45;  // B registers CE
@@ -138,10 +140,11 @@ module  dct1d_chen#(
    wire                        simd_cep45;

    reg                   [7:0] phase;
-    reg                   [3:0] phase_cnt;
+    reg                   [2:0] phase_cnt;
    reg        [OUT_WIDTH -1:0] dout_r;
    wire       [OUT_WIDTH -1:0] dout1_w;
    wire       [OUT_WIDTH -1:0] dout2_w;
+    reg                   [2:0] per_type; // idle/last:0, first cycle - 1, 2-nd - 2, other - 3,... ~en->6 ->7 -> 0  (to generate pre2_start_out)

 //        .ain      ({simd_a1,simd_a0}), // input[47:0] 
 //        .bin      ({simd_b1,simd_b0}), // input[47:0]
@@ -156,7 +159,8 @@ module  dct1d_chen#(
    assign simd_ceb01 =  phase[2] | phase[5];

    assign simd_sub01 = phase[3] | phase[6];
-    assign simd_cep01 = phase[2] | phase[3] | phase[5] | phase[6];
+//    assign simd_cep01 = phase[2] | phase[3] | phase[5] | phase[6];
+    assign simd_cep01 = phase[3] | phase[4] | phase[6] | phase[7];
    
    // dsp_addsub_simd2_i input connections
    assign  simd_a2 = phase[1]? d10_32_76_54[0 * WIDTH +: WIDTH] : simd_p0; // only phase[1] & phase[7], other phases - don't care
@@ -169,25 +173,35 @@ module  dct1d_chen#(
    assign simd_ceb23 =  phase[3] | phase[7];

    assign simd_sub23 = phase[4] | phase[7];
-    assign simd_cep23 = phase[0] | phase[3] | phase[4] | phase[7];
+//    assign simd_cep23 = phase[0] | phase[3] | phase[4] | phase[7];
+    assign simd_cep23 = phase[0] | phase[1] | phase[4] | phase[5];
    
    assign  simd_a4 = simd_p3; // only at phase[6], other phases - don't care
    assign  simd_a5 = simd_p0; // only at phase[6], other phases - don't care

    // dsp_addsub_reg2_simd_i input connections
-    assign  simd_b4 = dsp_ma_p_1[M_WIDTH-1 -: WIDTH]; // only at phase[6], other phases - don't care. TODO: add symmetric rounding here?
-    assign  simd_b5 = dsp_ma_p_1[M_WIDTH-1 -: WIDTH]; // only at phase[2], other phases - don't care. TODO: add symmetric rounding here?
+//    assign  simd_b4 = dsp_ma_p_1[M_WIDTH-1 -: WIDTH]; // only at phase[6], other phases - don't care. TODO: add symmetric rounding here?
+//    assign  simd_b5 = dsp_ma_p_1[M_WIDTH-1 -: WIDTH]; // only at phase[2], other phases - don't care. TODO: add symmetric rounding here?

-    assign simd_ceaf45 = phase[6];
-    assign simd_ceas45 = phase[2];
+    assign  simd_b4 = dsp_ma_p_1[COSINE_SHIFT +: WIDTH]; // only at phase[6], other phases - don't care. TODO: add symmetric rounding here?
+    assign  simd_b5 = dsp_ma_p_1[COSINE_SHIFT +: WIDTH]; // only at phase[2], other phases - don't care. TODO: add symmetric rounding here?
+
+
+
+
+//COSINE_SHIFT
+
+    assign simd_cea45 = phase[6];
+//    assign simd_ceas45 = phase[2];
    assign simd_ceb45 =  phase[2] | phase[4];

    assign simd_sub45 = phase[2] | phase[4];
-    assign simd_cep45 = phase[2] | phase[3] | phase[4] | phase[5];
+//    assign simd_cep45 = phase[2] | phase[3] | phase[4] | phase[5];
+    assign simd_cep45 = phase[3] | phase[4] | phase[5] | phase[6];
    
    // dsp_ma1_i control connections
-    assign dsp_ma_ceb1_1 =  phase[3] | phase[7];
-    assign dsp_ma_ceb2_1 =  phase[0];
+    assign dsp_ma_ceb1_1 =  phase[4] | phase[7];
+    assign dsp_ma_ceb2_1 =  phase[1];
    assign dsp_ma_selb_1 =  phase[3] | phase[6];
    assign dsp_ma_cea1_1 =  phase[2] | phase[6];
    assign dsp_ma_cea2_1 =  phase[1] | phase[3];
@@ -195,7 +209,7 @@ module  dct1d_chen#(
    assign dsp_ma_sela_1 =  phase[1] | phase[7];
    assign dsp_ma_en_a_1 =  !(phase[2] | phase[4]);
    assign dsp_ma_en_d_1 =  phase[0] | phase[2] | phase[4] | phase[6];
-    assign dsp_ma_sub_d_1 = phase[0];
+    assign dsp_ma_sub_a_1 = phase[0];
    assign dsp_ma_neg_m_1 = phase[6];
    assign dsp_ma_accum_1 = phase[5] | phase[7];
    // dsp_ma1_i data input connections
@@ -203,53 +217,83 @@ module  dct1d_chen#(
                            ({WIDTH{phase[1]}} & simd_p2) |
                            ({WIDTH{phase[2]}} & simd_p0) |
                            ({WIDTH{phase[3]}} & simd_p2) ; // Other - don't care */
-    assign dsp_ma_ain24_1 = phase[6] ? simd_p1 : (phase[2] ? simd_p0 : simd_p2); 
-    assign dsp_ma_din24_1 = phase[6] ? simd_p2 :  simd_p1; 
+    // Swapping A and d for pre-added (it is D-A, not A-D)                            
+//    assign dsp_ma_ain24_1 = phase[6] ? simd_p1 : (phase[2] ? simd_p0 : simd_p2); 
+//    assign dsp_ma_din24_1 = phase[6] ? simd_p2 :  simd_p1; 
+    assign dsp_ma_ain24_1 = phase[6] ? simd_p2 : (phase[2] ? simd_p0 : simd_p2); 
+//    assign dsp_ma_din24_1 = phase[6] ? simd_p1 :  simd_p1; 
+    assign dsp_ma_din24_1 = simd_p1; 

    // dsp_ma2_i control connections
-    assign dsp_ma_ceb1_2 = phase[1] | phase[6];
+    assign dsp_ma_ceb1_2 = phase[3] | phase[6];
    assign dsp_ma_ceb2_2 = phase[2] | phase[5];
-    assign dsp_ma_selb_2 = phase[1] | phase[3] | phase[5] | phase[7];
+    assign dsp_ma_selb_2 = phase[0] | phase[2] | phase[4] | phase[6];
    assign dsp_ma_cea1_2 = phase[5];
    assign dsp_ma_cea2_2 = phase[4];
    assign dsp_ma_ced_2 =  phase[1] | phase[6];
    assign dsp_ma_sela_2 =  phase[1] | phase[6];
-    assign dsp_ma_seld_2 =  phase[0] | phase[3] | phase[4] | phase[7];
+    assign dsp_ma_seld_2 =  phase[0] | phase[2] | phase[5] | phase[7];
    assign dsp_ma_neg_m_2 = phase[6];
    assign dsp_ma_accum_2 = phase[0] | phase[2] | phase[4] | phase[6];
    // dsp_ma2_i data input connections
    assign dsp_ma_ain24_2 = simd_p5; 
    assign dsp_ma_din24_2 = simd_p4; 

-    assign dsp_ma_din24_1 = phase[6] ? simd_p2 :  simd_p1; 
-
-
 // Shift adder outputs to the MSB of the multiplier inputs
-    assign dsp_ma_ain_1 = {dsp_ma_ain24_1, {A_WIDTH-WIDTH{1'b0}}};   
-    assign dsp_ma_din_1 = {dsp_ma_din24_1, {A_WIDTH-WIDTH{1'b0}}};   
-    assign dsp_ma_ain_2 = {dsp_ma_ain24_2, {A_WIDTH-WIDTH{1'b0}}};   
-    assign dsp_ma_din_2 = {dsp_ma_din24_2, {A_WIDTH-WIDTH{1'b0}}};
-// Shift DSP outputs to match output results    
-    assign  dout1_w = dsp_ma_p_1[M_WIDTH -: WIDTH]; // adding one it for adder (two MPY outputs are added)
-    assign  dout2_w = dsp_ma_p_2[M_WIDTH -: WIDTH]; // adding one it for adder (two MPY outputs are added)
+//    assign dsp_ma_ain_1 = {dsp_ma_ain24_1, {A_WIDTH-WIDTH{1'b0}}};   
+//    assign dsp_ma_din_1 = {dsp_ma_din24_1, {A_WIDTH-WIDTH{1'b0}}};   
+//    assign dsp_ma_ain_2 = {dsp_ma_ain24_2, {A_WIDTH-WIDTH{1'b0}}};   
+//    assign dsp_ma_din_2 = {dsp_ma_din24_2, {A_WIDTH-WIDTH{1'b0}}};
+// Extend sign  for A and D of the multiplier inputs (24bits->25 bits)
+    assign dsp_ma_ain_1 = {{A_WIDTH-WIDTH{dsp_ma_ain24_1[WIDTH-1]}},dsp_ma_ain24_1};   
+    assign dsp_ma_din_1 = {{A_WIDTH-WIDTH{dsp_ma_din24_1[WIDTH-1]}},dsp_ma_din24_1};   
+    assign dsp_ma_ain_2 = {{A_WIDTH-WIDTH{dsp_ma_ain24_2[WIDTH-1]}},dsp_ma_ain24_2};   
+    assign dsp_ma_din_2 = {{A_WIDTH-WIDTH{dsp_ma_din24_2[WIDTH-1]}},dsp_ma_din24_2};
+
+// Shift DSP outputs to match output results
+// Leave unshifted?
+    
+//    assign  dout1_w = dsp_ma_p_1[M_WIDTH -: WIDTH]; // adding one bit for adder (two MPY outputs are added)
+//    assign  dout2_w = dsp_ma_p_2[M_WIDTH -: WIDTH]; // adding one bit for adder (two MPY outputs are added)
+    assign  dout1_w = dsp_ma_p_1[COSINE_SHIFT +: WIDTH]; // adding one bit for adder (two MPY outputs are added)
+    assign  dout2_w = dsp_ma_p_2[COSINE_SHIFT +: WIDTH]; // adding one bit for adder (two MPY outputs are added)
+    
+    
    assign dout = dout_r;

    always @ (posedge clk) begin
-        phase <= {phase[6:0], en & (start |phase[7])};
-        if      (!rst || start)          phase_cnt <= 0;
-        else if (en || (phase_cnt != 7)) phase_cnt <= phase_cnt + 1;
+        if      (rst)      per_type <= 0;
+        else if (start)    per_type <= 3'h1;
+        else if (phase[7]) begin
+            if (!per_type[2] && !en)  per_type <= 3'h6;
+            else if ((per_type != 0) && (per_type != 3)) per_type <= per_type + 1;  
+        end
+        phase <= {phase[6:0], start | (phase[7] & (|per_type) )};
+        
+        if (rst || start || phase[7]) phase_cnt <= 0;
+        else if (|phase[6:0])         phase_cnt <= phase_cnt + 1;
+        
        // Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand
        case (phase_cnt)
-            3'h0: dsp_ma_bin <= COS_1_16;
+            3'h0: dsp_ma_bin <= COS_6_16;
            3'h1: dsp_ma_bin <= COS_7_16;
-            3'h2: dsp_ma_bin <= COS_2_16;
+            3'h2: dsp_ma_bin <= COS_1_16;
            3'h3: dsp_ma_bin <= COS_2_16;
-            3'h4: dsp_ma_bin <= COS_3_16;
-            3'h5: dsp_ma_bin <= COS_5_16;
+            3'h4: dsp_ma_bin <= COS_5_16;
+            3'h5: dsp_ma_bin <= COS_3_16;
            3'h6: dsp_ma_bin <= COS_4_16;
            3'h7: dsp_ma_bin <= COS_6_16;
        endcase
        dout_r <= phase_cnt[0] ? dout1_w : dout2_w;
+
+        if (rst) pre2_start_out <= 0;
+        else     pre2_start_out <= (per_type == 2) && phase[3];
+        
+        if (rst || !(en || (|phase))) en_out <= 0;
+        else if (phase[3]) begin
+            if      (per_type == 2)   en_out <= 1;
+            else if (per_type[2])     en_out <= 0;
+        end         
    end

    dsp_addsub_simd #(
@@ -281,7 +325,7 @@ module  dct1d_chen#(
        .cep      (simd_cep23),        // input
        .pout     ({simd_p3,simd_p2})  // output[47:0] 
    );
-
+/*
    dsp_addsub_reg2_simd #(
        .NUM_DATA(2),
        .WIDTH(24)
@@ -297,7 +341,21 @@ module  dct1d_chen#(
        .cep      (simd_cep45),        // input
        .pout     ({simd_p5,simd_p4})  // output[47:0] 
    );
-
+*/
+    dsp_addsub_simd #(
+        .NUM_DATA (2),
+        .WIDTH    (WIDTH)
+    ) dsp_addsub_simd3_i (
+        .clk      (clk),               // input
+        .rst      (rst),               // input
+        .ain      ({simd_a5,simd_a4}), // input[47:0] 
+        .bin      ({simd_b5,simd_b4}), // input[47:0] 
+        .cea      (simd_cea45),        // input
+        .ceb      (simd_ceb45),        // input
+        .subtract (simd_sub45),        // input
+        .cep      (simd_cep45),        // input
+        .pout     ({simd_p5,simd_p4})  // output[47:0] 
+    );
   
    dsp_ma_preadd #(
        .B_WIDTH(18),
@@ -319,7 +377,7 @@ module  dct1d_chen#(
        .sela  (dsp_ma_sela_1),  // input
        .en_a  (dsp_ma_en_a_1),    // input
        .en_d  (dsp_ma_en_d_1), // input
-        .sub_d (dsp_ma_sub_d_1), // input
+        .sub_a (dsp_ma_sub_a_1), // input
        .neg_m (dsp_ma_neg_m_1), // input
        .accum (dsp_ma_accum_1), // input
        .pout  (dsp_ma_p_1)      // output[47:0] signed 
@@ -348,7 +406,7 @@ module  dct1d_chen#(
        .accum (dsp_ma_accum_2), // input
        .pout  (dsp_ma_p_2)      // output[47:0] signed 
    );
-
+/*
    dly01_16 dly01_16_i (
        .clk   (clk),           // input
        .rst   (rst),           // input
@@ -356,7 +414,7 @@ module  dct1d_chen#(
        .din   (phase[7]),      // input
        .dout  (pre2_start_out) // output
    );
-
+*/

 endmodule

--- a/dsp/dct1d_chen_reorder_in.v
+++ b/dsp/dct1d_chen_reorder_in.v
@@ -48,22 +48,34 @@ module  dct1d_chen_reorder_in#(
    input                  start, // with first pixel 
    output [2*WIDTH -1:0]  dout_10_32_76_54, // Concatenated/reordered output data {x[1],x[0]}/{x[3],x[2]}/ {x[7],x[6]}/{x[5],x[4]}
    output reg             start_out,
-    output reg             en_out // to be sampled when start_out is expected
+    output                 en_out // to be sampled when start_out is expected
 );
    reg                    last_r;
    reg              [2:0] cntr_in;
    reg              [1:0] raddr;
    wire                   restart = !rst && en && (start || last_r);
-    wire             [1:0] we = ((|cntr_in) || en)? {~cntr_in[0]^cntr_in[2],cntr_in[0]^cntr_in[2]}:2'b0;
+//    wire             [1:0] we = ((|cntr_in) || en)? {~cntr_in[0]^cntr_in[2],cntr_in[0]^cntr_in[2]}:2'b0;
+    wire             [1:0] we = ((|cntr_in) || en)? {cntr_in[0]^cntr_in[2], ~cntr_in[0]^cntr_in[2]}:2'b0;
    wire             [1:0] waddr = {cntr_in[2],cntr_in[2]^cntr_in[1]};
    reg        [WIDTH-1:0] bufl_ram[0:3];
    reg        [WIDTH-1:0] bufh_ram[0:3];
    reg     [2*WIDTH -1:0] dout_10_32_76_54_r;
+    reg                    first_period;
+    reg                    en_out_r;
+    reg                    last_out;
+    reg                    re_r;
    assign dout_10_32_76_54 = dout_10_32_76_54_r;
+    assign en_out =           en_out_r;
    
    always @(posedge clk) begin
        if (rst) last_r <= 0;
        else     last_r <= &cntr_in;
+
+        last_out <= raddr == 2;
+        
+        if      (rst)          re_r <= 0;
+        else if (cntr_in == 5) re_r <= 1;
+        else if (last_out)     re_r <= 0;
        
        if      (rst)                   cntr_in <= 0;
        else if (restart || (|cntr_in)) cntr_in <= cntr_in + 1;
@@ -75,10 +87,18 @@ module  dct1d_chen_reorder_in#(
        else if (cntr_in == 5) raddr <= 0;
        else if (!(&raddr))    raddr <= raddr + 1;
        
-        dout_10_32_76_54_r <= {bufh_ram[raddr],bufl_ram[raddr]};
-        start_out <= (cntr_in == 5);
+        if      (rst)          first_period <= 0;
+        else if (start && en)  first_period <= 1;
+        else if (last_r)       first_period <= 0;
+        
+        if (re_r) dout_10_32_76_54_r <= {bufh_ram[raddr],bufl_ram[raddr]};
        
-        en_out <= en || (|cntr_in) || last_r;
+        start_out <= first_period && (cntr_in == 5);
+        
+        if      (rst)                 en_out_r <= 0;
+        else if (cntr_in == 5)        en_out_r <= 1;
+        else if ((raddr == 2) && !en) en_out_r <= 0;
+
    end
 endmodule

--- a/dsp/dct1d_chen_reorder_out.v
+++ b/dsp/dct1d_chen_reorder_out.v
@@ -43,33 +43,45 @@ module  dct1d_chen_reorder_out#(
 )(
    input                  clk,
    input                  rst,
+    input                  en,        // sampled at timeslot of pre2_start
    input  [WIDTH -1:0]    din,       // pre2_start-X-F4-X-F2-X-F6-F5-F0-F3-X-F1-X-F7
    input                  pre2_start,     // Two cycles ahead of F4 
    output   [WIDTH -1:0]  dout,      // data in natural order: F0-F1-F2-F3-F4-F5-F6-F7
-    output                 start_out, // 1 ahead of F0
-    output reg             en_out // to be sampled when start_out is expected
+    output                 start_out, // 1 ahead of the first F0
+    output reg             dv,        // output data valid
+    output                 en_out     // to be sampled when start_out is expected
 );
    reg [WIDTH -1:0] reord_buf_ram[0:15];
    reg [WIDTH -1:0] dout_r;
    reg  [3:0] cntr_in;
-    wire       start_8;
-    wire       start_11;
-    reg        start_12;
-    wire       stop_in;
+    reg        pre_we_r;
    reg        we_r;
    reg  [3:0] ina_rom;
    wire [3:0] waddr = {ina_rom[3] ^ cntr_in[3], ina_rom[2:0]};   
    reg  [3:0] raddr;
-    assign dout = dout_r; 
-    assign start_out = start_12;
+    reg  [2:0] per_type; // idle/last:0, first cycle - 1, 2-nd - 2, other - 3,... ~en->6 ->7 -> 0  (to generate pre2_start_out)
+    reg        start_out_r;
+    reg        en_out_r;
+    assign dout = dout_r;
+    assign start_out = start_out_r; 
+    assign en_out = en_out_r;
+    
    always @(posedge clk) begin
-        if      (rst)        we_r <= 0;
-        else if (pre2_start) we_r <= 1;
-        else if (stop_in)    we_r <= 0;
+        if      (rst)           per_type <= 0;
+        else if (pre2_start)    per_type <= 3'h1;
+        else if (&cntr_in[2:0]) begin
+            if      (!per_type[2] && !en)                per_type <= 3'h6;
+            else if ((per_type != 0) && (per_type != 3)) per_type <= per_type + 1;  
+        end
+    
+        if      (rst)                                              pre_we_r <= 0;
+        else if (pre2_start)                                       pre_we_r <= 1;
+        else if ((per_type == 0) || ((cntr_in==3) && per_type[2])) pre_we_r <= 0;
+        we_r <= pre_we_r;
        
        if      (rst)        cntr_in <= 0;
        else if (pre2_start) cntr_in <= {~cntr_in[3],3'b0};
-        else if (we_r)       cntr_in <= cntr_in + 1;
+        else if (pre_we_r)       cntr_in <= cntr_in + 1;
        case (cntr_in[2:0])
            3'h0: ina_rom <= {1'b0,3'h4};
            3'h1: ina_rom <= {1'b1,3'h1};
@@ -78,46 +90,24 @@ module  dct1d_chen_reorder_out#(
            3'h4: ina_rom <= {1'b0,3'h6};
            3'h5: ina_rom <= {1'b0,3'h5};
            3'h6: ina_rom <= {1'b0,3'h0};
-            3'h7: ina_rom <= {1'b0,3'h3};
+            3'h7: ina_rom <= {1'b1,3'h3};
        endcase
        
        if (we_r) reord_buf_ram[waddr] <= din;

-        if      (start_11)                  raddr <= {~cntr_in[3], 3'b0};
-        else if ((raddr[2:0] != 0) || we_r) raddr <= raddr + 1;
+        if      ((per_type == 2) && (cntr_in == 1))   raddr <= {~cntr_in[3], 3'b0};
+        else if ((raddr[2:0] != 0) || (per_type !=0)) raddr <= raddr + 1;
        
        dout_r <=  reord_buf_ram[raddr];
+        start_out_r <=  (per_type == 2) && (cntr_in == 1);
        
-        start_12 <= start_11;
-        
-        en_out <= start_12 || (raddr[2:0] != 0); 
-        
-    end
-
-    dly01_16 start_8__i (
-        .clk   (clk), // input
-        .rst   (rst), // input
-        .dly   (4'h7), // input[3:0] 
-        .din   (pre2_start), // input
-        .dout  (start_8) // output
-    );
-
-    dly01_16 start_11__i (
-        .clk   (clk), // input
-        .rst   (rst), // input
-        .dly   (4'h1), // input[3:0] 
-        .din   (start_8), // input
-        .dout  (start_11) // output
-    );
-
-    dly01_16 dly01_16_2_i (
-        .clk   (clk), // input
-        .rst   (rst), // input
-        .dly   (4'h4), // input[3:0] 
-        .din   (start_8 && !pre2_start), // input
-        .dout  (stop_in)            // output
-    );
+        if (rst ||(per_type == 0) ) en_out_r <= 0;
+        else if (cntr_in == 1)      en_out_r <= (per_type == 2) || !per_type[2]; 

+        if      (rst)                            dv <= 0;
+        else if (start_out_r)                    dv <= 1;
+        else if ((raddr[2:0] == 0) && !en_out_r) dv <= 0;
+    end

 endmodule

--- a/dsp/dct2d8x8_chen.v
+++ b/dsp/dct2d8x8_chen.v
+/*******************************************************************************
+ * <b>Module:</b>dct2d8x8_chen
+ * @file dct2d8x8_chen.v
+ * @date:2016-06-10  
+ * @author: Andrey Filippov
+ *     
+ * @brief: 2-d DCT implementation of Chen algorithm
+ *
+ * @copyright Copyright (c) 2016 Elphel, Inc.
+ *
+ * <b>License:</b>
+ *
+ *dct2d8x8_chen.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  dct2d8x8_chen.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  dct2d8x8_chen#(
+    parameter INPUT_WIDTH =     10,
+    parameter OUTPUT_WIDTH =    13,
+    parameter STAGE1_SAFE_BITS = 3, // leave this number of extra bits on DCT1D input to prevent output saturation
+    parameter STAGE2_SAFE_BITS = 3, // leave this number of extra bits on DCT1D input to prevent output saturation
+    parameter TRANSPOSE_WIDTH = 16, // transpose memory width
+    parameter TRIM_STAGE_1 =     0, // Trim these MSBs from the stage1 results
+    parameter TRIM_STAGE_2 =     2, // Trim these MSBs from the stage2 results TODO: put real value
+    parameter DSP_WIDTH =       24,
+    parameter DSP_OUT_WIDTH =   24,
+    parameter DSP_B_WIDTH =     18,
+    parameter DSP_A_WIDTH =     25,
+    parameter DSP_P_WIDTH =     48,
+    parameter DSP_M_WIDTH =     43  // actual multiplier width (== (A_WIDTH +B_WIDTH)
+    ) (
+    input                            clk,           /// system clock, posedge
+    input                            rst,           // sync reset
+//    input                            en,            //! if zero will reset transpose memory page njumbers
+    input                            start,         //@ single-cycle start pulse that goes with the first pixel data. Other 63 should follow
+    input signed   [INPUT_WIDTH-1:0] xin,           //! [9:0] - input data
+    output reg                       last_in,       //! output high during input of the last of 64 pixels in a 8x8 block
+    output                           pre_first_out, //! 1 cycle ahead of the first output in a 64 block
+    output                           dv,            //! data output valid. WAS: Will go high on the 94-th cycle after the start
+    output signed [OUTPUT_WIDTH-1:0] d_out);        //! [12:0]output data
+
+    localparam REPLICATE_IN_STAGE1 = STAGE1_SAFE_BITS;
+    localparam PAD_IN_STAGE1 =       DSP_WIDTH - INPUT_WIDTH - STAGE1_SAFE_BITS ;
+
+    localparam REPLICATE_IN_STAGE2 = STAGE2_SAFE_BITS;
+    localparam PAD_IN_STAGE2 =       DSP_WIDTH - TRANSPOSE_WIDTH - STAGE2_SAFE_BITS ;
+    
+    
+    reg signed      [INPUT_WIDTH-1:0] xin_r;
+    reg                               start_in_r;
+    reg                         [5:0] cntr_in = ~0;
+    reg                               en_in_r;
+    
+    wire signed     [INPUT_WIDTH-1:0] dct1in_h;                  
+    wire signed     [INPUT_WIDTH-1:0] dct1in_l;
+    wire                              dct1_start;                  
+    wire                              dct1_en;
+    
+    wire signed       [DSP_WIDTH-1:0] dct1in_pad_h;                  
+    wire signed       [DSP_WIDTH-1:0] dct1in_pad_l;
+    wire signed   [DSP_OUT_WIDTH-1:0] dct1_out;
+    wire                              stage1_pre2_start_out; 
+//    wire                              stage1_pre2_en_out; 
+    
+    wire signed [TRANSPOSE_WIDTH-1:0] transpose_din;
+    wire signed [TRANSPOSE_WIDTH-1:0] transpose_douth;
+    wire signed [TRANSPOSE_WIDTH-1:0] transpose_doutl;
+    wire                              transpose_start_out; 
+    wire                              transpose_en_out; 
+    
+    wire signed       [DSP_WIDTH-1:0] dct2in_pad_h;                  
+    wire signed       [DSP_WIDTH-1:0] dct2in_pad_l;
+    wire signed   [DSP_OUT_WIDTH-1:0] dct2_out;
+    wire                              stage2_pre2_start_out; 
+    wire                              stage2_pre2_en_out; 
+    
+    wire signed    [OUTPUT_WIDTH-1:0] dct2_trimmed;
+                      
+    assign dct1in_pad_h = {{REPLICATE_IN_STAGE1{dct1in_h[INPUT_WIDTH-1]}}, dct1in_h, {PAD_IN_STAGE1{1'b0}}};                  
+    assign dct1in_pad_l = {{REPLICATE_IN_STAGE1{dct1in_l[INPUT_WIDTH-1]}}, dct1in_l, {PAD_IN_STAGE1{1'b0}}};                  
+    assign transpose_din = dct1_out[DSP_OUT_WIDTH-1-TRIM_STAGE_1 -:TRANSPOSE_WIDTH];
+    
+    assign dct2in_pad_h = {{REPLICATE_IN_STAGE2{transpose_douth[TRANSPOSE_WIDTH-1]}}, transpose_douth, {PAD_IN_STAGE2{1'b0}}};                  
+    assign dct2in_pad_l = {{REPLICATE_IN_STAGE2{transpose_doutl[TRANSPOSE_WIDTH-1]}}, transpose_doutl, {PAD_IN_STAGE2{1'b0}}};                  
+
+    assign dct2_trimmed = dct2_out[DSP_OUT_WIDTH-1-TRIM_STAGE_2 -:OUTPUT_WIDTH];
+
+    always @(posedge clk) begin
+        start_in_r <= start;
+        
+        if      (rst)         cntr_in <= ~0;
+        else if (start)       cntr_in <= 0;
+        else if (!(&cntr_in)) cntr_in <= cntr_in + 1;
+        
+        last_in <= (cntr_in == 61);
+        
+        if      (rst)      en_in_r <= 0;
+        else if (start)    en_in_r <= 1;
+        else if (&cntr_in) en_in_r <= 0;
+        
+        if (start || en_in_r) xin_r <=xin; 
+    
+    end
+
+    dct1d_chen_reorder_in #(
+        .WIDTH(INPUT_WIDTH)
+    ) dct1d_chen_reorder_in_i (
+        .clk              (clk),                 // input
+        .rst              (rst),                 // input
+        .en               (en_in_r),             // input
+        .din              (xin_r),               // input[23:0] 
+        .start            (start_in_r),          // input
+        .dout_10_32_76_54 ({dct1in_h,dct1in_l}), // output[47:0] 
+        .start_out        (dct1_start),          // output reg 
+        .en_out           (dct1_en)              // output
+    );
+    wire dbg_stage1_pre2_en_out;
+    dct1d_chen #(
+        .WIDTH           (DSP_WIDTH),
+        .OUT_WIDTH       (DSP_OUT_WIDTH),
+        .B_WIDTH         (DSP_B_WIDTH),
+        .A_WIDTH         (DSP_A_WIDTH),
+        .P_WIDTH         (DSP_P_WIDTH),
+        .M_WIDTH         (DSP_M_WIDTH)
+    ) dct1d_chen_stage1_i (
+        .clk             (clk),                         // input
+        .rst             (rst),                         // input
+        .en              (dct1_en),                     // input
+        .d10_32_76_54    ({dct1in_pad_h,dct1in_pad_l}), // input[47:0] 
+        .start           (dct1_start),                  // input
+        .dout            (dct1_out),                    // output[23:0] 
+        .pre2_start_out  (stage1_pre2_start_out),       // output reg 
+        .en_out          (dbg_stage1_pre2_en_out)       // output reg 
+    );
+
+    dct_chen_transpose #(
+        .WIDTH(TRANSPOSE_WIDTH)
+    ) dct_chen_transpose_i (
+        .clk              (clk),                               // input
+        .rst              (rst),                               // input
+        .din              (transpose_din),                     // input[23:0] 
+        .pre2_start       (stage1_pre2_start_out),             // input
+        .dout_10_32_76_54 ({transpose_douth,transpose_doutl}), // output[47:0] 
+        .start_out        (transpose_start_out),               // output reg 
+        .en_out           (transpose_en_out)                   // output reg 
+    );
+
+    dct1d_chen #(
+        .WIDTH(DSP_WIDTH),
+        .OUT_WIDTH(DSP_OUT_WIDTH),
+        .B_WIDTH(DSP_B_WIDTH),
+        .A_WIDTH(DSP_A_WIDTH),
+        .P_WIDTH(DSP_P_WIDTH),
+        .M_WIDTH(DSP_M_WIDTH)
+    ) dct1d_chen_stage2_i (
+        .clk             (clk),                         // input
+        .rst             (rst),                         // input
+        .en              (transpose_en_out),            // input
+        .d10_32_76_54    ({dct2in_pad_h,dct2in_pad_l}), // input[47:0] 
+        .start           (transpose_start_out),         // input
+        .dout            (dct2_out),                    // output[23:0] 
+        .pre2_start_out  (stage2_pre2_start_out),       // output reg 
+        .en_out          (stage2_pre2_en_out)           // output reg 
+    );
+
+    dct1d_chen_reorder_out #(
+        .WIDTH       (OUTPUT_WIDTH)
+    ) dct1d_chen_reorder_out_i (
+        .clk         (clk),                   // input
+        .rst         (rst),                   // input
+        .en          (stage2_pre2_en_out),    // input
+        .din         (dct2_trimmed),          // input[23:0] 
+        .pre2_start  (stage2_pre2_start_out), // input
+        .dout        (d_out),                 // output[23:0] 
+        .start_out   (pre_first_out),         // output reg 
+        .dv          (dv),                    // output reg 
+        .en_out      ()                       // output reg 
+    );
+
+// Just for debugging/comparing with old 1-d DCT:
+wire [DSP_WIDTH-1:0] dbg_d_out;
+wire                 dbg_dv;
+wire                 dbg_en_out;
+wire                 dbg_pre_first_out;
+
+    dct1d_chen_reorder_out #(
+        .WIDTH       (DSP_WIDTH)
+    ) dct1d_chen_reorder_out_dbg_i (
+        .clk         (clk),                    // input
+        .rst         (rst),                    // input
+        .en          (dbg_stage1_pre2_en_out), // input
+        .din         (dct1_out),               // input[23:0] 
+        .pre2_start  (stage1_pre2_start_out),  // input
+        .dout        (dbg_d_out),              // output[23:0] 
+        .start_out   (dbg_pre_first_out),      // output reg 
+        .dv          (dbg_dv),                 // output reg 
+        .en_out      (dbg_en_out)              // output reg 
+    );
+endmodule
+
--- a/dsp/dct_chen_transpose.v
+++ b/dsp/dct_chen_transpose.v
+/*******************************************************************************
+ * <b>Module:</b>dct_chen_transpose
+ * @file dct_chen_transpose.v
+ * @date:2016-06-09  
+ * @author: Andrey Filippov
+ *     
+ * @brief: Reorder+transpose data between two 1-d DCT passes
+ *
+ * @copyright Copyright (c) 2016 Elphel, Inc.
+ *
+ * <b>License:</b>
+ *
+ *dct_chen_transpose.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  dct_chen_transpose.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  dct_chen_transpose#(
+    parameter WIDTH = 24
+ )(
+    input                  clk,
+    input                  rst,
+    input    [WIDTH -1:0]  din,            // pre2_start-X-F4-X-F2-X-F6-F5-F0-F3-X-F1-X-F7
+    input                  pre2_start,     // Two cycles ahead of F4. Next one should start either at exactly 64 cycles, or >=68 cycles from the previous one 
+    output [2*WIDTH -1:0]  dout_10_32_76_54, // Concatenated/reordered output data {x[1],x[0]}/{x[3],x[2]}/ {x[7],x[6]}/{x[5],x[4]}
+    output reg             start_out,
+    output reg             en_out // to be sampled when start_out is expected
+);
+    reg         [6:0] wcntr;    // write counter, used to calculate write address (2 pages of 64 words), that will be valid next cycle
+    wire        [2:0] wrow = wcntr[5:3];     
+    wire        [2:0] wcol = wcntr[2:0];
+    wire              wpage;
+         
+    reg               wcol13;    // columns 1 and 3 (special)
+    wire        [3:0] wrow_mod;  // effective row, including modifier for wpage
+    wire        [1:0] wcol01_mod = wcol[1:0] + wcol[2];   
+    reg         [6:0] waddr;
+    wire              pre2_stop;
+    reg   [WIDTH-1:0] transpose_ram[0:127];
+    reg               pre_we_r;
+    reg               we_r;
+    reg         [5:0] rcntr = 6'h3f;    // read counter
+    reg         [5:0] raddr;    // read counter, addresses dual words
+    reg               re_r;
+    reg               regen_r;
+    reg [2*WIDTH-1:0] ram_reg;
+    reg [2*WIDTH-1:0] ram_reg2;
+    wire              pre_rstart_w = wcntr[5:0] == 61;
+    reg         [1:0] rstop_r;
+    
+    assign wpage = wcntr[6] ^ wrow_mod[3]; // previous page for row 0, col 1 & 3
+    assign wrow_mod = {1'b0, wrow} - wcol13; 
+    assign dout_10_32_76_54 = ram_reg2;
+    // TODO: prevent writing to previous page after pause!
+    always @(posedge clk) begin
+        wcol13 <=     ~wcol[0] & ~wcol[2];
+        waddr[0] <=    wrow_mod[0] ^ wrow_mod[2];  
+        waddr[1] <=    wcol[1];
+        waddr[2] <=   ~wcol01_mod[0] ^ wcol01_mod[1];
+        waddr[3] <=   ~wcol01_mod[1];
+        waddr[4] <=    wrow_mod[0] ^ wrow_mod[2];
+        waddr[5] <=    wrow_mod[2];
+        waddr[6] <=    wpage;
+
+        if      (rst)        pre_we_r <= 0;
+        else if (pre2_start) pre_we_r <= 1;
+        else if (pre2_stop)  pre_we_r <= 0;
+        
+        if      (rst)        wcntr <= 0;
+        else if (pre_we_r)   wcntr <= wcntr + 1;        // including page, should be before 'if (pre2_start)'
+        else if (pre2_start) wcntr <= {wcntr[6], 6'b0}; // if happens during pre_we_r - will be ignore, otherwise (after pause) will zero in-page adderss
+        
+        we_r <= pre_we_r;
+        
+        if (we_r) transpose_ram[waddr] <= din;
+        
+        if      (rst)          rcntr <= ~0;
+        else if (pre_rstart_w) rcntr <= 0;
+        else if (rcntr != ~0)  rcntr <=  rcntr + 1;
+        
+        re_r <=    ~rcntr[2];
+        regen_r <= re_r;
+        
+        if (rcntr == 0) raddr[5] <= wcntr[6]; // page
+        raddr[4:0] <= {rcntr[1:0],rcntr[5:3]};
+        
+        if (re_r)    ram_reg <= {transpose_ram[2*raddr+1],transpose_ram[2*raddr]}; // See if it will correctly infer   
+        if (regen_r) ram_reg2 <= ram_reg;
+        
+        if (rst || pre_rstart_w) rstop_r <= 0;
+        else if (&rcntr)         rstop_r <= {rstop_r[0], 1'b1};
+        
+        start_out <= (rcntr == 1);
+        
+        if      (rst)        en_out <= 0;
+        else if (rcntr == 1) en_out <= 1;
+        else if (rstop_r[1]) en_out <= 0;
+    end
+    
+    dly01_16 dly01_16_stop_i (
+        .clk  (clk), // input
+        .rst  (rst),                        // input
+        .dly  (4'h3),                       // input[3:0] 
+        .din  (&wcntr[5:0] && !pre2_start), // input
+        .dout (pre2_stop)                   // output
+    );
+    
+    
+/*
+min latency == 60, // adding 1 for read after write in RAM
+max latency = 83 (when using a 2-page buffer)
+wseq=(0x08,  0x62,  0x04,  0x6e,  0x0c,  0x0a,  0x00,  0x06,
+ 0x09,  0x02,  0x05,  0x0e,  0x0d,  0x0b,  0x01,  0x07,
+ 0x18,  0x03,  0x14,  0x0f,  0x1c,  0x1a,  0x10,  0x16,
+ 0x19,  0x12,  0x15,  0x1e,  0x1d,  0x1b,  0x11,  0x17,
+ 0x39,  0x13,  0x35,  0x1f,  0x3d,  0x3b,  0x31,  0x37,
+ 0x38,  0x33,  0x34,  0x3f,  0x3c,  0x3a,  0x30,  0x36,
+ 0x29,  0x32,  0x25,  0x3e,  0x2d,  0x2b,  0x21,  0x27,
+ 0x28,  0x23,  0x24,  0x2f,  0x2c,  0x2a,  0x20,  0x26)
+rseq = (0x00,0x10,0x20,0x30,-1,-1,-1,-1,
+        0x02,0x12,0x22,0x32,-1,-1,-1,-1,
+        0x04,0x14,0x24,0x34,-1,-1,-1,-1,
+        0x06,0x16,0x26,0x36,-1,-1,-1,-1,
+        0x08,0x18,0x28,0x38,-1,-1,-1,-1,
+        0x0a,0x1a,0x2a,0x3a,-1,-1,-1,-1,
+        0x0c,0x1c,0x2c,0x3c,-1,-1,-1,-1,
+        0x0e,0x1e,0x2e,0x3e,-1,-1,-1,-1)
+
+*/
+endmodule
+
--- a/dsp/dsp_addsub_reg2_simd.v
+++ b/dsp/dsp_addsub_reg2_simd.v
@@ -125,8 +125,8 @@ module  dsp_addsub_reg2_simd#(
        .CEB1           (cea1),       // input
        .CEB2           (cea2),       // input
        .CEC            (ceb),        // input
-        .CECARRYIN      (1'b0),       // input
-        .CECTRL         (1'b0),       // input
+        .CECARRYIN      (1'b1),       // input
+        .CECTRL         (1'b1),       // input
        .CED            (1'b0),       // input
        .CEINMODE       (1'b1),       // input
        .CEM            (1'b1),       // input

--- a/dsp/dsp_addsub_simd.v
+++ b/dsp/dsp_addsub_simd.v
@@ -58,13 +58,15 @@ module  dsp_addsub_simd#(
                          1'b0,  // seld,
                          1'b0,  // seld, // ~en_a,
                          1'b1}; // ~sela};
-    wire [3:0] alumode = {2'b0,        // Z + X + Y + CIN  / -Z +( X + Y + CIN) -1
-                          1'b0,     
+// No CIN in the middle of SIMD words!                          
+//    wire [3:0] alumode = {2'b0,        // Z + X + Y + CIN  / -Z +( X + Y + CIN) -1
+    wire [3:0] alumode = {2'b0,        // Z + X + Y + CIN  / Z -( X + Y + CIN)
+                          subtract, // 1'b0,     
                          subtract};
    wire [6:0] opmode =  {3'b011, // Z = C-input
                          2'b00,  // Y = 0
                          2'b11}; // X = A:B
-    wire cryin = subtract;                      
+//    wire cryin = subtract;                      
                          
    DSP48E1 #(
        .ACASCREG            (1),
@@ -109,24 +111,24 @@ module  dsp_addsub_simd#(
        .PATTERNDETECT  (),           // output
        .PCOUT          (),           // output[47:0] 
        .UNDERFLOW      (),           // output
-        .A              (ain[47:18]), // input[29:0] 
+        .A              (bin[47:18]), // input[29:0] 
        .ACIN           (30'b0),      // input[29:0] 
        .ALUMODE        (alumode),    // input[3:0] 
-        .B              (ain[17:0]),  // input[17:0] 
+        .B              (bin[17:0]),  // input[17:0] 
        .BCIN           (18'b0),      // input[17:0] 
-        .C              (bin),        // input[47:0] 
+        .C              (ain),        // input[47:0] 
        .CARRYCASCIN    (1'b0),       // input
-        .CARRYIN        (cryin),      // input
+        .CARRYIN        (1'b0),       // cryin),      // input
        .CARRYINSEL     (3'h0),       // input[2:0] // later modify? 
-        .CEA1           (cea),        // input
-        .CEA2           (1'b0),       // input
+        .CEA1           (1'b0),       // input
+        .CEA2           (ceb),        // input
        .CEAD           (1'b0),       // input
        .CEALUMODE      (1'b1),       // input
-        .CEB1           (cea),        // input
-        .CEB2           (1'b0),       // input
-        .CEC            (ceb),        // input
-        .CECARRYIN      (1'b0),       // input
-        .CECTRL         (1'b0),       // input
+        .CEB1           (1'b0),       // input
+        .CEB2           (ceb),        // input
+        .CEC            (cea),        // input
+        .CECARRYIN      (1'b1),       // input
+        .CECTRL         (1'b1),       // input
        .CED            (1'b0),       // input
        .CEINMODE       (1'b1),       // input
        .CEM            (1'b1),       // input

--- a/dsp/dsp_ma.v
+++ b/dsp/dsp_ma.v
@@ -78,11 +78,11 @@ module  dsp_ma #(
        .ACASCREG            (1),
        .ADREG               (0), // (1),
        .ALUMODEREG          (1),
-        .AREG                (2), // (1)
+        .AREG                (1), // (2), // (1)  - means number in series, so "2" always reads the second
        .AUTORESET_PATDET    ("NO_RESET"),
        .A_INPUT             ("DIRECT"),
        .BCASCREG            (1),
-        .BREG                (2), // (1)
+        .BREG                (1), // (2), // (1)  - means number in series, so "2" always reads the second
        .B_INPUT             ("DIRECT"),
        .CARRYINREG          (1),
        .CARRYINSELREG       (1),
@@ -134,7 +134,7 @@ module  dsp_ma #(
        .CEB2           (ceb2),       // input
        .CEC            (1'b0),       // input
        .CECARRYIN      (1'b0),       // input
-        .CECTRL         (1'b0),       // input
+        .CECTRL         (1'b1),       // input
        .CED            (ced),        // input
        .CEINMODE       (1'b1),       // input
        .CEM            (1'b1),       // input

--- a/dsp/dsp_ma_preadd.v
+++ b/dsp/dsp_ma_preadd.v
@@ -58,14 +58,14 @@ module  dsp_ma_preadd #(
    input                       sela,     // 0 - select a1, 1 - select a2
    input                       en_a,     // 1 - enable a input (0 - zero) ~inmode[1]
    input                       en_d,     // 1 - enable d input (0 - zero) ~inmode[2]
-    input                       sub_d,    // 0 - pre-add (A+D), 1 - pre-subtract (A-D)
+    input                       sub_a,    // 0 - pre-add (D+A), 1 - pre-subtract (D-A)
    input                       neg_m,    // 1 - negate multiplier result
    input                       accum,    // 0 - use multiplier result, 1 add to accumulator
    output signed [P_WIDTH-1:0] pout
 );
 `ifdef INSTANTIATE_DSP48E1
    wire [4:0] inmode = {~selb,
-                          sub_d,
+                          sub_a,
                          en_d,
                         ~en_a,
                         ~sela};
@@ -82,11 +82,11 @@ module  dsp_ma_preadd #(
        .ACASCREG            (1),
        .ADREG               (1),
        .ALUMODEREG          (1),
-        .AREG                (2), // (1)
+        .AREG                (1), // 2), // (1) - means number in series, so "2" always reads the second
        .AUTORESET_PATDET    ("NO_RESET"),
        .A_INPUT             ("DIRECT"),
        .BCASCREG            (1),
-        .BREG                (2), // (1)
+        .BREG                (1), // (2), // (1) - means number in series, so "2" always reads the second
        .B_INPUT             ("DIRECT"),
        .CARRYINREG          (1),
        .CARRYINSELREG       (1),
@@ -138,7 +138,7 @@ module  dsp_ma_preadd #(
        .CEB2           (ceb2),       // input
        .CEC            (1'b0),       // input
        .CECARRYIN      (1'b0),       // input
-        .CECTRL         (1'b0),       // input
+        .CECTRL         (1'b1),       // input
        .CED            (ced),        // input
        .CEINMODE       (1'b1),       // input
        .CEM            (1'b1),       // input
@@ -179,7 +179,7 @@ module  dsp_ma_preadd #(
    reg                       sela_r;
    reg                       en_a_r;
    reg                       en_d_r;
-    reg                       sub_d_r;
+    reg                       sub_a_r;
    reg                       neg_m_r;
    reg                       accum_r;
    wire signed [P_WIDTH-1:0] m_reg_pm;            
@@ -189,7 +189,8 @@ module  dsp_ma_preadd #(
    assign pout = p_reg;
    assign b_wire = selb_r ? b2_reg : b1_reg;
    assign a_wire = en_a_r ? (sela_r ? a2_reg : a1_reg) : {A_WIDTH{1'b0}};
-    assign d_wire = en_d_r ? (sub_d_r ? -d_reg : d_reg) : {A_WIDTH{1'b0}};
+//    assign d_wire = en_d_r ? (sub_a_r ? -d_reg : d_reg) : {A_WIDTH{1'b0}};
+    assign d_wire = en_d_r ? d_reg : {A_WIDTH{1'b0}};
    assign m_wire = ad_reg * b_wire;
    
    assign m_reg_pm =   neg_m_r ? - m_reg : m_reg;  
@@ -212,7 +213,7 @@ module  dsp_ma_preadd #(
        else if (ced)  d_reg <= din;
        
        if      (rst)   ad_reg <= 0;
-        else if (cead)  ad_reg <= a_wire + d_wire;
+        else if (cead)  ad_reg <= sub_a_r? (d_wire - a_wire): (d_wire + a_wire);
        
        neg_m_r <= neg_m;
        accum_r <= accum;
@@ -221,7 +222,7 @@ module  dsp_ma_preadd #(
        sela_r <=  sela;
        en_a_r <=  en_a;
        en_d_r <=  en_d;
-        sub_d_r <= sub_d;
+        sub_a_r <= sub_a;
        
        m_reg <= {{P_WIDTH - A_WIDTH - B_WIDTH{1'b0}}, m_wire};
        

--- a/x393_testbench03.tf
+++ b/x393_testbench03.tf
@@ -1404,6 +1404,11 @@ end
 // protect from never end
  initial begin
  // after 1 frame compressed on all channels
+  // Debugging DCT Chen
+  
+  #100000;
+  $finish;
+  
 `ifdef HISPI
    #135000;


--- a/x393_testbench04.sav
+++ b/x393_testbench04.sav
 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Sat May 21 05:03:06 2016
+[*] Sun Jun 12 05:41:06 2016
 [*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160513194544675.fst"
-[dumpfile_mtime] "Sat May 14 02:32:17 2016"
-[dumpfile_size] 169964391
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160611211111571.fst"
+[dumpfile_mtime] "Sun Jun 12 03:26:59 2016"
+[dumpfile_size] 85746817
 [savefile] "/home/andrey/git/x393/x393_testbench04.sav"
-[timestart] 0
+[timestart] 90597800
 [size] 1823 1180
 [pos] 0 0
-*-25.461117 43097388 209370000 209396667 209423333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-14.383114 90668200 209370000 209396667 209423333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_testbench03.
 [treeopen] x393_testbench03.read_compressor_frame_irq.
 [treeopen] x393_testbench03.read_contol_register_irq.
@@ -18,7 +18,19 @@
 [treeopen] x393_testbench03.x393_i.
 [treeopen] x393_testbench03.x393_i.cmd_seq_mux_i.
 [treeopen] x393_testbench03.x393_i.cmd_seq_mux_i.status_generate_cmd_seq_mux_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.
 [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_in_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_ma1_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_ma1_i.DSP48E1_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_ma2_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_ma2_i.DSP48E1_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.
 [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].
 [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].
 [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].
@@ -49,10 +61,10 @@
 [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
 [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
 [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sensor_i2c_io_i.
-[sst_width] 287
-[signals_width] 254
+[sst_width] 352
+[signals_width] 267
 [sst_expanded] 1
-[sst_vpaned_height] 578
+[sst_vpaned_height] 420
 @820
 x393_testbench03.TEST_TITLE[639:0]
 @c00200
@@ -1044,16 +1056,6 @@ x393_testbench03.sns1_dn[7:0]
 x393_testbench03.sns1_dp[7:0]
 @200
 -
-@22
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pxd[11:0]
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pxd_out[11:0]
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_parallel12_i.pxd[11:0]
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_parallel12_i.pxd_out[11:0]
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.pxd[11:0]
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.pxd_out[11:0]
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.pxd[11:0]
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.pxd_out[11:0]
-@200
 -
 @22
 x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.dout[15:0]
@@ -1443,6 +1445,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 -sensor_i2c-0
 @800200
 -sensor_memory
+@c00200
 -top
 @800022
 x393_testbench03.x393_i.sens_rpage_set[3:0]
@@ -1453,9 +1456,9 @@ x393_testbench03.x393_i.sens_rpage_set[3:0]
 (3)x393_testbench03.x393_i.sens_rpage_set[3:0]
 @1001200
 -group_end
-@1000200
+@1401200
 -top
-@800200
+@c00200
 -mcntrl393
 @22
 x393_testbench03.x393_i.mcntrl393_i.sens_rpage_set[3:0]
@@ -1476,12 +1479,12 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
 x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
 x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.busy_r
 x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_page_rst_neg
-@29
 x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_page_rst_pos
 @200
 -
 @1000200
 -mcntrl_linear_wr_sensor
+@1401200
 -mcntrl393
 @c00200
 -all_channels
@@ -1527,6 +1530,7 @@ x393_testbench03.x393_i.sensors393_i.buf_dout[255:0]
 -all_channels
 @800200
 -chn0
+@c00200
 -sensor_membuf_0
 @28
 x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.pclk
@@ -1552,9 +1556,781 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf
 x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_dout[63:0]
 @200
 -
-@1000200
+@1401200
 -sensor_membuf_0
+@1000200
 -chn0
 -sensor_memory
+@800200
+-dct_chen
+@28
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xclk
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_en
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_start
+@420
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_nodc[9:0]
+@28
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_pre_first_out
+@22
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_out[12:0]
+@800200
+-xdct
+@420
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.xin[9:0]
+@28
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.start
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_we
+@22
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_wa[6:0]
+@420
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_di[15:0]
+@28
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_page
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.stage1_done
+@22
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_ra[6:0]
+@28
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_re
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_regen
+@420
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_out[15:0]
+@28
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.pre_first_out
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.dv
+@420
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.d_out[12:0]
+@1000200
+-xdct
+@800200
+-dct_chen
+@28
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.clk
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.start
+@22
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.cntr_in[5:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.xin[9:0]
+@28
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.en_in_r
+@22
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.ceinmode_in
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.clk_in
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.co11_lsb
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.co23_lsb
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.co35_lsb
+@22
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.comux[47:0]
+@28
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.cout2
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.cout3
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.cout4
+@22
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.d_dly[24:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.d_in[24:0]
+@28
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+@22
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.inmode_in[4:0]
+@28
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.mult_cout
+@22
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+@28
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.multsignin_in
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.multsignout_o_mux
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.multsignout_o_opmode
+@22
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.opmode_dly[6:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.opmode_in[6:0]
+@28
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.overflow_o
+@22
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.pcin_in[47:0]
+@28
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.pdetb_o_reg1
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.pdetb_o_reg2
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.ping_opmode_drc_check
+@22
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qa_o_mux[29:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qa_o_reg1[29:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qa_o_reg2[29:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qacout_o_mux[29:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qad_o_mux[24:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qad_o_reg1[24:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qalumode_o_mux[3:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qalumode_o_reg1[3:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qb_o_mux[17:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qb_o_reg1[17:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qb_o_reg2[17:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qbcout_o_mux[17:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qc_o_mux[47:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qc_o_reg1[47:0]
+@28
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qcarryin_o_mux0
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+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qcarryin_o_mux_tmp
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qcarryin_o_reg0
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qcarryin_o_reg7
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qcarryinsel_o_mux[2:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qcarryinsel_o_reg1[2:0]
+@22
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qd_o_mux[24:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qd_o_reg1[24:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qinmode_o_mux[4:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qinmode_o_reg[4:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qmult_o_mux[42:0]
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qmult_o_reg[42:0]
+@28
+x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_addsub_simd1_i.DSP48E1_i.qmultsignout_o_reg
+@22
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 [pattern_trace] 1
 [pattern_trace] 0