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Commit 2d03240b authored by Andrey Filippov's avatar Andrey Filippov
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finalizing initial x393 and dependencies

parent cd610a00
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Showing with 420 additions and 57 deletions
address_map.txt
View file @ 2d03240b
......@@ -57,6 +57,11 @@
parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory
parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?)
----
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0
0x1100..11ff - 32-bit per-channel memory control
0x1100..110f - control of memory channels 0,1 - PS-controlled sequences
parameter MCNTRL_PS_ADDR= 'h100,
......@@ -71,13 +76,9 @@
============= Add the following (addresses will vary for individual channels)
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_SCANLINE_ADDR= 'h120,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_CHN2_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
......@@ -88,10 +89,21 @@
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
============= Tiled read access (CHN4)
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
// Status read address
parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
......@@ -100,6 +112,9 @@
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CH4_ADDR= 'h5,
================================ OLD =======================================================
Control addresses (in original ddrc_test01)
......
memctrl/mcntrl393.v
View file @ 2d03240b
......@@ -175,8 +175,11 @@ module mcntrl393 #(
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
// Read back current address (for debugging)?
// parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h5,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
......@@ -184,7 +187,7 @@ module mcntrl393 #(
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_ADDR= 'h120,
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -195,9 +198,9 @@ module mcntrl393 #(
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
......@@ -620,7 +623,7 @@ module mcntrl393 #(
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_ADDR (MCNTRL_TILED_ADDR),
.MCNTRL_TILED_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
......@@ -630,7 +633,7 @@ module mcntrl393 #(
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WH (MCNTRL_TILED_TILE_WH),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_ADDR),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
.MCNTRL_TILED_WRITE_MODE (1'b0)
......@@ -788,7 +791,7 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_WRITE_MODE (1'b0)
) mcntrl_linear_rw_chn2_i (
......@@ -832,7 +835,7 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_WRITE_MODE (1'b1)
) mcntrl_linear_rw_chn3_i (
......
memctrl/mcntrl393_test01.v 0 → 100644
View file @ 2d03240b
/*******************************************************************************
* Module: mcntrl393_test01
* Date:2015-02-06
* Author: andrey
* Description: Temporary module to interface mcntrl393 control signals
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* mcntrl393_test01.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mcntrl393_test01.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module mcntrl393_test01#(
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0,
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
)(
input rst,
input mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
output frame_start_chn2, // input
output next_page_chn2, // input
input page_ready_chn2, // output
input frame_done_chn2, // output
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn2, // output[15:0]
output suspend_chn2, // input
output frame_start_chn3, // input
output next_page_chn3, // input
input page_ready_chn3, // output
input frame_done_chn3, // output
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn3, // output[15:0]
output suspend_chn3, // input
output frame_start_chn4, // input
output next_page_chn4, // input
input page_ready_chn4, // output
input frame_done_chn4, // output
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4, // output[15:0]
output suspend_chn4 // input
);
localparam PAGE_BITS=4; // number of LSB to indicate pages read/written
localparam STATUS_PAYLOAD_BITS=FRAME_HEIGHT_BITS+PAGE_BITS+2;
wire cmd_we;
wire [3:0] cmd_a;
wire [7:0] cmd_data;
wire [STATUS_PAYLOAD_BITS-1:0] status_chn2;
wire [7:0] status_chn2_ad;
wire status_chn2_rq;
wire status_chn2_start; // input
wire [STATUS_PAYLOAD_BITS-1:0] status_chn3;
wire [7:0] status_chn3_ad;
wire status_chn3_rq;
wire status_chn3_start; // input
wire [STATUS_PAYLOAD_BITS-1:0] status_chn4;
wire [7:0] status_chn4_ad;
wire status_chn4_rq;
wire status_chn4_start; // input
reg [PAGE_BITS-1:0] page_chn2;
reg [PAGE_BITS-1:0] page_chn3;
reg [PAGE_BITS-1:0] page_chn4;
reg frame_start_chn2_r;
reg frame_start_chn3_r;
reg frame_start_chn4_r;
reg next_page_chn2_r;
reg next_page_chn3_r;
reg next_page_chn4_r;
reg suspend_chn2_r;
reg suspend_chn3_r;
reg suspend_chn4_r;
wire set_chh2_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN2_MODE); // set mode register for channel 2
wire set_chh2_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN2_STATUS_CNTRL); // control status reporting for channel 2
wire set_chh3_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN3_MODE); // set mode register for channel 3
wire set_chh3_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN3_STATUS_CNTRL); // control status reporting for channel 3
wire set_chh4_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN4_MODE); // set mode register for channel 4
wire set_chh4_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN4_STATUS_CNTRL); // control status reporting for channel 4
wire cmd_frame_start_w=cmd_data[0];
wire cmd_next_page_w= cmd_data[1];
wire cmd_suspend_w= cmd_data[2];
reg frame_busy_chn2;
reg frame_busy_chn3;
reg frame_busy_chn4;
assign frame_start_chn2 = frame_start_chn2_r;
assign frame_start_chn3 = frame_start_chn3_r;
assign frame_start_chn4 = frame_start_chn4_r;
assign next_page_chn2 = next_page_chn2_r;
assign next_page_chn3 = next_page_chn3_r;
assign next_page_chn4 = next_page_chn4_r;
assign suspend_chn2 = suspend_chn2_r;
assign suspend_chn3 = suspend_chn3_r;
assign suspend_chn4 = suspend_chn4_r;
assign status_chn2={page_chn2,line_unfinished_chn2,1'b0, frame_busy_chn2};
assign status_chn3={page_chn3,line_unfinished_chn3,1'b0, frame_busy_chn3};
assign status_chn4={page_chn4,line_unfinished_chn4,1'b0, frame_busy_chn4};
always @ (posedge mclk) begin
frame_start_chn2_r <= set_chh2_mode && cmd_frame_start_w;
frame_start_chn3_r <= set_chh3_mode && cmd_frame_start_w;
frame_start_chn4_r <= set_chh4_mode && cmd_frame_start_w;
next_page_chn2_r <= set_chh2_mode && cmd_next_page_w;
next_page_chn3_r <= set_chh3_mode && cmd_next_page_w;
next_page_chn4_r <= set_chh4_mode && cmd_next_page_w;
end
always @ (posedge rst or posedge mclk) begin
if (rst) page_chn2 <= 0;
else if (frame_start_chn2_r) page_chn2 <= 0;
else if (page_ready_chn2) page_chn2 <= page_chn2 + 1;
if (rst) page_chn3 <= 0;
else if (frame_start_chn3_r) page_chn3 <= 0;
else if (page_ready_chn3) page_chn3 <= page_chn3 + 1;
if (rst) page_chn4 <= 0;
else if (frame_start_chn4_r) page_chn4 <= 0;
else if (page_ready_chn4) page_chn4 <= page_chn2 + 1;
if (rst) suspend_chn2_r <= 0;
else if (set_chh2_mode) suspend_chn2_r <= cmd_suspend_w;
if (rst) suspend_chn3_r <= 0;
else if (set_chh3_mode) suspend_chn3_r <= cmd_suspend_w;
if (rst) suspend_chn4_r <= 0;
else if (set_chh4_mode) suspend_chn4_r <= cmd_suspend_w;
if (rst) frame_busy_chn2 <= 0;
else if ( frame_start_chn2_r && !frame_done_chn2) frame_busy_chn2 <= 1;
else if (!frame_start_chn2_r && frame_done_chn2) frame_busy_chn2 <= 0;
if (rst) frame_busy_chn3 <= 0;
else if ( frame_start_chn3_r && !frame_done_chn3) frame_busy_chn3 <= 1;
else if (!frame_start_chn3_r && frame_done_chn3) frame_busy_chn3 <= 0;
if (rst) frame_busy_chn4 <= 0;
else if ( frame_start_chn4_r && !frame_done_chn4) frame_busy_chn4 <= 1;
else if (!frame_start_chn4_r && frame_done_chn4) frame_busy_chn4 <= 0;
end
always @ (posedge mclk) begin
frame_start_chn2_r <= set_chh2_mode && cmd_frame_start_w;
frame_start_chn3_r <= set_chh3_mode && cmd_frame_start_w;
frame_start_chn4_r <= set_chh4_mode && cmd_frame_start_w;
next_page_chn2_r <= set_chh2_mode && cmd_next_page_w;
next_page_chn3_r <= set_chh3_mode && cmd_next_page_w;
next_page_chn4_r <= set_chh4_mode && cmd_next_page_w;
end
cmd_deser #(
.ADDR (MCNTRL_TEST01_ADDR),
.ADDR_MASK (MCNTRL_TEST01_MASK),
.NUM_CYCLES (3),
.ADDR_WIDTH (4),
.DATA_WIDTH (8)
) cmd_deser_mcontr_test01_8bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_router4 status_router4_i (
.rst (rst), // input
.clk (mclk), // input
.db_in0 (status_chn2_ad), // input[7:0]
.rq_in0 (status_chn2_rq), // input
.start_in0 (status_chn2_start), // output
.db_in1 (status_chn3_ad), // input[7:0]
.rq_in1 (status_chn3_rq), // input
.start_in1 (status_chn3_start), // output
.db_in2 (status_chn4_ad), // input[7:0]
.rq_in2 (status_chn4_rq), // input
.start_in2 (status_chn4_start), // output
.db_in3 (8'b0), // input[7:0]
.rq_in3 (1'b0), // input
.start_in3 (), // output
.db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output
.start_out (status_start) // input
);
status_generate #(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn2_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chh2_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn2), // input[25:0]
.ad (status_chn2_ad), // output[7:0]
.rq (status_chn2_rq), // output
.start (status_chn2_start) // input
);
status_generate #(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn3_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chh3_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn3), // input[25:0]
.ad (status_chn3_ad), // output[7:0]
.rq (status_chn3_rq), // output
.start (status_chn3_start) // input
);
status_generate #(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn4_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chh4_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn4), // input[25:0]
.ad (status_chn4_ad), // output[7:0]
.rq (status_chn4_rq), // output
.start (status_chn4_start) // input
);
endmodule
memctrl/mcntrl_linear_rw.v
View file @ 2d03240b
......@@ -38,7 +38,7 @@ module mcntrl_linear_rw #(
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
// Read back current address (for debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
......
memctrl/mcntrl_tiled_rw.v
View file @ 2d03240b
......@@ -39,7 +39,7 @@ module mcntrl_tiled_rw#(
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
......
x393.v
View file @ 2d03240b
......@@ -158,8 +158,8 @@ module x393 #(
parameter NUM_CYCLES_01 = 4, // 4-cycle 040.007f
parameter NUM_CYCLES_02 = 3, // 3-cycle 080.00bf
parameter NUM_CYCLES_03 = 3, // 3-cycle 0c0.00ff
parameter NUM_CYCLES_04 = 4, // 4-cycle 100.013f
parameter NUM_CYCLES_05 = 4, // 4-cycle 140.017f
parameter NUM_CYCLES_04 = 6, // 6-cycle 100.013f
parameter NUM_CYCLES_05 = 6, // 6-cycle 140.017f
parameter NUM_CYCLES_06 = 4, // 4-cycle 180.01bf
parameter NUM_CYCLES_07 = 4, // 4-cycle 1c0.01ff
parameter NUM_CYCLES_08 = 6, //
......@@ -195,8 +195,9 @@ module x393 #(
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
// Read back current address (for debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h5,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
......@@ -204,7 +205,7 @@ module x393 #(
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_ADDR= 'h120,
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -215,17 +216,28 @@ module x393 #(
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter BUFFER_DEPTH32= 10 // Block rum buffer depth on a 32-bit port
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter BUFFER_DEPTH32= 10, // Block rum buffer depth on a 32-bit port
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0,
parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
)(
// DDR3 interface
output SDRST, // DDR3 reset (active low)
......@@ -335,7 +347,7 @@ module x393 #(
wire [31:0] axird_rdata; // .data_out(rdata[31:0]), // data out
// wire [31:0] port0_rdata; //
wire [31:0] status_rdata; //
wire status_valid; // never used - supposed to be always valid?
wire status_valid; /// SuppressThisWarning VEditor ****** never used - supposed to be always valid?
wire mclk;
......@@ -407,13 +419,13 @@ end
`endif
//TODO: The following is the interface to the frame-based command sequencer (not yet implemnted)
wire [AXI_WR_ADDR_BITS-1:0] cseq_waddr; // command sequencer write address (output to command multiplexer)
wire cseq_wr_en; // command sequencer write enable (output to command multiplexer) - keep until cseq_ackn received
wire [31:0] cseq_wdata; // command sequencer write data (output to command multiplexer)
wire cseq_ackn; // ackn to command sequencer, command sequencer should de-assert cseq_wr_en
wire [AXI_WR_ADDR_BITS-1:0] cseq_waddr; /// SuppressThisWarning VEditor ****** command sequencer write address (output to command multiplexer)
wire cseq_wr_en; /// SuppressThisWarning VEditor ****** command sequencer write enable (output to command multiplexer) - keep until cseq_ackn received
wire [31:0] cseq_wdata; /// SuppressThisWarning VEditor ****** command sequencer write data (output to command multiplexer)
wire cseq_ackn; /// SuppressThisWarning VEditor ****** ackn to command sequencer, command sequencer should de-assert cseq_wr_en
// parallel address/data - where higher bandwidth (single-cycle) is needed
wire [AXI_WR_ADDR_BITS-1:0] par_waddr; // multiplexed address (full, parallel) to slave devices
wire [31:0] par_data; // multiplexed data (full, parallel) to slave devices
wire [AXI_WR_ADDR_BITS-1:0] par_waddr; /// SuppressThisWarning VEditor ****** multiplexed address (full, parallel) to slave devices
wire [31:0] par_data; /// SuppressThisWarning VEditor ****** multiplexed data (full, parallel) to slave devices
......@@ -428,14 +440,98 @@ end
wire status_mcontr_rq; // Memory controller status request
wire status_mcontr_start; // Memory controller status packet transfer start (currently with 0 latency from status_root_rq)
// Not yet connected
wire [7:0] status_other_ad; // Other status byte-wide address/data
wire status_other_rq; // Other status request
wire status_other_start; // Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_other_ad; /// S uppressThisWarning VEditor ****** Other status byte-wide address/data
wire status_other_rq; /// S uppressThisWarning VEditor ****** Other status request
wire status_other_start; /// S =uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_test01_ad; // Test module status byte-wide address/data
wire status_test01_rq; // Test module status request
wire status_test01_start; // Test module status packet transfer start (currently with 0 latency from status_root_rq)
// Interface to channels to read/write memory (including 4 page BRAM buffers)
// Insert register layer if needed
wire [7:0] cmd_mcontr_ad;
wire cmd_mcontr_stb;
wire [7:0] cmd_test01_ad;
wire cmd_test01_stb;
//mcntrl393_test01
wire frame_start_chn2; // input
wire next_page_chn2; // input
wire page_ready_chn2; // output
wire frame_done_chn2; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn2; // output[15:0]
wire suspend_chn2; // input
wire frame_start_chn3; // input
wire next_page_chn3; // input
wire page_ready_chn3; // output
wire frame_done_chn3; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn3; // output[15:0]
wire suspend_chn3; // input
wire frame_start_chn4; // input
wire next_page_chn4; // input
wire page_ready_chn4; // output
wire frame_done_chn4; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4; // output[15:0]
wire suspend_chn4; // input
assign cmd_mcontr_ad= cmd_root_ad;
assign cmd_mcontr_stb=cmd_root_stb;
assign cmd_test01_ad= cmd_root_ad;
assign cmd_test01_stb=cmd_root_stb;
// For now - connect status_test01 to status_other, if needed - increase number of multiplexer inputs)
assign status_other_ad = status_test01_ad;
assign status_other_rq = status_test01_rq;
assign status_test01_start = status_other_start;
// channel test module
mcntrl393_test01 #(
.MCNTRL_TEST01_ADDR (MCNTRL_TEST01_ADDR),
.MCNTRL_TEST01_MASK (MCNTRL_TEST01_MASK),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MCNTRL_TEST01_CHN2_MODE (MCNTRL_TEST01_CHN2_MODE),
.MCNTRL_TEST01_CHN2_STATUS_CNTRL (MCNTRL_TEST01_CHN2_STATUS_CNTRL),
.MCNTRL_TEST01_CHN3_MODE (MCNTRL_TEST01_CHN3_MODE),
.MCNTRL_TEST01_CHN3_STATUS_CNTRL (MCNTRL_TEST01_CHN3_STATUS_CNTRL),
.MCNTRL_TEST01_CHN4_MODE (MCNTRL_TEST01_CHN4_MODE),
.MCNTRL_TEST01_CHN4_STATUS_CNTRL (MCNTRL_TEST01_CHN4_STATUS_CNTRL),
.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
) mcntrl393_test01_i (
.rst(axi_rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_test01_ad), // input[7:0]
.cmd_stb (cmd_test01_stb), // input
.status_ad (status_test01_ad), // output[7:0]
.status_rq (status_test01_rq), // output
.status_start (status_test01_start), // input
.frame_start_chn2 (frame_start_chn2), // output
.next_page_chn2 (next_page_chn2), // output
.page_ready_chn2 (page_ready_chn2), // input
.frame_done_chn2 (frame_done_chn2), // input
.line_unfinished_chn2 (line_unfinished_chn2), // input[15:0]
.suspend_chn2 (suspend_chn2), // output
.frame_start_chn3 (frame_start_chn3), // output
.next_page_chn3 (next_page_chn3), // output
.page_ready_chn3 (page_ready_chn3), // input
.frame_done_chn3 (frame_done_chn3), // input
.line_unfinished_chn3 (line_unfinished_chn3), // input[15:0]
.suspend_chn3 (suspend_chn3), // output
.frame_start_chn4 (frame_start_chn4), // output
.next_page_chn4 (next_page_chn4), // output
.page_ready_chn4 (page_ready_chn4), // input
.frame_done_chn4 (frame_done_chn4), // input
.line_unfinished_chn4 (line_unfinished_chn4), // input[15:0]
.suspend_chn4 (suspend_chn4) // output
);
// Interface to channels to read/write memory (including 4 page BRAM buffers)
cmd_mux #(
.AXI_WR_ADDR_BITS (AXI_WR_ADDR_BITS),
......@@ -500,13 +596,6 @@ end
);
// Insert register layer if needed
wire [7:0] cmd_mcontr_ad;
wire cmd_mcontr_stb;
assign cmd_mcontr_ad= cmd_root_ad;
assign cmd_mcontr_stb=cmd_root_stb;
// mux status info from the memory controller and other modules
status_router2 status_router2_top_i (
.rst (axi_rst), // input
......@@ -623,11 +712,12 @@ end
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_ADDR (MCNTRL_TILED_ADDR),
.MCNTRL_TILED_CHN4_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
......@@ -637,7 +727,7 @@ end
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WH (MCNTRL_TILED_TILE_WH),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_ADDR),
.MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS (MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
) mcntrl393_i (
......@@ -682,8 +772,8 @@ end
.page_ready_chn4 (page_ready_chn4), // output
.frame_done_chn4 (frame_done_chn4), // output
.line_unfinished_chn4 (line_unfinished_chn4), // output[15:0]
.suspend_chn4 (suspend_chn4), // input
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output
......@@ -1613,7 +1703,4 @@ assign DUMMY_TO_KEEP = 1'b0; // dbg_toggle[0];
.PSSRSTB() // PS PSSRSTB, inout
);
endmodule
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