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Commit 299231f6 authored by Andrey Filippov's avatar Andrey Filippov
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connecting sensor and compressor signals to the memory controller

parent baa32a59
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compressor_jp/compressor393.v
View file @ 299231f6
...@@ -27,7 +27,7 @@ module compressor393 # ( ...@@ -27,7 +27,7 @@ module compressor393 # (
parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr) parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_RADDR1= 'h50, // relative to CMPRS_NUM_AFI_CHN ( 16 addr) parameter CMPRS_AFIMUX_RADDR1= 'h50, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_MASK= 'h7f0, parameter CMPRS_AFIMUX_MASK= 'h7f0,
// Ststus needs 'h10 (16) registers, currently 'h10..'h1f
parameter CMPRS_STATUS_REG_BASE= 'h10, parameter CMPRS_STATUS_REG_BASE= 'h10,
parameter CMPRS_HIFREQ_REG_BASE= 'h14, parameter CMPRS_HIFREQ_REG_BASE= 'h14,
parameter CMPRS_AFIMUX_REG_ADDR0= 'h18, // Uses 4 locations parameter CMPRS_AFIMUX_REG_ADDR0= 'h18, // Uses 4 locations
...@@ -35,7 +35,6 @@ module compressor393 # ( ...@@ -35,7 +35,6 @@ module compressor393 # (
parameter CMPRS_STATUS_REG_INC= 1, parameter CMPRS_STATUS_REG_INC= 1,
parameter CMPRS_HIFREQ_REG_INC= 1, parameter CMPRS_HIFREQ_REG_INC= 1,
// parameter CMPRS_ADDR= 'h120, //TODO: assign valid address
parameter CMPRS_MASK= 'h7f8, parameter CMPRS_MASK= 'h7f8,
parameter CMPRS_CONTROL_REG= 0, parameter CMPRS_CONTROL_REG= 0,
parameter CMPRS_STATUS_CNTRL= 1, parameter CMPRS_STATUS_CNTRL= 1,
...@@ -125,34 +124,29 @@ module compressor393 # ( ...@@ -125,34 +124,29 @@ module compressor393 # (
output status_rq, // input request to send status downstream output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address) input status_start, // Acknowledge of the first status packet byte (address)
// Buffer interfaces // Buffer interfaces, combined for 4 channels
input xfer_reset_page_rd_chn0, // from mcntrl_tiled_rw ( input [3:0] xfer_reset_page_rd, // from mcntrl_tiled_rw (
input buf_wpage_nxt_chn0, // advance to next page memory interface writes to input [3:0] buf_wpage_nxt, // advance to next page memory interface writes to
input buf_we_chn0, // @!mclk write buffer from memory, increment write input [3:0] buf_we, // @!mclk write buffer from memory, increment write
input [63:0] buf_din_chn0, // data out input [255:0] buf_din, // data out
input page_ready_chn0, // single mclk (posedge) input [3:0] page_ready, // single mclk (posedge)
output next_page_chn0, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data output [3:0] next_page, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
input xfer_reset_page_rd_chn1, // from mcntrl_tiled_rw (
input buf_wpage_nxt_chn1, // advance to next page memory interface writes to
input buf_we_chn1, // @!mclk write buffer from memory, increment write
input [63:0] buf_din_chn1, // data out
input page_ready_chn1, // single mclk (posedge)
output next_page_chn1, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
input xfer_reset_page_rd_chn2, // from mcntrl_tiled_rw ( // master (sensor) with slave (compressor) synchronization I/Os
input buf_wpage_nxt_chn2, // advance to next page memory interface writes to output [3:0] frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
input buf_we_chn2, // @!mclk write buffer from memory, increment write // these output either follows vsync_late (reclocks it) or generated in non-bonded mode
input [63:0] buf_din_chn2, // data out // (compress from memory)
input page_ready_chn2, // single mclk (posedge) input [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
output next_page_chn2, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data input [4*LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel
input [3:0] frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// frame_done_src is later than line_unfinished_src/ frame_number_src changes
// Used withe a single-frame buffers
input [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel
input [4*LAST_FRAME_BITS-1:0] frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel
input [3:0]frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
output [3:0]suspend, // suspend reading data for this channel - waiting for the source data
input xfer_reset_page_rd_chn3, // from mcntrl_tiled_rw (
input buf_wpage_nxt_chn3, // advance to next page memory interface writes to
input buf_we_chn3, // @!mclk write buffer from memory, increment write
input [63:0] buf_din_chn3, // data out
input page_ready_chn3, // single mclk (posedge)
output next_page_chn3, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
// statistics data was not used in late nc353 // statistics data was not used in late nc353
// input dccout, //enable output of DC and HF components for brightness/color/focus adjustments // input dccout, //enable output of DC and HF components for brightness/color/focus adjustments
...@@ -161,80 +155,18 @@ module compressor393 # ( ...@@ -161,80 +155,18 @@ module compressor393 # (
// output [15:0] statistics_do, // output [15:0] statistics_do,
// Timestamp messages (@mclk) - combine to a single ts_data? // Timestamp messages (@mclk) - combine to a single ts_data?
input ts_pre_stb_chn0, // @mclk - 1 cycle before receiving 8 bytes of timestamp data input [3:0] ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data_chn0, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0) input [31:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input ts_pre_stb_chn1, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data_chn1, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input ts_pre_stb_chn2, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data_chn2, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input ts_pre_stb_chn3, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data_chn3, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
// Outputs for interrupts generation // Outputs for interrupts generation
output eof_written_mclk_chn0, output [3:0] eof_written_mclk,
output stuffer_done_mclk_chn0, output [3:0] stuffer_done_mclk,
output eof_written_mclk_chn1,
output stuffer_done_mclk_chn1,
output eof_written_mclk_chn2,
output stuffer_done_mclk_chn2,
output eof_written_mclk_chn3,
output stuffer_done_mclk_chn3,
// frame input synchronization // frame input synchronization
input vsync_late_chn0, // delayed start of frame, @xclk. In 353 it was 16 lines after VACT active input [3:0] vsync_late, // delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands // source channel should already start, some delay give time for sequencer commands
// that should arrive before it // that should arrive before it
input vsync_late_chn1,
input vsync_late_chn2,
input vsync_late_chn3,
// master (sensor) with slave (compressor) synchronization I/Os
output frame_start_dst_chn0, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory)
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src_chn0,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
input [LAST_FRAME_BITS-1:0] frame_number_src_chn0, // current frame number (for multi-frame ranges) in the source (sensor) channel
input frame_done_src_chn0, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// frame_done_src is later than line_unfinished_src/ frame_number_src changes
// Used withe a single-frame buffers
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst_chn0,// number of the current (unfinished ) line in this (compressor) channel
input [LAST_FRAME_BITS-1:0] frame_number_dst_chn0, // current frame number (for multi-frame ranges) in this (compressor channel
input frame_done_dst_chn0, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
output suspend_chn0, // suspend reading data for this channel - waiting for the source data
output frame_start_dst_chn1,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src_chn1,
input [LAST_FRAME_BITS-1:0] frame_number_src_chn1,
input frame_done_src_chn1,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst_chn1,
input [LAST_FRAME_BITS-1:0] frame_number_dst_chn1,
input frame_done_dst_chn1,
output suspend_chn1,
output frame_start_dst_chn2,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src_chn2,
input [LAST_FRAME_BITS-1:0] frame_number_src_chn2,
input frame_done_src_chn2,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst_chn2,
input [LAST_FRAME_BITS-1:0] frame_number_dst_chn2,
input frame_done_dst_chn2,
output suspend_chn2,
output frame_start_dst_chn3,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src_chn3,
input [LAST_FRAME_BITS-1:0] frame_number_src_chn3,
input frame_done_src_chn3,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst_chn3,
input [LAST_FRAME_BITS-1:0] frame_number_dst_chn3,
input frame_done_dst_chn3,
output suspend_chn3,
// AXI_HP inteface (single/dual). afi indices - relative (0,1) may actually be connected to 1,2 (or only to 1) // AXI_HP inteface (single/dual). afi indices - relative (0,1) may actually be connected to 1,2 (or only to 1)
input hclk, input hclk,
...@@ -301,38 +233,6 @@ module compressor393 # ( ...@@ -301,38 +233,6 @@ module compressor393 # (
wire [5:0] status_rq_mux; wire [5:0] status_rq_mux;
wire [5:0] status_start_mux; wire [5:0] status_start_mux;
wire [3:0] xfer_reset_page_rd = {xfer_reset_page_rd_chn3, xfer_reset_page_rd_chn2, xfer_reset_page_rd_chn1, xfer_reset_page_rd_chn0};
wire [3:0] buf_wpage_nxt = {buf_wpage_nxt_chn3, buf_wpage_nxt_chn2, buf_wpage_nxt_chn1, buf_wpage_nxt_chn0};
wire [3:0] buf_we = {buf_we_chn3, buf_we_chn2, buf_we_chn1, buf_we_chn0};
wire [255:0] buf_din = {buf_din_chn3, buf_din_chn2, buf_din_chn1, buf_din_chn0};
wire [3:0] page_ready = {page_ready_chn3, page_ready_chn2, page_ready_chn1, page_ready_chn0};
wire [3:0] next_page;
assign {next_page_chn3, next_page_chn2, next_page_chn1, next_page_chn0} = next_page;
// Timestamp messages (@mclk) - combine to a single ts_data?
wire [3:0] ts_pre_stb = {ts_pre_stb_chn3, ts_pre_stb_chn2, ts_pre_stb_chn1, ts_pre_stb_chn0};
wire [31:0] ts_data = {ts_data_chn3, ts_data_chn2, ts_data_chn1, ts_data_chn0};
// Outputs for interrupts generation
wire [3:0] eof_written_mclk;
wire [3:0] stuffer_done_mclk;
assign {eof_written_mclk_chn3, eof_written_mclk_chn2, eof_written_mclk_chn1, eof_written_mclk_chn0} = eof_written_mclk;
assign {stuffer_done_mclk_chn3, stuffer_done_mclk_chn2, stuffer_done_mclk_chn1, stuffer_done_mclk_chn0} = stuffer_done_mclk;
// frame input synchronization
wire [3:0] vsync_late = {vsync_late_chn3, vsync_late_chn2, vsync_late_chn1, vsync_late_chn0};
// master (sensor) with slave (compressor) synchronization I/Os
wire [3:0] frame_start_dst;
assign {frame_start_dst_chn3, frame_start_dst_chn2, frame_start_dst_chn1, frame_start_dst_chn0} = frame_start_dst;
wire [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_src = {line_unfinished_src_chn3, line_unfinished_src_chn2, line_unfinished_src_chn1, line_unfinished_src_chn0};
wire [4*LAST_FRAME_BITS-1:0] frame_number_src = {frame_number_src_chn3, frame_number_src_chn2, frame_number_src_chn1, frame_number_src_chn0};
wire [3:0] frame_done_src = {frame_done_src_chn3, frame_done_src_chn2, frame_done_src_chn1, frame_done_src_chn0};
wire [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_dst = {line_unfinished_dst_chn3, line_unfinished_dst_chn2, line_unfinished_dst_chn1, line_unfinished_dst_chn0};
wire [4*LAST_FRAME_BITS-1:0] frame_number_dst = {frame_number_dst_chn3, frame_number_dst_chn2, frame_number_dst_chn1, frame_number_dst_chn0};
wire [3:0] frame_done_dst = {frame_done_dst_chn3, frame_done_dst_chn2, frame_done_dst_chn1, frame_done_dst_chn0};
wire [3:0] suspend;
assign {suspend_chn3, suspend_chn2, suspend_chn1, suspend_chn0} = suspend;
// signals to connect to AFI multiplexers // signals to connect to AFI multiplexers
wire [3:0] fifo_rst; wire [3:0] fifo_rst;
wire [3:0] fifo_ren; wire [3:0] fifo_ren;
...@@ -469,6 +369,16 @@ module compressor393 # ( ...@@ -469,6 +369,16 @@ module compressor393 # (
.buf_din (buf_din[64 * i +: 64]), // input[63:0] .buf_din (buf_din[64 * i +: 64]), // input[63:0]
.page_ready_chn (page_ready[i]), // input .page_ready_chn (page_ready[i]), // input
.next_page_chn (next_page[i]), // output .next_page_chn (next_page[i]), // output
.frame_start_dst (frame_start_dst[i]), // output
.line_unfinished_src (line_unfinished_src[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0]
.frame_number_src (frame_number_src[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0]
.frame_done_src (frame_done_src[i]), // input
.line_unfinished_dst (line_unfinished_dst[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0]
.frame_number_dst (frame_number_dst[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0]
.frame_done_dst (frame_done_dst[i]), // input
.suspend (suspend[i]), // output
.dccout (1'b0), // input .dccout (1'b0), // input
.hfc_sel (3'b0), // input[2:0] .hfc_sel (3'b0), // input[2:0]
.statistics_dv (), // output .statistics_dv (), // output
...@@ -478,14 +388,6 @@ module compressor393 # ( ...@@ -478,14 +388,6 @@ module compressor393 # (
.eof_written_mclk (eof_written_mclk[i]), // output .eof_written_mclk (eof_written_mclk[i]), // output
.stuffer_done_mclk (stuffer_done_mclk[i]), // output .stuffer_done_mclk (stuffer_done_mclk[i]), // output
.vsync_late (vsync_late[i]), // input .vsync_late (vsync_late[i]), // input
.frame_start_dst (frame_start_dst[i]), // output
.line_unfinished_src (line_unfinished_src[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0]
.frame_number_src (frame_number_src[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0]
.frame_done_src (frame_done_src[i]), // input
.line_unfinished_dst (line_unfinished_dst[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0]
.frame_number_dst (frame_number_dst[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0]
.frame_done_dst (frame_done_dst[i]), // input
.suspend (suspend[i]), // output
.hclk (hclk), // input .hclk (hclk), // input
.fifo_rst (fifo_rst[i]), // input .fifo_rst (fifo_rst[i]), // input
......
compressor_jp/jp_channel.v
View file @ 299231f6
...@@ -122,6 +122,22 @@ module jp_channel#( ...@@ -122,6 +122,22 @@ module jp_channel#(
input page_ready_chn, // single mclk (posedge) input page_ready_chn, // single mclk (posedge)
output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
// Master(sensor)/slave(compressor) synchronization signals
output frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory)
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
input [LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel
input frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// frame_done_src is later than line_unfinished_src/ frame_number_src changes
// Used withe a single-frame buffers
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel
input [LAST_FRAME_BITS-1:0] frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel
input frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
output suspend, // suspend reading data for this channel - waiting for the source data
// statistics data was not used in late nc353 // statistics data was not used in late nc353
input dccout, //enable output of DC and HF components for brightness/color/focus adjustments input dccout, //enable output of DC and HF components for brightness/color/focus adjustments
input [2:0] hfc_sel, // [2:0] (for autofocus) only components with both spacial frequencies higher than specified will be added input [2:0] hfc_sel, // [2:0] (for autofocus) only components with both spacial frequencies higher than specified will be added
...@@ -139,20 +155,6 @@ module jp_channel#( ...@@ -139,20 +155,6 @@ module jp_channel#(
input vsync_late, // delayed start of frame, @xclk. In 353 it was 16 lines after VACT active input vsync_late, // delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands // source channel should already start, some delay give time for sequencer commands
// that should arrive before it // that should arrive before it
output frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory)
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
input [LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel
input frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// frame_done_src is later than line_unfinished_src/ frame_number_src changes
// Used withe a single-frame buffers
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel
input [LAST_FRAME_BITS-1:0] frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel
input frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
output suspend, // suspend reading data for this channel - waiting for the source data
// Output interface to the AFI mux // Output interface to the AFI mux
input hclk, input hclk,
......
includes/x393_parameters.vh
View file @ 299231f6
...@@ -299,10 +299,10 @@ ...@@ -299,10 +299,10 @@
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
parameter SENSI2C_STATUS_REG_BASE = 'h30, // 4 locations" x30, x32, x34, x36 parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h30, 'h32, 'h34, 'h36 parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h20, 'h22, 'h24, 'h26
parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h31, 'h33, 'h35, 'h37 parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h21, 'h23, 'h25, 'h27
parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels
parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32" parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_GAMMA_NUM_CHN = 3, // number of subchannels for his sensor ports (1..4) parameter SENS_GAMMA_NUM_CHN = 3, // number of subchannels for his sensor ports (1..4)
...@@ -439,6 +439,94 @@ ...@@ -439,6 +439,94 @@
parameter SENS_REF_JITTER2 = 0.010, parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter CMPRS_NUM_AFI_CHN = 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_RADDR1= 'h50, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_MASK= 'h7f0,
parameter CMPRS_STATUS_REG_BASE= 'h10,
parameter CMPRS_HIFREQ_REG_BASE= 'h14,
parameter CMPRS_AFIMUX_REG_ADDR0= 'h18, // Uses 4 locations
parameter CMPRS_AFIMUX_REG_ADDR1= 'h1c, // Uses 4 locations
parameter CMPRS_STATUS_REG_INC= 1,
parameter CMPRS_HIFREQ_REG_INC= 1,
parameter CMPRS_MASK= 'h7f8,
parameter CMPRS_CONTROL_REG= 0,
parameter CMPRS_STATUS_CNTRL= 1,
parameter CMPRS_FORMAT= 2,
parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_TABLES= 6, // 6..7
// Bit-fields in compressor control word
parameter CMPRS_CBIT_RUN = 2, // bit # to control compressor run modes
parameter CMPRS_CBIT_RUN_BITS = 2, // number of bits to control compressor run modes
parameter CMPRS_CBIT_QBANK = 6, // bit # to control quantization table page
parameter CMPRS_CBIT_QBANK_BITS = 3, // number of bits to control quantization table page
parameter CMPRS_CBIT_DCSUB = 8, // bit # to control extracting DC components bypassing DCT
parameter CMPRS_CBIT_DCSUB_BITS = 1, // bit # to control extracting DC components bypassing DCT
parameter CMPRS_CBIT_CMODE = 13, // bit # to control compressor color modes
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
parameter CMPRS_CBIT_RUN_STANDALONE = 2'h2, // enable compressor, compress single frame from memory (async)
parameter CMPRS_CBIT_RUN_ENABLE = 2'h3, // enable compressor, enable synchronous compression mode
parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks, dc-improved
parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
parameter CMPRS_COLOR20 = 1, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer (not implemented)
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBRM1 = 13, // bit # of number of macroblock rows minus 1 field in format word
parameter CMPRS_FRMT_MBRM1_BITS = 13, // number of bits in number of macroblock rows minus 1 field in format word
parameter CMPRS_FRMT_LMARG = 26, // bit # of left margin field in format word
parameter CMPRS_FRMT_LMARG_BITS = 5, // number of bits in left margin field in format word
parameter CMPRS_CSAT_CB = 0, // bit # of number of blue scale field in color saturation word
parameter CMPRS_CSAT_CB_BITS = 10, // number of bits in blue scale field in color saturation word
parameter CMPRS_CSAT_CR = 12, // bit # of number of red scale field in color saturation word
parameter CMPRS_CSAT_CR_BITS = 10, // number of bits in red scale field in color saturation word
parameter CMPRS_CORING_BITS = 3, // number of bits in coring mode
parameter CMPRS_TIMEOUT_BITS= 12,
parameter CMPRS_TIMEOUT= 1000, // mclk cycles
parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel)
parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets
parameter CMPRS_AFIMUX_MODE= 'h2, // per-channel select - which register to return as status
parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7
parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
\ No newline at end of file
memctrl/mcntrl393.v
View file @ 299231f6
...@@ -21,7 +21,16 @@ ...@@ -21,7 +21,16 @@
`timescale 1ns/1ps `timescale 1ns/1ps
`include "system_defines.vh" `include "system_defines.vh"
module mcntrl393 #( module mcntrl393 #(
// AXI // MAXI address space, in 32-bit words
parameter MCONTR_SENS_BASE = 'h680, // .. 'h6bf
parameter MCONTR_SENS_INC = 'h10,
parameter MCONTR_CMPRS_BASE = 'h6c0, // .. 'h6ff
parameter MCONTR_CMPRS_INC = 'h10,
parameter MCONTR_SENS_STATUS_BASE = 'h28, // .. 'h2b
parameter MCONTR_SENS_STATUS_INC = 'h1,
parameter MCONTR_CMPRS_STATUS_BASE = 'h2c, // .. 'h2f
parameter MCONTR_CMPRS_STATUS_INC = 'h1,
parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy
...@@ -261,8 +270,35 @@ module mcntrl393 #( ...@@ -261,8 +270,35 @@ module mcntrl393 #(
// wire [31:0] axird_bram_rdata; // .data_out(rdata[31:0]), // data out // wire [31:0] axird_bram_rdata; // .data_out(rdata[31:0]), // data out
output [31:0] axird_rdata, // combinatorial multiplexed (add external register layer, modify axibram_read?) .data_out(rdata[31:0]), // data out output [31:0] axird_rdata, // combinatorial multiplexed (add external register layer, modify axibram_read?) .data_out(rdata[31:0]), // data out
output axird_selected, // axird_rdata contains valid data from this module output axird_selected, // axird_rdata contains valid data from this module
// wire [31:0] port0_rdata; //
// wire [31:0] status_rdata; // // sensor subsystem interface
output [3:0] sens_rpage_set, // (), // input
output [3:0] sens_rpage_next, // (), // input
output [3:0] sens_buf_rd, // (), // input
input [255:0] sens_buf_dout, // (), // output[63:0]
// compressor subsystem interface
// Buffer interfaces, combined for 4 channels
output [3:0] cmprs_xfer_reset_page_rd, // from mcntrl_tiled_rw (
output [3:0] cmprs_buf_wpage_nxt, // advance to next page memory interface writes to
output [3:0] cmprs_buf_we, // @!mclk write buffer from memory, increment write
output [255:0] cmprs_buf_din, // data out
output [3:0] cmprs_page_ready, // single mclk (posedge)
input [3:0] cmprs_next_page, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
// master (sensor) with slave (compressor) synchronization I/Os
input [3:0] cmprs_frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory)
output [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
output [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel
output [3:0] cmprs_frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// frame_done_src is later than line_unfinished_src/ frame_number_src changes
// Used withe a single-frame buffers
output [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel
output [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel
output [3:0] cmprs_frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
input [3:0] cmprs_suspend, // suspend reading data for this channel - waiting for the source data
// TODO: move line_unfinished and suspend to internals of this module (and control comparator modes) // TODO: move line_unfinished and suspend to internals of this module (and control comparator modes)
// Channel 1 - AFI read/write to system memory with scanline linear mode // Channel 1 - AFI read/write to system memory with scanline linear mode
...@@ -287,10 +323,6 @@ module mcntrl393 #( ...@@ -287,10 +323,6 @@ module mcntrl393 #(
output buf_rd_chn1, output buf_rd_chn1,
input [63:0] buf_rdata_chn1, input [63:0] buf_rdata_chn1,
// Channels 2 and 3 control signals // Channels 2 and 3 control signals
input frame_start_chn2, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page) input frame_start_chn2, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page_chn2, // page was read/written from/to 4*1kB on-chip buffer input next_page_chn2, // page was read/written from/to 4*1kB on-chip buffer
...@@ -320,6 +352,10 @@ module mcntrl393 #( ...@@ -320,6 +352,10 @@ module mcntrl393 #(
input suspend_chn4, // suspend transfers (from external line number comparator) input suspend_chn4, // suspend transfers (from external line number comparator)
// DDR3 interface // DDR3 interface
output SDRST, // DDR3 reset (active low) output SDRST, // DDR3 reset (active low)
output SDCLK, // DDR3 clock differential output, positive output SDCLK, // DDR3 clock differential output, positive
...@@ -345,7 +381,8 @@ module mcntrl393 #( ...@@ -345,7 +381,8 @@ module mcntrl393 #(
// temporary debug data // temporary debug data
,output [11:0] tmp_debug // add some signals generated here? ,output [11:0] tmp_debug // add some signals generated here?
); );
localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts
localparam FRAME_WBP1 = FRAME_WIDTH_BITS + 1;
wire rst=rst_in; wire rst=rst_in;
wire axi_rst=rst_in; wire axi_rst=rst_in;
...@@ -441,9 +478,15 @@ module mcntrl393 #( ...@@ -441,9 +478,15 @@ module mcntrl393 #(
wire cmd_scanline_chn3_stb; wire cmd_scanline_chn3_stb;
wire [7:0] cmd_tiled_chn2_ad; wire [7:0] cmd_tiled_chn2_ad;
wire cmd_tiled_chn2_stb; wire cmd_tiled_chn2_stb;
wire [7:0] cmd_tiled_chn4_ad; wire [7:0] cmd_tiled_chn4_ad;
wire cmd_tiled_chn4_stb; wire cmd_tiled_chn4_stb;
wire [7:0] cmd_sens_ad;
wire cmd_sens_stb;
wire [7:0] cmd_cmprs_ad;
wire cmd_cmprs_stb;
// Status tree: // Status tree:
wire [7:0] status_mcontr_ad; // Memory controller status byte-wide address/data wire [7:0] status_mcontr_ad; // Memory controller status byte-wide address/data
...@@ -470,6 +513,46 @@ module mcntrl393 #( ...@@ -470,6 +513,46 @@ module mcntrl393 #(
wire status_tiled_chn4_rq; // PL tiled channel4 (memory read) channels status request wire status_tiled_chn4_rq; // PL tiled channel4 (memory read) channels status request
wire status_tiled_chn4_start; // PL tiled channel4 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq) wire status_tiled_chn4_start; // PL tiled channel4 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
// status control for scanline sensor access, 4 channels
wire [31:0] status_sens_ad;
wire [3:0] status_sens_rq;
wire [3:0] status_sens_start;
// status control for tiled compressor access, 4 channels
wire [31:0] status_cmprs_ad;
wire [3:0] status_cmprs_rq;
wire [3:0] status_cmprs_start;
// Sensor and compressor signals
wire [3:0] sens_want;
wire [3:0] sens_need;
wire [3:0] cmprs_want;
wire [3:0] cmprs_need;
wire [3:0] sens_channel_pgm_en;
wire [3:0] sens_start_wr;
wire [11:0] sens_bank; // output[2:0]
wire [4*ADDRESS_NUMBER-1:0] sens_row; // output[14:0]
wire [4*COL_WDTH-1:0] sens_col; // output[6:0]
wire [4*6-1:0] sens_num128; // output[5:0]
wire [3:0] sens_partial; // output
wire [3:0] sens_done; // input : sequence over
wire [3:0] cmprs_channel_pgm_en;
wire [3:0] cmprs_start_rd16;
wire [3:0] cmprs_start_rd32;
wire [11:0] cmprs_bank; // output[2:0]
wire [4*ADDRESS_NUMBER-1:0] cmprs_row; // output[14:0]
wire [4*COL_WDTH-1:0] cmprs_col; // output[6:0]
wire [4*FRAME_WBP1-1:0] cmprs_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [4*MAX_TILE_WIDTH-1:0] cmprs_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [4*MAX_TILE_HEIGHT-1:0] cmprs_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [3:0] cmprs_keep_open; // start generating commands
wire [3:0] cmprs_partial; // output
wire [3:0] cmprs_done; // input : sequence over
// combinatorial early signals // combinatorial early signals
wire select_cmd0_w; wire select_cmd0_w;
wire select_buf0rd_w; wire select_buf0rd_w;
...@@ -534,7 +617,7 @@ module mcntrl393 #( ...@@ -534,7 +617,7 @@ module mcntrl393 #(
// common for channels 1 and 3 // common for channels 1 and 3
wire [2:0] lin_rw_bank; // memory bank wire [2:0] lin_rw_bank; // memory bank
wire [ADDRESS_NUMBER-1:0] lin_rw_row; // memory row wire [ADDRESS_NUMBER-1:0] lin_rw_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_rw_col; // start memory column in 8-bursts wire [COL_WDTH-1:0] lin_rw_col; // start memory column in 8-bursts
wire [5:0] lin_rw_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [5:0] lin_rw_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rw_xfer_partial; // do not increment page in the end, continue current wire lin_rw_xfer_partial; // do not increment page in the end, continue current
wire lin_rw_start_rd; // start generating commands for read sequence wire lin_rw_start_rd; // start generating commands for read sequence
...@@ -542,7 +625,7 @@ module mcntrl393 #( ...@@ -542,7 +625,7 @@ module mcntrl393 #(
wire [2:0] lin_rw_chn1_bank; // bank address wire [2:0] lin_rw_chn1_bank; // bank address
wire [ADDRESS_NUMBER-1:0] lin_rw_chn1_row; // memory row wire [ADDRESS_NUMBER-1:0] lin_rw_chn1_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_rw_chn1_col; // start memory column in 8-bursts wire [COL_WDTH-1:0] lin_rw_chn1_col; // start memory column in 8-bursts
wire [5:0] lin_rw_chn1_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [5:0] lin_rw_chn1_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rw_chn1_partial; // do not increment page in the end, continue current wire lin_rw_chn1_partial; // do not increment page in the end, continue current
wire lin_rw_chn1_start_rd; // start generating commands wire lin_rw_chn1_start_rd; // start generating commands
...@@ -552,7 +635,7 @@ module mcntrl393 #( ...@@ -552,7 +635,7 @@ module mcntrl393 #(
wire [2:0] lin_rw_chn3_bank; // bank address wire [2:0] lin_rw_chn3_bank; // bank address
wire [ADDRESS_NUMBER-1:0] lin_rw_chn3_row; // memory row wire [ADDRESS_NUMBER-1:0] lin_rw_chn3_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_rw_chn3_col; // start memory column in 8-bursts wire [COL_WDTH-1:0] lin_rw_chn3_col; // start memory column in 8-bursts
wire [5:0] lin_rw_chn3_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [5:0] lin_rw_chn3_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rw_chn3_partial; // do not increment page in the end, continue current wire lin_rw_chn3_partial; // do not increment page in the end, continue current
wire lin_rw_chn3_start_rd; // start generating commands wire lin_rw_chn3_start_rd; // start generating commands
...@@ -563,7 +646,7 @@ module mcntrl393 #( ...@@ -563,7 +646,7 @@ module mcntrl393 #(
// common for tiled r/w - channels 2 and 4 // common for tiled r/w - channels 2 and 4
wire [2:0] tiled_rw_bank; // bank address wire [2:0] tiled_rw_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rw_row; // memory row wire [ADDRESS_NUMBER-1:0] tiled_rw_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rw_col; // start memory column in 8-bursts wire [COL_WDTH-1:0] tiled_rw_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rw_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [FRAME_WIDTH_BITS:0] tiled_rw_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rw_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [MAX_TILE_WIDTH-1:0] tiled_rw_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rw_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [MAX_TILE_HEIGHT-1:0] tiled_rw_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
...@@ -572,7 +655,7 @@ module mcntrl393 #( ...@@ -572,7 +655,7 @@ module mcntrl393 #(
wire [2:0] tiled_rw_chn2_bank; // bank address wire [2:0] tiled_rw_chn2_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rw_chn2_row; // memory row wire [ADDRESS_NUMBER-1:0] tiled_rw_chn2_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rw_chn2_col; // start memory column in 8-bursts wire [COL_WDTH-1:0] tiled_rw_chn2_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rw_chn2_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [FRAME_WIDTH_BITS:0] tiled_rw_chn2_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rw_chn2_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [MAX_TILE_WIDTH-1:0] tiled_rw_chn2_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rw_chn2_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [MAX_TILE_HEIGHT-1:0] tiled_rw_chn2_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
...@@ -589,7 +672,7 @@ module mcntrl393 #( ...@@ -589,7 +672,7 @@ module mcntrl393 #(
wire [2:0] tiled_rw_chn4_bank; // bank address wire [2:0] tiled_rw_chn4_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rw_chn4_row; // memory row wire [ADDRESS_NUMBER-1:0] tiled_rw_chn4_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rw_chn4_col; // start memory column in 8-bursts wire [COL_WDTH-1:0] tiled_rw_chn4_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rw_chn4_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [FRAME_WIDTH_BITS:0] tiled_rw_chn4_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rw_chn4_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [MAX_TILE_WIDTH-1:0] tiled_rw_chn4_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rw_chn4_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [MAX_TILE_HEIGHT-1:0] tiled_rw_chn4_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
...@@ -645,6 +728,11 @@ module mcntrl393 #( ...@@ -645,6 +728,11 @@ module mcntrl393 #(
assign cmd_tiled_chn4_ad= cmd_ad; assign cmd_tiled_chn4_ad= cmd_ad;
assign cmd_tiled_chn4_stb= cmd_stb; assign cmd_tiled_chn4_stb= cmd_stb;
assign cmd_sens_ad= cmd_ad;
assign cmd_sens_stb= cmd_stb;
assign cmd_cmprs_ad= cmd_ad;
assign cmd_cmprs_stb= cmd_stb;
// For now - combinatorial, maybe add registers (modify axibram_read) // For now - combinatorial, maybe add registers (modify axibram_read)
...@@ -736,56 +824,58 @@ module mcntrl393 #( ...@@ -736,56 +824,58 @@ module mcntrl393 #(
end end
//axiwr_waddr //axiwr_waddr
status_router16 status_router16_mctrl_top_i ( status_router16 status_router16_mctrl_top_i (
.rst (rst), // input .rst (rst), // input
.clk (mclk), // input .clk (mclk), // input
.db_in0 (status_mcontr_ad), // input[7:0] .db_in0 (status_mcontr_ad), // input[7:0]
.rq_in0 (status_mcontr_rq), // input .rq_in0 (status_mcontr_rq), // input
.start_in0 (status_mcontr_start), // output .start_in0 (status_mcontr_start), // output
.db_in1 (status_ps_pio_ad), // input[7:0] .db_in1 (status_ps_pio_ad), // input[7:0]
.rq_in1 (status_ps_pio_rq), // input .rq_in1 (status_ps_pio_rq), // input
.start_in1 (status_ps_pio_start), // output .start_in1 (status_ps_pio_start), // output
.db_in2 (status_scanline_chn1_ad), // input[7:0] .db_in2 (status_scanline_chn1_ad), // input[7:0]
.rq_in2 (status_scanline_chn1_rq), // input .rq_in2 (status_scanline_chn1_rq), // input
.start_in2 (status_scanline_chn1_start), // output .start_in2 (status_scanline_chn1_start), // output
.db_in3 (status_scanline_chn3_ad), // input[7:0] .db_in3 (status_scanline_chn3_ad), // input[7:0]
.rq_in3 (status_scanline_chn3_rq), // input .rq_in3 (status_scanline_chn3_rq), // input
.start_in3 (status_scanline_chn3_start), // output .start_in3 (status_scanline_chn3_start), // output
.db_in4 (status_tiled_chn2_ad), // input[7:0] .db_in4 (status_tiled_chn2_ad), // input[7:0]
.rq_in4 (status_tiled_chn2_rq), // input .rq_in4 (status_tiled_chn2_rq), // input
.start_in4 (status_tiled_chn2_start), // output .start_in4 (status_tiled_chn2_start), // output
.db_in5 (status_tiled_chn4_ad), // input[7:0] .db_in5 (status_tiled_chn4_ad), // input[7:0]
.rq_in5 (status_tiled_chn4_rq), // input .rq_in5 (status_tiled_chn4_rq), // input
.start_in5 (status_tiled_chn4_start), // output .start_in5 (status_tiled_chn4_start), // output
// spare
.db_in6 (8'b0), // input[7:0] .db_in6 (8'b0), // input[7:0]
.rq_in6 (1'b0), // input .rq_in6 (1'b0), // input
.start_in6 (), // output .start_in6 (), // output
.db_in7 (8'b0), // input[7:0] .db_in7 (8'b0), // input[7:0]
.rq_in7 (1'b0), // input .rq_in7 (1'b0), // input
.start_in7 (), // output .start_in7 (), // output
.db_in8 (8'b0), // input[7:0]
.rq_in8 (1'b0), // input .db_in8 (status_sens_ad[0 * 8 +: 8]), // input[7:0]
.start_in8 (), // output .rq_in8 (status_sens_rq[0]), // input
.db_in9 (8'b0), // input[7:0] .start_in8 (status_sens_start[0]), // output
.rq_in9 (1'b0), // input .db_in9 (status_sens_ad[1 * 8 +: 8]), // input[7:0]
.start_in9 (), // output .rq_in9 (status_sens_rq[1]), // input
.db_in10 (8'b0), // input[7:0] .start_in9 (status_sens_start[1]), // output
.rq_in10 (1'b0), // input .db_in10 (status_sens_ad[2 * 8 +: 8]), // input[7:0]
.start_in10(), // output .rq_in10 (status_sens_rq[2]), // input
.db_in11 (8'b0), // input[7:0] .start_in10 (status_sens_start[2]), // output
.rq_in11 (1'b0), // input .db_in11 (status_sens_ad[3 * 8 +: 8]), // input[7:0]
.start_in11(), // output .rq_in11 (status_sens_rq[3]), // input
.db_in12 (8'b0), // input[7:0] .start_in11 (status_sens_start[3]), // output
.rq_in12 (1'b0), // input .db_in12 (status_cmprs_ad[0 * 8 +: 8]), // input[7:0]
.start_in12(), // output .rq_in12 (status_cmprs_rq[0]), // input
.db_in13 (8'b0), // input[7:0] .start_in12 (status_cmprs_start[0]), // output
.rq_in13 (1'b0), // input .db_in13 (status_cmprs_ad[1 * 8 +: 8]), // input[7:0]
.start_in13(), // output .rq_in13 (status_cmprs_rq[1]), // input
.db_in14 (8'b0), // input[7:0] .start_in13 (status_cmprs_start[1]), // output
.rq_in14 (1'b0), // input .db_in14 (status_cmprs_ad[2 * 8 +: 8]), // input[7:0]
.start_in14(), // output .rq_in14 (status_cmprs_rq[2]), // input
.db_in15 (8'b0), // input[7:0] .start_in14 (status_cmprs_start[2]), // output
.rq_in15 (1'b0), // input .db_in15 (status_cmprs_ad[3 * 8 +: 8]), // input[7:0]
.start_in15(), // output .rq_in15 (status_cmprs_rq[3]), // input
.start_in15 (status_cmprs_start[3]), // output
.db_out (status_ad), // output[7:0] .db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output .rq_out (status_rq), // output
...@@ -939,6 +1029,124 @@ module mcntrl393 #( ...@@ -939,6 +1029,124 @@ module mcntrl393 #(
.rd (buf_rd_chn4), // input .rd (buf_rd_chn4), // input
.data_out (buf_rdata_chn4) // output[63:0] .data_out (buf_rdata_chn4) // output[63:0]
); );
generate
genvar i;
for (i = 0; i < 4; i = i+1) begin:sens_comp_block
mcntrl_linear_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.LAST_FRAME_BITS (LAST_FRAME_BITS),
.MCNTRL_SCANLINE_ADDR (MCONTR_SENS_BASE + MCONTR_SENS_INC * i),
.MCNTRL_SCANLINE_MASK (MCNTRL_SCANLINE_MASK),
.MCNTRL_SCANLINE_MODE (MCNTRL_SCANLINE_MODE),
.MCNTRL_SCANLINE_STATUS_CNTRL (MCNTRL_SCANLINE_STATUS_CNTRL),
.MCNTRL_SCANLINE_STARTADDR (MCNTRL_SCANLINE_STARTADDR),
.MCNTRL_SCANLINE_FRAME_FULL_WIDTH (MCNTRL_SCANLINE_FRAME_FULL_WIDTH),
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCONTR_SENS_STATUS_BASE + MCONTR_SENS_STATUS_INC * i),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
) mcntrl_linear_wr_sensor_i (
.rst (rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_sens_ad), // input[7:0]
.cmd_stb (cmd_sens_stb), // input
.status_ad (status_sens_ad[i * 8 +: 8]), // output[7:0]
.status_rq (status_sens_rq[i]), // output
.status_start (status_sens_start[i]), // input
.frame_start (WTF_WTF_WTF), // input
.next_page (sens_rpage_next[i]), // input
.frame_done (WTF_WTF_WTF), // output - just as status to reed somewhere?
.frame_finished (), // output
.line_unfinished (cmprs_line_unfinished_src[i * FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS]), // output[15:0]
.suspend (1'b0), // input
.frame_number (cmprs_frame_number_src[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]),
.xfer_want (sens_want[i]), // output
.xfer_need (sens_need[i]), // output
.xfer_grant (sens_channel_pgm_en[i]), // input
.xfer_start_rd (), // output
.xfer_start_wr (sens_start_wr[i]), // output
.xfer_bank (sens_bank[3 * i +: 3]), // output[2:0]
.xfer_row (sens_row[ADDRESS_NUMBER * i +: ADDRESS_NUMBER]), // output[14:0]
.xfer_col (sens_col[COL_WDTH * i +: COL_WDTH]), // output[6:0]
.xfer_num128 (sens_num128[i * 6 +: 6]), // output[5:0]
.xfer_partial (sens_partial[i]), // output
.xfer_done (sens_done[i]), // input : sequence over
.xfer_page_rst_wr (sens_rpage_set[i]), // output
.xfer_page_rst_rd (), // output
.cmd_wrmem () // output
);
mcntrl_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.LAST_FRAME_BITS (LAST_FRAME_BITS),
.MCNTRL_TILED_ADDR (MCONTR_CMPRS_BASE + MCONTR_CMPRS_INC * i),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
.MCNTRL_TILED_STARTADDR (MCNTRL_TILED_STARTADDR),
.MCNTRL_TILED_FRAME_FULL_WIDTH (MCNTRL_TILED_FRAME_FULL_WIDTH),
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCONTR_CMPRS_STATUS_BASE + MCONTR_CMPRS_STATUS_INC * i),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
) mcntrl_tiled_rd_compressor_i (
.rst (rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_cmprs_ad), // input[7:0]
.cmd_stb (cmd_cmprs_stb), // input
.status_ad (status_cmprs_ad[i * 8 +: 8]), // output[7:0]
.status_rq (status_cmprs_rq[i]), // output
.status_start (status_cmprs_start[i]), // input
.frame_start (cmprs_frame_start_dst[i]), // input
.next_page (WTF_WTF_WTF), // input compressor consumed page cmprs_buf_wpage_nxt?
.frame_done (cmprs_frame_done_dst[i]), // output
.frame_finished (), // output
.line_unfinished (cmprs_line_unfinished_dst[i * FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS]), // output[15:0]
.suspend (cmprs_suspend[i]), // input
.frame_number (cmprs_frame_number_dst[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]),
.xfer_want (cmprs_want[i]), // output
.xfer_need (cmprs_need[i]), // output
.xfer_grant (cmprs_channel_pgm_en[i]), // input
.xfer_start_rd (cmprs_start_rd16[i]), // output
.xfer_start_wr (), // output
.xfer_start32_rd (cmprs_start_rd32[i]), // output
.xfer_start32_wr (), // output
.xfer_bank (cmprs_bank[i * 3 +: 3]), // output[2:0]
.xfer_row (cmprs_row[ADDRESS_NUMBER * i +: ADDRESS_NUMBER]), // output[14:0]
.xfer_col (cmprs_col[COL_WDTH * i +: COL_WDTH]), // output[6:0]
.rowcol_inc (cmprs_rowcol_inc[i * FRAME_WBP1 +: FRAME_WBP1]), // output[13:0]
.num_rows_m1 (cmprs_num_rows_m1[i * MAX_TILE_WIDTH +: MAX_TILE_WIDTH]), // output[5:0]
.num_cols_m1 (cmprs_num_cols_m1[i * MAX_TILE_HEIGHT +: MAX_TILE_HEIGHT]), // output[5:0]
.keep_open (cmprs_keep_open[i]), // output
.xfer_partial (cmprs_partial[i]), // output
.xfer_page_done (cmprs_done[i]), // input
.xfer_page_rst_wr (), // output
.xfer_page_rst_rd (cmprs_xfer_reset_page_rd[i]) // output
);
end
endgenerate
mcntrl_linear_rw #( mcntrl_linear_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER), .ADDRESS_NUMBER (ADDRESS_NUMBER),
...@@ -970,7 +1178,7 @@ module mcntrl393 #( ...@@ -970,7 +1178,7 @@ module mcntrl393 #(
.frame_start (frame_start_chn1), // input .frame_start (frame_start_chn1), // input
.next_page (next_page_chn1), // input .next_page (next_page_chn1), // input
.frame_done (frame_done_chn1), // output .frame_done (frame_done_chn1), // output
.frame_finished (), // output .frame_finished (), // output
.line_unfinished (line_unfinished_chn1), // output[15:0] .line_unfinished (line_unfinished_chn1), // output[15:0]
.suspend (suspend_chn1), // input .suspend (suspend_chn1), // input
.frame_number (), // output[15:0] - not used for this channel .frame_number (), // output[15:0] - not used for this channel
......
sensor/sens_parallel12.v
View file @ 299231f6
...@@ -28,7 +28,7 @@ module sens_parallel12 #( ...@@ -28,7 +28,7 @@ module sens_parallel12 #(
parameter SENSIO_JTAG = 'h2, parameter SENSIO_JTAG = 'h2,
parameter SENSIO_WIDTH = 'h3, // set line width (1.. 2^16) if 0 - use HACT parameter SENSIO_WIDTH = 'h3, // set line width (1.. 2^16) if 0 - use HACT
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data
parameter SENSIO_STATUS_REG = 'h31, parameter SENSIO_STATUS_REG = 'h21,
parameter SENS_JTAG_PGMEN = 8, parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6, parameter SENS_JTAG_PROG = 6,
......
sensor/sensor_i2c_io.v
View file @ 299231f6
...@@ -28,7 +28,7 @@ module sensor_i2c_io#( ...@@ -28,7 +28,7 @@ module sensor_i2c_io#(
parameter SENSI2C_CTRL_MASK = 'h7fe, parameter SENSI2C_CTRL_MASK = 'h7fe,
parameter SENSI2C_CTRL = 'h0, parameter SENSI2C_CTRL = 'h0,
parameter SENSI2C_STATUS = 'h1, parameter SENSI2C_STATUS = 'h1,
parameter SENSI2C_STATUS_REG = 'h30, parameter SENSI2C_STATUS_REG = 'h20,
parameter integer SENSI2C_DRIVE = 12, parameter integer SENSI2C_DRIVE = 12,
parameter SENSI2C_IBUF_LOW_PWR = "TRUE", parameter SENSI2C_IBUF_LOW_PWR = "TRUE",
parameter SENSI2C_IOSTANDARD = "DEFAULT", parameter SENSI2C_IOSTANDARD = "DEFAULT",
......
sensor/sensors393.v
View file @ 299231f6
...@@ -29,11 +29,11 @@ module sensors393 #( ...@@ -29,11 +29,11 @@ module sensors393 #(
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
// Sesnors use 8 status registers, 'h20..'h27
parameter SENSI2C_STATUS_REG_BASE = 'h30, // 4 locations" x30, x32, x34, x36 parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h30, 'h32, 'h34, 'h36 parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h20, 'h22, 'h24, 'h26
parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h31, 'h33, 'h35, 'h37 parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h21, 'h23, 'h25, 'h27
parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels
parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32" parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_GAMMA_NUM_CHN = 3, // number of subchannels for his sensor ports (1..4) parameter SENS_GAMMA_NUM_CHN = 3, // number of subchannels for his sensor ports (1..4)
...@@ -225,26 +225,11 @@ module sensors393 #( ...@@ -225,26 +225,11 @@ module sensors393 #(
inout sns4_ctl, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only inout sns4_ctl, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns4_pg, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only inout sns4_pg, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
// Memory interface // Memory interface (4 channels)
input rpage_set0, // set internal read page to rpage_in (reset pointers) input [3:0] rpage_set, // set internal read page to rpage_in (reset pointers)
input rpage_next0, // advance to next page (and reset lower bits to 0) input [3:0] rpage_next, // advance to next page (and reset lower bits to 0)
input buf_rd0, // read buffer to memory, increment read address (regester enable will be delayed) input [3:0] buf_rd, // read buffer to memory, increment read address (regester enable will be delayed)
output [63:0] buf_dout0, // data out output [255:0] buf_dout, // data out
input rpage_set1, // set internal read page to rpage_in (reset pointers)
input rpage_next1, // advance to next page (and reset lower bits to 0)
input buf_rd1, // read buffer to memory, increment read address (regester enable will be delayed)
output [63:0] buf_dout1, // data out
input rpage_set2, // set internal read page to rpage_in (reset pointers)
input rpage_next2, // advance to next page (and reset lower bits to 0)
input buf_rd2, // read buffer to memory, increment read address (regester enable will be delayed)
output [63:0] buf_dout2, // data out
input rpage_set3, // set internal read page to rpage_in (reset pointers)
input rpage_next3, // advance to next page (and reset lower bits to 0)
input buf_rd3, // read buffer to memory, increment read address (regester enable will be delayed)
output [63:0] buf_dout3, // data out
// Lower bits of frame numbers to use with the histograms, get from the sequencers // Lower bits of frame numbers to use with the histograms, get from the sequencers
// trigger inputs // trigger inputs
...@@ -291,10 +276,6 @@ module sensors393 #( ...@@ -291,10 +276,6 @@ module sensors393 #(
); );
wire [3:0] rpage_set = {rpage_set3, rpage_set2, rpage_set1, rpage_set0}; // set internal read page to rpage_in (reset pointers)
wire [3:0] rpage_next = {rpage_next3, rpage_next2, rpage_next1, rpage_next0}; // advance to next page (and reset lower bits to 0)
wire [3:0] buf_rd = {buf_rd3, buf_rd2, buf_rd1, buf_rd0}; // read buffer to memory, increment read address (regester enable will be delayed)
reg [7:0] cmd_ad; reg [7:0] cmd_ad;
reg cmd_stb; reg cmd_stb;
...@@ -310,13 +291,6 @@ module sensors393 #( ...@@ -310,13 +291,6 @@ module sensors393 #(
wire [7:0] hist_chn; wire [7:0] hist_chn;
wire [3:0] hist_dvalid; wire [3:0] hist_dvalid;
wire [127:0] hist_data; wire [127:0] hist_data;
wire [255:0] buf_dout_all;
// wire [3:0] sns_pg; // bidir!
//my_alias
// my_alias #(.WIDTH(4)) my_alias_i (sns_pg, {sns4_pg, sns3_pg, sns2_pg, sns1_pg});
assign {buf_dout3, buf_dout2, buf_dout1, buf_dout0} = buf_dout_all;
always @ (posedge mclk) begin always @ (posedge mclk) begin
cmd_ad <= cmd_ad_in; cmd_ad <= cmd_ad_in;
...@@ -474,7 +448,7 @@ module sensors393 #( ...@@ -474,7 +448,7 @@ module sensors393 #(
.rpage_set (rpage_set[i]), // input .rpage_set (rpage_set[i]), // input
.rpage_next (rpage_next[i]), // input .rpage_next (rpage_next[i]), // input
.buf_rd (buf_rd[i]), // input .buf_rd (buf_rd[i]), // input
.buf_dout (buf_dout_all[64*i +: 64]) // output[63:0] .buf_dout (buf_dout[64*i +: 64]) // output[63:0]
); );
end end
endgenerate endgenerate
...@@ -581,13 +555,3 @@ module sensors393 #( ...@@ -581,13 +555,3 @@ module sensors393 #(
endmodule endmodule
// TODO: if that works, move it to util_modules
/*
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
module my_alias #(
parameter WIDTH=1
) (a,a);
inout [WIDTH-1:0] a; // SuppressThisWarning VEditor : it is just an alias for bidirectional wires
endmodule
*/
x393.v
View file @ 299231f6
...@@ -186,9 +186,20 @@ module x393 #( ...@@ -186,9 +186,20 @@ module x393 #(
reg readback_selected_regen; reg readback_selected_regen;
reg mcntrl_axird_selected_regen; // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles) reg mcntrl_axird_selected_regen; // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
// global clocks
wire mclk; // global clock, memory controller, command/status network (currently 200MHz) wire mclk; // global clock, memory controller, command/status network (currently 200MHz)
wire ref_clk; // global clock for idelay_ctrl calibration wire ref_clk; // global clock for idelay_ctrl calibration
wire hclk; // global clock, axi_hp (150MHz) derived from aclk_in = 50MHz wire hclk; // global clock, axi_hp (150MHz) derived from aclk_in = 50MHz
// sensor pixel rate clock likely to originate from the external clock
wire pclk; // global clock, sensor pixel rate (96 MHz)
wire pclk2x; // global clock, sensor double pixel rate (192 MHz)
// compressor pixel rate can be adjusted independently
wire xclk; // global clock, compressor pixel rate (100 MHz)?
wire xclk2x; // global clock, compressor double pixel rate (200 MHz)
wire [11:0] tmp_debug; wire [11:0] tmp_debug;
...@@ -345,26 +356,10 @@ module x393 #( ...@@ -345,26 +356,10 @@ module x393 #(
wire [63:0] gpio_in; wire [63:0] gpio_in;
// signals for sensor393 (in/outs as sseen for the sensor393) // signals for sensor393 (in/outs as sseen for the sensor393)
wire rpage_set0; // (), // input wire [3:0] sens_rpage_set; // (), // input
wire rpage_next0; // (), // input wire [3:0] sens_rpage_next; // (), // input
wire buf_rd0; // (), // input wire [3:0] sens_buf_rd; // (), // input
wire [63:0] buf_dout0; // (), // output[63:0] wire [255:0] sens_buf_dout; // (), // output[63:0]
wire rpage_set1; // (), // input
wire rpage_next1; // (), // input
wire buf_rd1; // (), // input
wire [63:0] buf_dout1; // (), // output[63:0]
wire rpage_set2; // (), // input
wire rpage_next2; // (), // input
wire buf_rd2; // (), // input
wire [63:0] buf_dout2; // (), // output[63:0]
wire rpage_set3; // (), // input
wire rpage_next3; // (), // input
wire buf_rd3; // (), // input
wire [63:0] buf_dout3; // (), // output[63:0]
wire trigger_mode; // (), // input wire trigger_mode; // (), // input
wire [3:0] trig_in; // input[3:0] wire [3:0] trig_in; // input[3:0]
...@@ -379,9 +374,41 @@ module x393 #( ...@@ -379,9 +374,41 @@ module x393 #(
wire [NUM_FRAME_BITS - 1:0] frame_num2; // (), // input[3:0] wire [NUM_FRAME_BITS - 1:0] frame_num2; // (), // input[3:0]
wire [NUM_FRAME_BITS - 1:0] frame_num3; // (), // input[3:0] wire [NUM_FRAME_BITS - 1:0] frame_num3; // (), // input[3:0]
// signals for compressor393 (in/outs as seen for the sensor393)
// per-channel memory buffers interface
wire [3:0] cmprs_xfer_reset_page_rd; // input
wire [3:0] cmprs_buf_wpage_nxt; // input
wire [3:0] cmprs_buf_we; // input
wire [255:0] cmprs_buf_din; // input[63:0]
wire [3:0] cmprs_page_ready; // input
wire [3:0] cmprs_next_page; // output
// per-channel master (sesnor)/slave (compressor) synchronization (compressor wait until sesnor provided data)
wire [3:0] cmprs_frame_start_dst; // output - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory)
wire [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_src; // input[15:0] number of the current (unfinished ) line, in the source (sensor)
// channel (RELATIVE TO FRAME, NOT WINDOW?)
wire [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_src;// input[15:0] current frame number (for multi-frame ranges) in the source (sensor) channel
wire [3:0] cmprs_frame_done_src; // input single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// frame_done_src is later than line_unfinished_src/ frame_number_src changes
// Used withe a single-frame buffers
wire [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_dst; // input[15:0] number of the current (unfinished ) line in this (compressor) channel
wire [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_dst; // input[15:0] current frame number (for multi-frame ranges) in this (compressor channel
wire [3:0] cmprs_frame_done_dst; // input single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
wire [3:0] cmprs_suspend; // output suspend reading data for this channel - waiting for the source data
// Timestamp messages (@mclk) - combine to a single ts_data?
wire [3:0] ts_pre_stb; // input
wire [31:0] ts_data; // input[7:0]
// Compressor signals for interrupts generation
wire [3:0] eof_written_mclk; // output
wire [3:0] stuffer_done_mclk; // output
// Compressor frame synchronization
wire [3:0] vsync_late; // input
assign gpio_in= {48'h0,frst,tmp_debug}; assign gpio_in= {48'h0,frst,tmp_debug};
...@@ -771,6 +798,15 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -771,6 +798,15 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
/* Instance template for module mcntrl393 */ /* Instance template for module mcntrl393 */
mcntrl393 #( mcntrl393 #(
.MCONTR_SENS_BASE('h680),
.MCONTR_SENS_INC('h10),
.MCONTR_CMPRS_BASE('h6c0),
.MCONTR_CMPRS_INC('h10),
.MCONTR_SENS_STATUS_BASE('h28),
.MCONTR_SENS_STATUS_INC('h1),
.MCONTR_CMPRS_STATUS_BASE('h2c),
.MCONTR_CMPRS_STATUS_INC('h1),
.MCONTR_WR_MASK (MCONTR_WR_MASK), .MCONTR_WR_MASK (MCONTR_WR_MASK),
.MCONTR_RD_MASK (MCONTR_RD_MASK), .MCONTR_RD_MASK (MCONTR_RD_MASK),
.MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR), .MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR),
...@@ -900,89 +936,113 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -900,89 +936,113 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.RSEL (RSEL), .RSEL (RSEL),
.WSEL (WSEL) .WSEL (WSEL)
) mcntrl393_i ( ) mcntrl393_i (
.rst_in (axi_rst), // input .rst_in (axi_rst), // input
.clk_in (axi_aclk), // == axird_bram_rclk SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #mcntrl393_i:clk_in to constant 0 .clk_in (axi_aclk), // == axird_bram_rclk SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #mcntrl393_i:clk_in to constant 0
.mclk (mclk), // output .mclk (mclk), // output
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0] .cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input .cmd_stb (cmd_mcontr_stb), // input
.status_ad (status_mcontr_ad[7:0]), // output[7:0] .status_ad (status_mcontr_ad[7:0]), // output[7:0]
.status_rq (status_mcontr_rq), // input request to send status downstream .status_rq (status_mcontr_rq), // input request to send status downstream
.status_start (status_mcontr_start), // Acknowledge of the first status packet byte (address) .status_start (status_mcontr_start), // Acknowledge of the first status packet byte (address)
.axi_clk (axird_bram_rclk), // ==axi_aclk, // input - same?
.axiwr_pre_awaddr (axiwr_pre_awaddr), // input[12:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #mcntrl393_i:axiwr_pre_awaddr[9:0] to constant 0
.axiwr_start_burst (axiwr_start_burst), // input
.axiwr_waddr (axiwr_waddr[BUFFER_DEPTH32-1:0]), // input[9:0]
.axiwr_wen (axiwr_wen), // input
.axiwr_data (axiwr_wdata), // input[31:0]
.axi_clk (axird_bram_rclk), // ==axi_aclk, // input - same? .axird_pre_araddr (axird_pre_araddr), // input[12:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #mcntrl393_i:axird_pre_araddr[9:0] to constant 0 (seems to be unused, not undriven)
.axiwr_pre_awaddr (axiwr_pre_awaddr), // input[12:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #mcntrl393_i:axiwr_pre_awaddr[9:0] to constant 0 .axird_start_burst (axird_start_burst), // input
.axiwr_start_burst (axiwr_start_burst), // input .axird_raddr (axird_raddr[BUFFER_DEPTH32-1:0]), // input[9:0]
.axiwr_waddr (axiwr_waddr[BUFFER_DEPTH32-1:0]), // input[9:0] .axird_ren (axird_ren), // input
.axiwr_wen (axiwr_wen), // input .axird_regen (axird_regen), // input
.axiwr_data (axiwr_wdata), // input[31:0] .axird_rdata (mcntrl_axird_rdata), // output[31:0]
.axird_selected (mcntrl_axird_selected), // output
// sensors interface
.sens_rpage_set (sens_rpage_set), // output[3:0]
.sens_rpage_next (sens_rpage_next), // output[3:0]
.sens_buf_rd (sens_buf_rd), // output[3:0]
.sens_buf_dout (sens_buf_dout), // input[255:0]
// compressor interface
.cmprs_xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // output[3:0]
.cmprs_buf_wpage_nxt (cmprs_buf_wpage_nxt), // output[3:0]
.cmprs_buf_we (cmprs_buf_we), // output[3:0]
.cmprs_buf_din (cmprs_buf_din), // output[255:0]
.cmprs_page_ready (cmprs_page_ready), // output[3:0]
.cmprs_next_page (cmprs_next_page), // input[3:0]
.cmprs_frame_start_dst (cmprs_frame_start_dst), // input[3:0]
.cmprs_line_unfinished_src (cmprs_line_unfinished_src), // output[63:0]
.cmprs_frame_number_src (cmprs_frame_number_src), // output[63:0]
.cmprs_frame_done_src (cmprs_frame_done_src), // output[3:0]
.cmprs_line_unfinished_dst (cmprs_line_unfinished_dst), // output[63:0]
.cmprs_frame_number_dst (cmprs_frame_number_dst), // output[63:0]
.cmprs_frame_done_dst (cmprs_frame_done_dst), // output[3:0]
.cmprs_suspend (cmprs_suspend), // input[3:0]
.axird_pre_araddr (axird_pre_araddr), // input[12:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #mcntrl393_i:axird_pre_araddr[9:0] to constant 0 (seems to be unused, not undriven) // Originally implemented channels, some are just for testing and may be replaced
.axird_start_burst (axird_start_burst), // input .frame_start_chn1 (frame_start_chn1), // input
.axird_raddr (axird_raddr[BUFFER_DEPTH32-1:0]), // input[9:0] .next_page_chn1 (next_page_chn1), // input
.axird_ren (axird_ren), // input .cmd_wrmem_chn1 (cmd_wrmem_chn1), // output
.axird_regen (axird_regen), // input .page_ready_chn1 (page_ready_chn1), // output
.axird_rdata (mcntrl_axird_rdata), // output[31:0] .frame_done_chn1 (frame_done_chn1), // output
.axird_selected (mcntrl_axird_selected), // output .line_unfinished_chn1 (line_unfinished_chn1), // output[15:0]
//TODO: .suspend_chn1 (suspend_chn1), // input
.frame_start_chn1 (frame_start_chn1), // input .xfer_reset_page1_rd (xfer_reset_page1_rd), // output
.next_page_chn1 (next_page_chn1), // input .buf_wpage_nxt_chn1 (buf_wpage_nxt_chn1), // output
.cmd_wrmem_chn1 (cmd_wrmem_chn1), // output .buf_wr_chn1 (buf_wr_chn1), // output
.page_ready_chn1 (page_ready_chn1), // output .buf_wdata_chn1 (buf_wdata_chn1[63:0]), // output[63:0]
.frame_done_chn1 (frame_done_chn1), // output .xfer_reset_page1_wr (xfer_reset_page1_wr), // output
.line_unfinished_chn1 (line_unfinished_chn1), // output[15:0] .rpage_nxt_chn1 (rpage_nxt_chn1), // output
.suspend_chn1 (suspend_chn1), // input .buf_rd_chn1 (buf_rd_chn1), // output
.xfer_reset_page1_rd (xfer_reset_page1_rd), // output .buf_rdata_chn1 (buf_rdata_chn1[63:0]), // input[63:0]
.buf_wpage_nxt_chn1 (buf_wpage_nxt_chn1), // output
.buf_wr_chn1 (buf_wr_chn1), // output
.buf_wdata_chn1 (buf_wdata_chn1[63:0]), // output[63:0]
.xfer_reset_page1_wr (xfer_reset_page1_wr), // output
.rpage_nxt_chn1 (rpage_nxt_chn1), // output
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_rdata_chn1 (buf_rdata_chn1[63:0]), // input[63:0]
.frame_start_chn2 (frame_start_chn2), // input .frame_start_chn2 (frame_start_chn2), // input
.next_page_chn2 (next_page_chn2), // input .next_page_chn2 (next_page_chn2), // input
.page_ready_chn2 (page_ready_chn2), // output .page_ready_chn2 (page_ready_chn2), // output
.frame_done_chn2 (frame_done_chn2), // output .frame_done_chn2 (frame_done_chn2), // output
.line_unfinished_chn2 (line_unfinished_chn2), // output[15:0] .line_unfinished_chn2 (line_unfinished_chn2), // output[15:0]
.frame_number_chn2 (frame_number_chn2), // output[15:0] .frame_number_chn2 (frame_number_chn2), // output[15:0]
.suspend_chn2 (suspend_chn2), // input .suspend_chn2 (suspend_chn2), // input
.frame_start_chn3 (frame_start_chn3), // input .frame_start_chn3 (frame_start_chn3), // input
.next_page_chn3 (next_page_chn3), // input .next_page_chn3 (next_page_chn3), // input
.page_ready_chn3 (page_ready_chn3), // output .page_ready_chn3 (page_ready_chn3), // output
.frame_done_chn3 (frame_done_chn3), // output .frame_done_chn3 (frame_done_chn3), // output
.line_unfinished_chn3 (line_unfinished_chn3), // output[15:0] .line_unfinished_chn3 (line_unfinished_chn3), // output[15:0]
.frame_number_chn3 (frame_number_chn3), // output[15:0] .frame_number_chn3 (frame_number_chn3), // output[15:0]
.suspend_chn3 (suspend_chn3), // input .suspend_chn3 (suspend_chn3), // input
.frame_start_chn4 (frame_start_chn4), // input .frame_start_chn4 (frame_start_chn4), // input
.next_page_chn4 (next_page_chn4), // input .next_page_chn4 (next_page_chn4), // input
.page_ready_chn4 (page_ready_chn4), // output .page_ready_chn4 (page_ready_chn4), // output
.frame_done_chn4 (frame_done_chn4), // output .frame_done_chn4 (frame_done_chn4), // output
.line_unfinished_chn4 (line_unfinished_chn4), // output[15:0] .line_unfinished_chn4 (line_unfinished_chn4), // output[15:0]
.frame_number_chn4 (frame_number_chn4), // output[15:0] .frame_number_chn4 (frame_number_chn4), // output[15:0]
.suspend_chn4 (suspend_chn4), // input .suspend_chn4 (suspend_chn4), // input
.SDRST (SDRST), // output .SDRST (SDRST), // output
.SDCLK (SDCLK), // output .SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output .SDNCLK (SDNCLK), // output
.SDA (SDA), // output[14:0] .SDA (SDA), // output[14:0]
.SDBA (SDBA), // output[2:0] .SDBA (SDBA), // output[2:0]
.SDWE (SDWE), // output .SDWE (SDWE), // output
.SDRAS (SDRAS), // output .SDRAS (SDRAS), // output
.SDCAS (SDCAS), // output .SDCAS (SDCAS), // output
.SDCKE (SDCKE), // output .SDCKE (SDCKE), // output
.SDODT (SDODT), // output .SDODT (SDODT), // output
.SDD (SDD), // inout[15:0] .SDD (SDD), // inout[15:0]
.SDDML (SDDML), // output .SDDML (SDDML), // output
.DQSL (DQSL), // inout .DQSL (DQSL), // inout
.NDQSL (NDQSL), // inout .NDQSL (NDQSL), // inout
.SDDMU (SDDMU), // output .SDDMU (SDDMU), // output
.DQSU (DQSU), // inout .DQSU (DQSU), // inout
.NDQSU (NDQSU), // inout .NDQSU (NDQSU), // inout
.tmp_debug (tmp_debug) // output[11:0] .tmp_debug (tmp_debug) // output[11:0]
); );
// AFI0 (AXI_HP0) signals // AFI0 (AXI_HP0) signals
wire [31:0] afi0_awaddr; // output[31:0] wire [31:0] afi0_awaddr; // output[31:0]
...@@ -1254,8 +1314,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -1254,8 +1314,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD) .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
) sensors393_i ( ) sensors393_i (
.rst (axi_rst), // input .rst (axi_rst), // input
.pclk (), // input .pclk (pclk), // input
.pclk2x (), // input .pclk2x (pclk2x), // input
.ref_clk (ref_clk), // input .ref_clk (ref_clk), // input
.dly_rst (axi_rst), // input .dly_rst (axi_rst), // input
.mclk (mclk), // input .mclk (mclk), // input
...@@ -1300,25 +1360,10 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -1300,25 +1360,10 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.sns4_ctl (sns4_ctl), // inout .sns4_ctl (sns4_ctl), // inout
.sns4_pg (sns4_pg), // inout .sns4_pg (sns4_pg), // inout
.rpage_set0 (rpage_set0), // input .rpage_set (sens_rpage_set), // input
.rpage_next0 (rpage_next0), // input .rpage_next (sens_rpage_next), // input
.buf_rd0 (buf_rd0), // input .buf_rd (sens_buf_rd), // input
.buf_dout0 (buf_dout0), // output[63:0] .buf_dout (sens_buf_dout), // output[63:0]
.rpage_set1 (rpage_set1), // input
.rpage_next1 (rpage_next1), // input
.buf_rd1 (buf_rd1), // input
.buf_dout1 (buf_dout1), // output[63:0]
.rpage_set2 (rpage_set2), // input
.rpage_next2 (rpage_next2), // input
.buf_rd2 (buf_rd2), // input
.buf_dout2 (buf_dout2), // output[63:0]
.rpage_set3 (rpage_set3), // input
.rpage_next3 (rpage_next3), // input
.buf_rd3 (buf_rd3), // input
.buf_dout3 (buf_dout3), // output[63:0]
.trigger_mode (trigger_mode), // input .trigger_mode (trigger_mode), // input
.trig_in (trig_in), // input[3:0] .trig_in (trig_in), // input[3:0]
...@@ -1357,6 +1402,229 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -1357,6 +1402,229 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.saxi_bresp (saxi0_bresp) // input[1:0] .saxi_bresp (saxi0_bresp) // input[1:0]
); );
// AFI1 (AXI_HP1) signals - write channels only
wire [31:0] afi1_awaddr; // output[31:0]
wire afi1_awvalid; // output
wire afi1_awready; // input
wire [ 5:0] afi1_awid; // output[5:0]
wire [ 1:0] afi1_awlock; // output[1:0]
wire [ 3:0] afi1_awcache; // output[3:0]
wire [ 2:0] afi1_awprot; // output[2:0]
wire [ 3:0] afi1_awlen; // output[3:0]
wire [ 2:0] afi1_awsize; // output[2:0]
wire [ 1:0] afi1_awburst; // output[1:0]
wire [ 3:0] afi1_awqos; // output[3:0]
wire [63:0] afi1_wdata; // output[63:0]
wire afi1_wvalid; // output
wire afi1_wready; // input
wire [ 5:0] afi1_wid; // output[5:0]
wire afi1_wlast; // output
wire [ 7:0] afi1_wstrb; // output[7:0]
wire afi1_bvalid; // input
wire afi1_bready; // output
wire [ 5:0] afi1_bid; // input[5:0]
wire [ 1:0] afi1_bresp; // input[1:0]
wire [ 7:0] afi1_wcount; // input[7:0]
wire [ 5:0] afi1_wacount; // input[5:0]
wire afi1_wrissuecap1en; // output
// AFI2 (AXI_HP2) signals - write channels only - used only if CMPRS_NUM_AFI_CHN == 2
wire [31:0] afi2_awaddr; // output[31:0]
wire afi2_awvalid; // output
wire afi2_awready; // input
wire [ 5:0] afi2_awid; // output[5:0]
wire [ 1:0] afi2_awlock; // output[1:0]
wire [ 3:0] afi2_awcache; // output[3:0]
wire [ 2:0] afi2_awprot; // output[2:0]
wire [ 3:0] afi2_awlen; // output[3:0]
wire [ 2:0] afi2_awsize; // output[2:0]
wire [ 1:0] afi2_awburst; // output[1:0]
wire [ 3:0] afi2_awqos; // output[3:0]
wire [63:0] afi2_wdata; // output[63:0]
wire afi2_wvalid; // output
wire afi2_wready; // input
wire [ 5:0] afi2_wid; // output[5:0]
wire afi2_wlast; // output
wire [ 7:0] afi2_wstrb; // output[7:0]
wire afi2_bvalid; // input
wire afi2_bready; // output
wire [ 5:0] afi2_bid; // input[5:0]
wire [ 1:0] afi2_bresp; // input[1:0]
wire [ 7:0] afi2_wcount; // input[7:0]
wire [ 5:0] afi2_wacount; // input[5:0]
wire afi2_wrissuecap1en; // output
compressor393 #(
.CMPRS_NUM_AFI_CHN (CMPRS_NUM_AFI_CHN),
.CMPRS_GROUP_ADDR (CMPRS_GROUP_ADDR),
.CMPRS_BASE_INC (CMPRS_BASE_INC),
.CMPRS_AFIMUX_RADDR0 (CMPRS_AFIMUX_RADDR0),
.CMPRS_AFIMUX_RADDR1 (CMPRS_AFIMUX_RADDR1),
.CMPRS_AFIMUX_MASK (CMPRS_AFIMUX_MASK),
.CMPRS_STATUS_REG_BASE (CMPRS_STATUS_REG_BASE),
.CMPRS_HIFREQ_REG_BASE (CMPRS_HIFREQ_REG_BASE),
.CMPRS_AFIMUX_REG_ADDR0 (CMPRS_AFIMUX_REG_ADDR0),
.CMPRS_AFIMUX_REG_ADDR1 (CMPRS_AFIMUX_REG_ADDR1),
.CMPRS_STATUS_REG_INC (CMPRS_STATUS_REG_INC),
.CMPRS_HIFREQ_REG_INC (CMPRS_HIFREQ_REG_INC),
.CMPRS_MASK (CMPRS_MASK),
.CMPRS_CONTROL_REG (CMPRS_CONTROL_REG),
.CMPRS_STATUS_CNTRL (CMPRS_STATUS_CNTRL),
.CMPRS_FORMAT (CMPRS_FORMAT),
.CMPRS_COLOR_SATURATION (CMPRS_COLOR_SATURATION),
.CMPRS_CORING_MODE (CMPRS_CORING_MODE),
.CMPRS_TABLES (CMPRS_TABLES),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.LAST_FRAME_BITS (LAST_FRAME_BITS),
.CMPRS_CBIT_RUN (CMPRS_CBIT_RUN),
.CMPRS_CBIT_RUN_BITS (CMPRS_CBIT_RUN_BITS),
.CMPRS_CBIT_QBANK (CMPRS_CBIT_QBANK),
.CMPRS_CBIT_QBANK_BITS (CMPRS_CBIT_QBANK_BITS),
.CMPRS_CBIT_DCSUB (CMPRS_CBIT_DCSUB),
.CMPRS_CBIT_DCSUB_BITS (CMPRS_CBIT_DCSUB_BITS),
.CMPRS_CBIT_CMODE (CMPRS_CBIT_CMODE),
.CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS),
.CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES),
.CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS),
.CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER),
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
.CMPRS_CBIT_FOCUS_BITS (CMPRS_CBIT_FOCUS_BITS),
.CMPRS_CBIT_RUN_RST (CMPRS_CBIT_RUN_RST),
.CMPRS_CBIT_RUN_STANDALONE (CMPRS_CBIT_RUN_STANDALONE),
.CMPRS_CBIT_RUN_ENABLE (CMPRS_CBIT_RUN_ENABLE),
.CMPRS_CBIT_CMODE_JPEG18 (CMPRS_CBIT_CMODE_JPEG18),
.CMPRS_CBIT_CMODE_MONO6 (CMPRS_CBIT_CMODE_MONO6),
.CMPRS_CBIT_CMODE_JP46 (CMPRS_CBIT_CMODE_JP46),
.CMPRS_CBIT_CMODE_JP46DC (CMPRS_CBIT_CMODE_JP46DC),
.CMPRS_CBIT_CMODE_JPEG20 (CMPRS_CBIT_CMODE_JPEG20),
.CMPRS_CBIT_CMODE_JP4 (CMPRS_CBIT_CMODE_JP4),
.CMPRS_CBIT_CMODE_JP4DC (CMPRS_CBIT_CMODE_JP4DC),
.CMPRS_CBIT_CMODE_JP4DIFF (CMPRS_CBIT_CMODE_JP4DIFF),
.CMPRS_CBIT_CMODE_JP4DIFFHDR (CMPRS_CBIT_CMODE_JP4DIFFHDR),
.CMPRS_CBIT_CMODE_JP4DIFFDIV2 (CMPRS_CBIT_CMODE_JP4DIFFDIV2),
.CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 (CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2),
.CMPRS_CBIT_CMODE_MONO1 (CMPRS_CBIT_CMODE_MONO1),
.CMPRS_CBIT_CMODE_MONO4 (CMPRS_CBIT_CMODE_MONO4),
.CMPRS_CBIT_FRAMES_SINGLE (CMPRS_CBIT_FRAMES_SINGLE),
.CMPRS_COLOR18 (CMPRS_COLOR18),
.CMPRS_COLOR20 (CMPRS_COLOR20),
.CMPRS_MONO16 (CMPRS_MONO16),
.CMPRS_JP4 (CMPRS_JP4),
.CMPRS_JP4DIFF (CMPRS_JP4DIFF),
.CMPRS_MONO8 (CMPRS_MONO8),
.CMPRS_FRMT_MBCM1 (CMPRS_FRMT_MBCM1),
.CMPRS_FRMT_MBCM1_BITS (CMPRS_FRMT_MBCM1_BITS),
.CMPRS_FRMT_MBRM1 (CMPRS_FRMT_MBRM1),
.CMPRS_FRMT_MBRM1_BITS (CMPRS_FRMT_MBRM1_BITS),
.CMPRS_FRMT_LMARG (CMPRS_FRMT_LMARG),
.CMPRS_FRMT_LMARG_BITS (CMPRS_FRMT_LMARG_BITS),
.CMPRS_CSAT_CB (CMPRS_CSAT_CB),
.CMPRS_CSAT_CB_BITS (CMPRS_CSAT_CB_BITS),
.CMPRS_CSAT_CR (CMPRS_CSAT_CR),
.CMPRS_CSAT_CR_BITS (CMPRS_CSAT_CR_BITS),
.CMPRS_CORING_BITS (CMPRS_CORING_BITS),
.CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS),
.CMPRS_TIMEOUT (CMPRS_TIMEOUT),
.CMPRS_AFIMUX_EN (CMPRS_AFIMUX_EN),
.CMPRS_AFIMUX_RST (CMPRS_AFIMUX_RST),
.CMPRS_AFIMUX_MODE (CMPRS_AFIMUX_MODE),
.CMPRS_AFIMUX_STATUS_CNTRL (CMPRS_AFIMUX_STATUS_CNTRL),
.CMPRS_AFIMUX_SA_LEN (CMPRS_AFIMUX_SA_LEN),
.CMPRS_AFIMUX_WIDTH (CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) compressor393_i (
.rst (axi_rst), // input
.xclk (xclk), // input
.xclk2x (xclk2x), // input
.mclk (mclk), // input
.cmd_ad (cmd_compressor_ad), // input[7:0]
.cmd_stb (cmd_compressor_stb), // input
.status_ad (status_compressor_ad), // output[7:0]
.status_rq (status_compressor_rq), // output
.status_start (status_compressor_start), // input
.xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // input[3:0]
.buf_wpage_nxt (cmprs_buf_wpage_nxt), // input[3:0]
.buf_we (cmprs_buf_we), // input[3:0]
.buf_din (cmprs_buf_din), // input[255:0]
.page_ready (cmprs_page_ready), // input[3:0]
.next_page (cmprs_next_page), // output[3:0]
.frame_start_dst (cmprs_frame_start_dst), // output[3:0]
.line_unfinished_src (cmprs_line_unfinished_src), // input[63:0]
.frame_number_src (cmprs_frame_number_src), // input[63:0]
.frame_done_src (cmprs_frame_done_src), // input[3:0]
.line_unfinished_dst (cmprs_line_unfinished_dst), // input[63:0]
.frame_number_dst (cmprs_frame_number_dst), // input[63:0]
.frame_done_dst (cmprs_frame_done_dst), // input[3:0]
.suspend (cmprs_suspend), // output[3:0]
.ts_pre_stb (ts_pre_stb), // input[3:0]
.ts_data (ts_data), // input[31:0]
.eof_written_mclk (eof_written_mclk), // output[3:0]
.stuffer_done_mclk (stuffer_done_mclk), // output[3:0]
.vsync_late (vsync_late), // input[3:0]
.hclk (hclk), // input
.afi0_awaddr (afi1_awaddr), // output[31:0]
.afi0_awvalid (afi1_awvalid), // output
.afi0_awready (afi1_awready), // input
.afi0_awid (afi1_awid), // output[5:0]
.afi0_awlock (afi1_awlock), // output[1:0]
.afi0_awcache (afi1_awcache), // output[3:0]
.afi0_awprot (afi1_awprot), // output[2:0]
.afi0_awlen (afi1_awlen), // output[3:0]
.afi0_awsize (afi1_awsize), // output[2:0]
.afi0_awburst (afi1_awburst), // output[1:0]
.afi0_awqos (afi1_awqos), // output[3:0]
.afi0_wdata (afi1_wdata), // output[63:0]
.afi0_wvalid (afi1_wvalid), // output
.afi0_wready (afi1_wready), // input
.afi0_wid (afi1_wid), // output[5:0]
.afi0_wlast (afi1_wlast), // output
.afi0_wstrb (afi1_wstrb), // output[7:0]
.afi0_bvalid (afi1_bvalid), // input
.afi0_bready (afi1_bready), // output
.afi0_bid (afi1_bid), // input[5:0]
.afi0_bresp (afi1_bresp), // input[1:0]
.afi0_wcount (afi1_wcount), // input[7:0]
.afi0_wacount (afi1_wacount), // input[5:0]
.afi0_wrissuecap1en (afi1_wrissuecap1en), // output
.afi1_awaddr (afi2_awaddr), // output[31:0]
.afi1_awvalid (afi2_awvalid), // output
.afi1_awready (afi2_awready), // input
.afi1_awid (afi2_awid), // output[5:0]
.afi1_awlock (afi2_awlock), // output[1:0]
.afi1_awcache (afi2_awcache), // output[3:0]
.afi1_awprot (afi2_awprot), // output[2:0]
.afi1_awlen (afi2_awlen), // output[3:0]
.afi1_awsize (afi2_awsize), // output[2:0]
.afi1_awburst (afi2_awburst), // output[1:0]
.afi1_awqos (afi2_awqos), // output[3:0]
.afi1_wdata (afi2_wdata), // output[63:0]
.afi1_wvalid (afi2_wvalid), // output
.afi1_wready (afi2_wready), // input
.afi1_wid (afi2_wid), // output[5:0]
.afi1_wlast (afi2_wlast), // output
.afi1_wstrb (afi2_wstrb), // output[7:0]
.afi1_bvalid (afi2_bvalid), // input
.afi1_bready (afi2_bready), // output
.afi1_bid (afi2_bid), // input[5:0]
.afi1_bresp (afi2_bresp), // input[1:0]
.afi1_wcount (afi2_wcount), // input[7:0]
.afi1_wacount (afi2_wacount), // input[5:0]
.afi1_wrissuecap1en (afi2_wrissuecap1en) // output
);
axibram_write #( axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS) .ADDRESS_BITS(AXI_WR_ADDR_BITS)
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal. ) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
...@@ -1949,9 +2217,9 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0]; ...@@ -1949,9 +2217,9 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
// AXI PS Slave HP1 // AXI PS Slave HP1
// AXI PS Slave 1: Clock, Reset // AXI PS Slave 1: Clock, Reset
.SAXIHP1ACLK(), // AXI PS Slave HP1 Clock , input .SAXIHP1ACLK (hclk), // AXI PS Slave HP1 Clock , input
.SAXIHP1ARESETN(), // AXI PS Slave HP1 Reset, output .SAXIHP1ARESETN(), // AXI PS Slave HP1 Reset, output
// AXI PS Slave HP1: Read Address // AXI PS Slave HP1: Read Address - unused
.SAXIHP1ARADDR(), // AXI PS Slave HP1 ARADDR[31:0], input .SAXIHP1ARADDR(), // AXI PS Slave HP1 ARADDR[31:0], input
.SAXIHP1ARVALID(), // AXI PS Slave HP1 ARVALID, input .SAXIHP1ARVALID(), // AXI PS Slave HP1 ARVALID, input
.SAXIHP1ARREADY(), // AXI PS Slave HP1 ARREADY, output .SAXIHP1ARREADY(), // AXI PS Slave HP1 ARREADY, output
...@@ -1974,38 +2242,38 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0]; ...@@ -1974,38 +2242,38 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
.SAXIHP1RACOUNT(), // AXI PS Slave HP1 RACOUNT[2:0], output .SAXIHP1RACOUNT(), // AXI PS Slave HP1 RACOUNT[2:0], output
.SAXIHP1RDISSUECAP1EN(), // AXI PS Slave HP1 RDISSUECAP1EN, input .SAXIHP1RDISSUECAP1EN(), // AXI PS Slave HP1 RDISSUECAP1EN, input
// AXI PS Slave HP1: Write Address // AXI PS Slave HP1: Write Address
.SAXIHP1AWADDR(), // AXI PS Slave HP1 AWADDR[31:0], input .SAXIHP1AWADDR (afi1_awaddr), // AXI PS Slave HP1 AWADDR[31:0], input
.SAXIHP1AWVALID(), // AXI PS Slave HP1 AWVALID, input .SAXIHP1AWVALID (afi1_awvalid), // AXI PS Slave HP1 AWVALID, input
.SAXIHP1AWREADY(), // AXI PS Slave HP1 AWREADY, output .SAXIHP1AWREADY (afi1_awready), // AXI PS Slave HP1 AWREADY, output
.SAXIHP1AWID(), // AXI PS Slave HP1 AWID[5:0], input .SAXIHP1AWID (afi1_awid), // AXI PS Slave HP1 AWID[5:0], input
.SAXIHP1AWLOCK(), // AXI PS Slave HP1 AWLOCK[1:0], input .SAXIHP1AWLOCK (afi1_awlock), // AXI PS Slave HP1 AWLOCK[1:0], input
.SAXIHP1AWCACHE(), // AXI PS Slave HP1 AWCACHE[3:0], input .SAXIHP1AWCACHE (afi1_awcache), // AXI PS Slave HP1 AWCACHE[3:0], input
.SAXIHP1AWPROT(), // AXI PS Slave HP1 AWPROT[2:0], input .SAXIHP1AWPROT (afi1_awprot), // AXI PS Slave HP1 AWPROT[2:0], input
.SAXIHP1AWLEN(), // AXI PS Slave HP1 AWLEN[3:0], input .SAXIHP1AWLEN (afi1_awlen), // AXI PS Slave HP1 AWLEN[3:0], input
.SAXIHP1AWSIZE(), // AXI PS Slave HP1 AWSIZE[1:0], input .SAXIHP1AWSIZE (afi1_awsize), // AXI PS Slave HP1 AWSIZE[1:0], input
.SAXIHP1AWBURST(), // AXI PS Slave HP1 AWBURST[1:0], input .SAXIHP1AWBURST (afi1_awburst), // AXI PS Slave HP1 AWBURST[1:0], input
.SAXIHP1AWQOS(), // AXI PS Slave HP1 AWQOS[3:0], input .SAXIHP1AWQOS (afi1_awqos), // AXI PS Slave HP1 AWQOS[3:0], input
// AXI PS Slave HP1: Write Data // AXI PS Slave HP1: Write Data
.SAXIHP1WDATA(), // AXI PS Slave HP1 WDATA[63:0], input .SAXIHP1WDATA (afi1_wdata), // AXI PS Slave HP1 WDATA[63:0], input
.SAXIHP1WVALID(), // AXI PS Slave HP1 WVALID, input .SAXIHP1WVALID (afi1_wvalid), // AXI PS Slave HP1 WVALID, input
.SAXIHP1WREADY(), // AXI PS Slave HP1 WREADY, output .SAXIHP1WREADY (afi1_wready), // AXI PS Slave HP1 WREADY, output
.SAXIHP1WID(), // AXI PS Slave HP1 WID[5:0], input .SAXIHP1WID (afi1_wid), // AXI PS Slave HP1 WID[5:0], input
.SAXIHP1WLAST(), // AXI PS Slave HP1 WLAST, input .SAXIHP1WLAST (afi1_wlast), // AXI PS Slave HP1 WLAST, input
.SAXIHP1WSTRB(), // AXI PS Slave HP1 WSTRB[7:0], input .SAXIHP1WSTRB (afi1_wstrb), // AXI PS Slave HP1 WSTRB[7:0], input
.SAXIHP1WCOUNT(), // AXI PS Slave HP1 WCOUNT[7:0], output .SAXIHP1WCOUNT (afi1_wcount), // AXI PS Slave HP1 WCOUNT[7:0], output
.SAXIHP1WACOUNT(), // AXI PS Slave HP1 WACOUNT[5:0], output .SAXIHP1WACOUNT (afi1_wacount), // AXI PS Slave HP1 WACOUNT[5:0], output
.SAXIHP1WRISSUECAP1EN(), // AXI PS Slave HP1 WRISSUECAP1EN, input .SAXIHP1WRISSUECAP1EN (afi1_wrissuecap1en), // AXI PS Slave HP1 WRISSUECAP1EN, input
// AXI PS Slave HP1: Write Responce // AXI PS Slave HP1: Write Responce
.SAXIHP1BVALID(), // AXI PS Slave HP1 BVALID, output .SAXIHP1BVALID (afi1_bvalid), // AXI PS Slave HP1 BVALID, output
.SAXIHP1BREADY(), // AXI PS Slave HP1 BREADY, input .SAXIHP1BREADY (afi1_bready), // AXI PS Slave HP1 BREADY, input
.SAXIHP1BID(), // AXI PS Slave HP1 BID[5:0], output .SAXIHP1BID (afi1_bid), // AXI PS Slave HP1 BID[5:0], output
.SAXIHP1BRESP(), // AXI PS Slave HP1 BRESP[1:0], output .SAXIHP1BRESP (afi1_bresp), // AXI PS Slave HP1 BRESP[1:0], output
// AXI PS Slave HP2 // AXI PS Slave HP2
// AXI PS Slave HP2: Clock, Reset // AXI PS Slave HP2: Clock, Reset
.SAXIHP2ACLK(), // AXI PS Slave HP2 Clock , input .SAXIHP2ACLK(), // AXI PS Slave HP2 Clock , input
.SAXIHP2ARESETN(), // AXI PS Slave HP2 Reset, output .SAXIHP2ARESETN(), // AXI PS Slave HP2 Reset, output
// AXI PS Slave HP2: Read Address // AXI PS Slave HP2: Read Address - not used
.SAXIHP2ARADDR(), // AXI PS Slave HP2 ARADDR[31:0], input .SAXIHP2ARADDR(), // AXI PS Slave HP2 ARADDR[31:0], input
.SAXIHP2ARVALID(), // AXI PS Slave HP2 ARVALID, input .SAXIHP2ARVALID(), // AXI PS Slave HP2 ARVALID, input
.SAXIHP2ARREADY(), // AXI PS Slave HP2 ARREADY, output .SAXIHP2ARREADY(), // AXI PS Slave HP2 ARREADY, output
...@@ -2017,7 +2285,7 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0]; ...@@ -2017,7 +2285,7 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
.SAXIHP2ARSIZE(), // AXI PS Slave HP2 ARSIZE[2:0], input .SAXIHP2ARSIZE(), // AXI PS Slave HP2 ARSIZE[2:0], input
.SAXIHP2ARBURST(), // AXI PS Slave HP2 ARBURST[1:0], input .SAXIHP2ARBURST(), // AXI PS Slave HP2 ARBURST[1:0], input
.SAXIHP2ARQOS(), // AXI PS Slave HP2 ARQOS[3:0], input .SAXIHP2ARQOS(), // AXI PS Slave HP2 ARQOS[3:0], input
// AXI PS Slave HP2: Read Data // AXI PS Slave HP2: Read Data - not used
.SAXIHP2RDATA(), // AXI PS Slave HP2 RDATA[63:0], output .SAXIHP2RDATA(), // AXI PS Slave HP2 RDATA[63:0], output
.SAXIHP2RVALID(), // AXI PS Slave HP2 RVALID, output .SAXIHP2RVALID(), // AXI PS Slave HP2 RVALID, output
.SAXIHP2RREADY(), // AXI PS Slave HP2 RREADY, input .SAXIHP2RREADY(), // AXI PS Slave HP2 RREADY, input
...@@ -2028,32 +2296,32 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0]; ...@@ -2028,32 +2296,32 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
.SAXIHP2RACOUNT(), // AXI PS Slave HP2 RACOUNT[2:0], output .SAXIHP2RACOUNT(), // AXI PS Slave HP2 RACOUNT[2:0], output
.SAXIHP2RDISSUECAP1EN(), // AXI PS Slave HP2 RDISSUECAP1EN, input .SAXIHP2RDISSUECAP1EN(), // AXI PS Slave HP2 RDISSUECAP1EN, input
// AXI PS Slave HP2: Write Address // AXI PS Slave HP2: Write Address
.SAXIHP2AWADDR(), // AXI PS Slave HP2 AWADDR[31:0], input .SAXIHP2AWADDR (afi2_awaddr), // AXI PS Slave HP2 AWADDR[31:0], input
.SAXIHP2AWVALID(), // AXI PS Slave HP2 AWVALID, input .SAXIHP2AWVALID (afi2_awvalid), // AXI PS Slave HP2 AWVALID, input
.SAXIHP2AWREADY(), // AXI PS Slave HP2 AWREADY, output .SAXIHP2AWREADY (afi2_awready), // AXI PS Slave HP2 AWREADY, output
.SAXIHP2AWID(), // AXI PS Slave HP2 AWID[5:0], input .SAXIHP2AWID (afi2_awid), // AXI PS Slave HP2 AWID[5:0], input
.SAXIHP2AWLOCK(), // AXI PS Slave HP2 AWLOCK[1:0], input .SAXIHP2AWLOCK (afi2_awlock), // AXI PS Slave HP2 AWLOCK[1:0], input
.SAXIHP2AWCACHE(), // AXI PS Slave HP2 AWCACHE[3:0], input .SAXIHP2AWCACHE (afi2_awcache), // AXI PS Slave HP2 AWCACHE[3:0], input
.SAXIHP2AWPROT(), // AXI PS Slave HP2 AWPROT[2:0], input .SAXIHP2AWPROT (afi2_awprot), // AXI PS Slave HP2 AWPROT[2:0], input
.SAXIHP2AWLEN(), // AXI PS Slave HP2 AWLEN[3:0], input .SAXIHP2AWLEN (afi2_awlen), // AXI PS Slave HP2 AWLEN[3:0], input
.SAXIHP2AWSIZE(), // AXI PS Slave HP2 AWSIZE[1:0], input .SAXIHP2AWSIZE (afi2_awsize), // AXI PS Slave HP2 AWSIZE[1:0], input
.SAXIHP2AWBURST(), // AXI PS Slave HP2 AWBURST[1:0], input .SAXIHP2AWBURST (afi2_awburst), // AXI PS Slave HP2 AWBURST[1:0], input
.SAXIHP2AWQOS(), // AXI PS Slave HP2 AWQOS[3:0], input .SAXIHP2AWQOS (afi2_awqos), // AXI PS Slave HP2 AWQOS[3:0], input
// AXI PS Slave HP2: Write Data // AXI PS Slave HP2: Write Data
.SAXIHP2WDATA(), // AXI PS Slave HP2 WDATA[63:0], input .SAXIHP2WDATA (afi2_wdata), // AXI PS Slave HP2 WDATA[63:0], input
.SAXIHP2WVALID(), // AXI PS Slave HP2 WVALID, input .SAXIHP2WVALID (afi2_wvalid), // AXI PS Slave HP2 WVALID, input
.SAXIHP2WREADY(), // AXI PS Slave HP2 WREADY, output .SAXIHP2WREADY (afi2_wready), // AXI PS Slave HP2 WREADY, output
.SAXIHP2WID(), // AXI PS Slave HP2 WID[5:0], input .SAXIHP2WID (afi2_wid), // AXI PS Slave HP2 WID[5:0], input
.SAXIHP2WLAST(), // AXI PS Slave HP2 WLAST, input .SAXIHP2WLAST (afi2_wlast), // AXI PS Slave HP2 WLAST, input
.SAXIHP2WSTRB(), // AXI PS Slave HP2 WSTRB[7:0], input .SAXIHP2WSTRB (afi2_wstrb), // AXI PS Slave HP2 WSTRB[7:0], input
.SAXIHP2WCOUNT(), // AXI PS Slave HP2 WCOUNT[7:0], output .SAXIHP2WCOUNT (afi2_wcount), // AXI PS Slave HP2 WCOUNT[7:0], output
.SAXIHP2WACOUNT(), // AXI PS Slave HP2 WACOUNT[5:0], output .SAXIHP2WACOUNT (afi2_wacount), // AXI PS Slave HP2 WACOUNT[5:0], output
.SAXIHP2WRISSUECAP1EN(), // AXI PS Slave HP2 WRISSUECAP1EN, input .SAXIHP2WRISSUECAP1EN (afi2_wrissuecap1en), // AXI PS Slave HP2 WRISSUECAP1EN, input
// AXI PS Slave HP2: Write Responce // AXI PS Slave HP2: Write Responce
.SAXIHP2BVALID(), // AXI PS Slave HP2 BVALID, output .SAXIHP2BVALID (afi2_bvalid), // AXI PS Slave HP2 BVALID, output
.SAXIHP2BREADY(), // AXI PS Slave HP2 BREADY, input .SAXIHP2BREADY (afi2_bready), // AXI PS Slave HP2 BREADY, input
.SAXIHP2BID(), // AXI PS Slave HP2 BID[5:0], output .SAXIHP2BID (afi2_bid), // AXI PS Slave HP2 BID[5:0], output
.SAXIHP2BRESP(), // AXI PS Slave HP2 BRESP[1:0], output .SAXIHP2BRESP (afi2_bresp), // AXI PS Slave HP2 BRESP[1:0], output
// AXI PS Slave HP3 // AXI PS Slave HP3
// AXI PS Slave HP3: Clock, Reset // AXI PS Slave HP3: Clock, Reset
......
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