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x393
Commit 28b974c3 authored by Andrey Filippov's avatar Andrey Filippov
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continue on C exporting

parent fcd19b51
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Showing with 459 additions and 36 deletions
includes/x393_parameters.vh
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......@@ -85,7 +85,7 @@
// 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
// 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
// 0x1034..1037 - reserved
parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // set pre-programmed delays
parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // disable/enable memory controller
parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs
//0x1040..107f - 16-bit data
// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
......
py393/x393_export_c.py
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py393/x393_pio_sequences.py
View file @ 28b974c3
......@@ -822,7 +822,8 @@ class X393PIOSequences(object):
self.x393_axi_tasks.write_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_REFRESH_PERIOD, t_refi)
# enable refresh - should it be done here?
if en_refresh:
self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + 1, 0)
# self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + 1, 0)
self.x393_axi_tasks.write_control_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + 1, 0)
def set_mrs(self, # will also calibrate ZQ
......
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