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Commit 27a6599b authored by Andrey Filippov's avatar Andrey Filippov
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working on hardware testing, added utility functions to load bitstream and use GPIO for debugging

parent fad107cb
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.project
View file @ 27a6599b
......@@ -62,77 +62,77 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150228213748063.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150311172942225.log</location>
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<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150228213748063.log</location>
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</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150228213748063.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150311172942225.log</location>
</link>
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<name>vivado_logs/VivadoOptPower.log</name>
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<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150228213748063.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150311172942225.log</location>
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<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150228213748063.log</location>
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<name>vivado_logs/VivadoRoute.log</name>
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<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150228213748063.log</location>
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<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150311172804030.log</location>
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<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150311172942225.dcp</location>
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<name>vivado_state/x393-place.dcp</name>
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<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150228213503140.dcp</location>
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</projectDescription>
includes/x393_localparams.vh
View file @ 27a6599b
......@@ -19,6 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// S uppressWarnings VEditor
localparam [1:0] DEFAULT_STATUS_MODE = 3; // auto status on change, increase sequence number
localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080
localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090
localparam LD_DLY_LANE1_ODELAY = DLY_LD+'h20; // 0x10a0
......@@ -26,8 +27,93 @@
localparam LD_DLY_CMDA = DLY_LD+'h40; // 0x10c0
localparam LD_DLY_PHASE = DLY_LD+'h60; // 0x10e0
localparam DLY_SET = MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020
// different sets of settings for the functional simulation and the actual hardware
/*
if use200Mhz:
DLY_LANE0_DQS_WLV_IDELAY = 0xb0 # idelay dqs
DLY_LANE1_DQS_WLV_IDELAY = 0xb0 # idelay dqs
DLY_LANE0_ODELAY= [0x98,0x4c,0x94,0x94,0x98,0x9c,0x92,0x99,0x98,0x94] # odelay dqm, odelay ddqs, odelay dq[7:0]
`ifdef use200Mhz
DLY_LANE0_IDELAY= [0x40,0x13,0x14,0x14,0x1c,0x13,0x14,0x13,0x1a] # idelay dqs, idelay dq[7:0
DLY_LANE1_ODELAY= [0x98,0x4c,0x98,0x98,0x98,0x9b,0x99,0xa8,0x9c,0x98] # odelay dqm, odelay ddqs, odelay dq[7:0]
DLY_LANE1_IDELAY= [0x40,0x2c,0x2b,0x2c,0x2c,0x34,0x30,0x33,0x30] # idelay dqs, idelay dq[7:0
DLY_CMDA= [0x3c,0x3c,0x3c,0x3c,0x3b,0x3a,0x39,0x38,0x34,0x34,0x34,0x34,0x33,0x32,0x31,0x30,
0x00,0x2c,0x2c,0x2c,0x2b,0x2a,0x29,0x28,0x24,0x24,0x24,0x24,0x23,0x22,0x21,0x20] # odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
# alternative to set same type delays to the same value
DLY_DQ_IDELAY = 0x20
DLY_DQ_ODELAY = 0xa0
DLY_DQS_IDELAY = 0x40
DLY_DQS_ODELAY = 0x4c #should match with phase write leveling
DLY_DM_ODELAY = 0xa0
DLY_CMDA_ODELAY =0x50
else:
DLY_LANE0_DQS_WLV_IDELAY = 0xe8 # idelay dqs
DLY_LANE1_DQS_WLV_IDELAY = 0xe8 # idelay dqs
DLY_LANE0_ODELAY= [0x74,0x74,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # odelay dqm, odelay ddqs, odelay dq[7:0]
DLY_LANE0_IDELAY= [0xd8,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # idelay dqs, idelay dq[7:0
DLY_LANE1_ODELAY= [0x74,0x74,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # odelay dqm, odelay ddqs, odelay dq[7:0]
DLY_LANE1_IDELAY= [0xd8,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # idelay dqs, idelay dq[7:0
DLY_CMDA= [0x5c,0x5c,0x5c,0x5c,0x5b,0x5a,0x59,0x58,0x54,0x54,0x54,0x54,0x53,0x52,0x51,0x50,
0x00,0x4c,0x4c,0x4c,0x4b,0x4a,0x49,0x48,0x44,0x44,0x44,0x44,0x43,0x42,0x41,0x40] # odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
# alternative to set same type delays to the same value
DLY_DQ_IDELAY = 0x20
DLY_DQ_ODELAY = 0xa0
DLY_DQS_IDELAY = 0x40
DLY_DQS_ODELAY = 0x4c #should match with phase write leveling
DLY_DM_ODELAY = 0xa0
DLY_CMDA_ODELAY =0x50
NUM_FINE_STEPS= 5
#`endif
DLY_PHASE= 0x2c # 0x1c # mmcm fine phase shift, 1/4 tCK
*/
`ifdef TARGET_MODE
`ifdef use200Mhz
localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
localparam DLY_LANE0_ODELAY= 80'h984c9494989c92999894; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE0_IDELAY= 72'h401314141c1314131a; // idelay dqs, idelay dq[7:0
localparam DLY_LANE1_ODELAY= 80'h984c9898989b99a89c98; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE1_IDELAY= 72'h402c2b2c2c34303330; // idelay dqs, idelay dq[7:0
localparam DLY_CMDA= 256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// alternative to set same type delays to the same value
localparam DLY_DQ_IDELAY = 'h20 ;// 'h60;
localparam DLY_DQ_ODELAY = 'ha0; // 'h48;
localparam DLY_DQS_IDELAY = 'h40; // 'ha0;
localparam DLY_DQS_ODELAY = 'h4c; //
localparam DLY_DM_ODELAY = 'ha0; // 'h48;
localparam DLY_CMDA_ODELAY ='h50; // 'h30;
`else
localparam DLY_LANE0_DQS_WLV_IDELAY = 8'he8; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = 8'he8; // idelay dqs
localparam DLY_LANE0_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE0_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
localparam DLY_CMDA= 256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// alternative to set same type delays to the same value
/* localparam DLY_DQ_IDELAY = 'h70;
localparam DLY_DQ_ODELAY = 'h68;
localparam DLY_DQS_IDELAY = 'hd8;
localparam DLY_DQS_ODELAY = 'h74; // b0 for WLV
localparam DLY_DM_ODELAY = 'h74;
localparam DLY_CMDA_ODELAY ='h50; */
localparam DLY_DQ_IDELAY = 'h20 ;// 'h60;
localparam DLY_DQ_ODELAY = 'ha0; // 'h48;
localparam DLY_DQS_IDELAY = 'h40; // 'ha0;
localparam DLY_DQS_ODELAY = 'h4c; //
localparam DLY_DM_ODELAY = 'ha0; // 'h48;
localparam DLY_CMDA_ODELAY ='h50; // 'h30;
`endif
localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
`else
`ifdef use200Mhz
localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
localparam DLY_LANE0_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
......@@ -42,8 +128,7 @@
localparam DLY_DQS_ODELAY = 'h4c; //
localparam DLY_DM_ODELAY = 'ha0; // 'h48;
localparam DLY_CMDA_ODELAY ='h50; // 'h30;
`else
`else
localparam DLY_LANE0_DQS_WLV_IDELAY = 8'he8; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = 8'he8; // idelay dqs
localparam DLY_LANE0_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
......@@ -58,11 +143,9 @@
localparam DLY_DQS_ODELAY = 'h74; // b0 for WLV
localparam DLY_DM_ODELAY = 'h74;
localparam DLY_CMDA_ODELAY ='h50;
`endif
`endif
localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
`endif
localparam DQSTRI_FIRST= 4'h3; // DQS tri-state control word, first when enabling output
localparam DQSTRI_LAST= 4'hc; // DQS tri-state control word, first after disabling output
......
includes/x393_simulation_parameters.vh
View file @ 27a6599b
......@@ -24,5 +24,5 @@
parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
parameter integer AXI_TASK_HOLD=1.0,
parameter [1:0] DEFAULT_STATUS_MODE=3,
// parameter [1:0] DEFAULT_STATUS_MODE=3,
parameter SIMUL_AXI_READ_WIDTH=16
\ No newline at end of file
py393/.settings/org.eclipse.core.resources.prefs
View file @ 27a6599b
eclipse.preferences.version=1
encoding/exp_gpio.py=utf-8
encoding/import_verilog_parameters.py=utf-8
encoding/mon_gpio.py=utf-8
encoding/test_mcntrl.py=utf-8
py393/args
View file @ 27a6599b
-v
-d aaa=bbb
-d ccc=ddd
-d TARGET_MODE=1
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_localparams.vh
-p NEWPAR='h3ff
......
py393/hargs 0 → 100644
View file @ 27a6599b
-v
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_localparams.vh
-p NEWPAR='h3ff
-i
\ No newline at end of file
py393/import_verilog_parameters.py
View file @ 27a6599b
......@@ -521,7 +521,7 @@ class ImportVerilogParameters(object):
break
# common for comma-separated parameters - real/integer or bit range
if line[0]=="[": # skip bit range
while ((line.find("]")<0) or (line.find("]")==(len(line-1)))) and preprocessedLines: # not found at all or last element in the stting - add next line
while ((line.find("]")<0) or (line.find("]")==(len(line)-1))) and preprocessedLines: # not found at all or last element in the string - add next line
line+=preprocessedLines.pop(0)
parType=line[:line.find("]")+1:]
line=line[line.find("]")+1:]
......
py393/test_mcntrl.py
View file @ 27a6599b
......@@ -45,6 +45,7 @@ from argparse import RawDescriptionHelpFormatter
from import_verilog_parameters import ImportVerilogParameters
from import_verilog_parameters import VerilogParameters
import x393_mem
import x393_utils
import x393_axi_control_status
import x393_pio_sequences
import x393_mcntrl_timing
......@@ -58,6 +59,7 @@ __updated__ = '2015-03-01'
DEBUG = 1
TESTRUN = 0
PROFILE = 0
QUIET=1 # more try/excepts
callableTasks={}
class CLIError(Exception):
#Generic exception to raise and log different fatal errors.
......@@ -99,8 +101,7 @@ def execTask(commandLine):
funcArgs[i]=eval(arg) # Try parsing parameters as numbers, if possible
except:
pass
result = callableTasks[funcName]['func'](callableTasks[funcName]['inst'],*funcArgs)
'''
if QUIET:
try:
result = callableTasks[funcName]['func'](callableTasks[funcName]['inst'],*funcArgs)
except Exception as e:
......@@ -117,7 +118,8 @@ def execTask(commandLine):
sFuncArgs+=' <'+str(a)+'>'
print ("Usage:\n%s %s"%(funcName,sFuncArgs))
print ("exception message:"+str(e))
'''
else:
result = callableTasks[funcName]['func'](callableTasks[funcName]['inst'],*funcArgs)
return result
def hx(obj):
try:
......@@ -181,11 +183,13 @@ USAGE
parser.add_argument("-c", "--command", dest="commands", action="append", default=[], help="execute command" , nargs='*')
parser.add_argument("-i", "--interactive", dest="interactive", action="store_true", help="enter interactive mode [default: %(default)s]")
parser.add_argument("-s", "--simulated", dest="simulated", action="store_true", help="Simulated mode (no real hardware I/O) [default: %(default)s]")
parser.add_argument("-x", "--exceptions", dest="exceptions", action="count", help="Exit on more exceptions [default: %(default)s]")
# Process arguments
args = parser.parse_args()
QUIET = args.exceptions == 0
if not args.simulated:
if not os.path.isfile("/dev/xdevcfg"):
if not os.path.exists("/dev/xdevcfg"):
args.simulated=True
print("Program is forced to run in SIMULATED mode as '/dev/xdevcfg' does not exist (not a camera)")
#print("--- defines=%s"% str(args.defines))
......@@ -282,6 +286,7 @@ USAGE
if verbose > 3: print("vpars1.VERBOSE__RAW="+str(vpars1.VERBOSE__RAW))
x393mem= x393_mem.X393Mem(verbose,args.simulated) #add dry run parameter
x393utils= x393_utils.X393Utils(verbose,args.simulated)
x393tasks= x393_axi_control_status.X393AxiControlStatus(verbose,args.simulated)
x393Pio= x393_pio_sequences.X393PIOSequences(verbose,args.simulated)
x393Timing= x393_mcntrl_timing.X393McntrlTiming(verbose,args.simulated)
......@@ -302,6 +307,7 @@ USAGE
func_args=x393_mem.X393Mem.__dict__[name].func_code.co_varnames[1:x393_mem.X393Mem.__dict__[name].func_code.co_argcount]
print (name+": "+str(func_args))
extractTasks(x393_mem.X393Mem,x393mem)
extractTasks(x393_utils.X393Utils,x393utils)
extractTasks(x393_axi_control_status.X393AxiControlStatus,x393tasks)
extractTasks(x393_pio_sequences.X393PIOSequences,x393Pio)
extractTasks(x393_mcntrl_timing.X393McntrlTiming,x393Timing)
......
py393/x393_axi_control_status.py
View file @ 27a6599b
......@@ -41,6 +41,7 @@ class X393AxiControlStatus(object):
# vpars=None
x393_mem=None
enabled_channels=0 # currently enable channels
FPGA_RST_CTRL=0xf8000240
# verbose=1
def __init__(self, debug_mode=1,dry_mode=True):
self.DEBUG_MODE=debug_mode
......@@ -140,7 +141,7 @@ class X393AxiControlStatus(object):
mode, # input [1:0] mode;
seq_number): # input [5:0] seq_number;
"""
Poll specified status register until some condition is matched
Program status control for specified module/register
<base_addr> - base control address of the selected module
<reg_addr> - status control register relative to the module address space
<mode> - status generation mode:
......
py393/x393_mem.py
View file @ 27a6599b
......@@ -83,7 +83,7 @@ class X393Mem(object):
'''
if self.DRY_MODE:
print ("read_mem(0x%x)"%(addr))
return
return addr # just some data
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
......@@ -96,6 +96,38 @@ class X393Mem(object):
print ("0x%08x ==> 0x%08x (%d)"%(addr,d,d))
return d
# mm.close() #probably not needed with "with"
def mem_dump (self,start_addr,end_addr=0):
'''
Read and print memory range from physical memory
<start_addr> - physical byte start address
<end_addr> - physical byte end address (inclusive)
Returns list of read values
'''
start_addr &= 0xfffffffc
end_addr &= 0xfffffffc
if end_addr<start_addr:
end_addr = start_addr
rslt=[]
if self.DRY_MODE:
rslt=range(start_addr,end_addr+1,4)
else:
with open("/dev/mem", "r+b") as f:
for addr in range (start_addr,end_addr+4,4):
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
data=struct.unpack(self.ENDIAN+"L",mm[page_offs:page_offs+4])
rslt.append(data[0])
for addr in range (start_addr,end_addr+4,4):
if (addr == start_addr) or ((addr & 0x3f) == 0):
print ("\n0x%08x:"%addr,end=""),
d=rslt[(addr-start_addr) >> 2]
print ("%08x "%d,end=""),
print("")
return rslt
'''
Read/write slave AXI using byte addresses relative to the AXI memory region
'''
......
py393/x393_utils.py 0 → 100644
View file @ 27a6599b
from __future__ import print_function
'''
# Copyright (C) 2015, Elphel.inc.
# Parsing Verilog parameters from the header files
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
from import_verilog_parameters import VerilogParameters
from x393_mem import X393Mem
#from verilog_utils import hx,concat, bits
#from verilog_utils import hx
#from subprocess import call
from time import sleep
DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
FPGA_RST_CTRL= 0xf8000240
FPGA0_THR_CTRL=0xf8000178
FPGA_LOAD_BITSTREAM="/dev/xdevcfg"
INT_STS= 0xf800700c
class X393Utils(object):
DRY_MODE= True # True
DEBUG_MODE=1
# vpars=None
x393_mem=None
enabled_channels=0 # currently enable channels
# verbose=1
def __init__(self, debug_mode=1,dry_mode=True):
self.DEBUG_MODE=debug_mode
self.DRY_MODE=dry_mode
self.x393_mem=X393Mem(debug_mode,dry_mode)
self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
def reset_get(self):
"""
Get current reset state
"""
return self.x393_mem.read_mem(FPGA_RST_CTRL)
def reset_once(self):
"""
Pulse reset ON, then OFF
"""
self.reset((0,0xa))
def reset(self,data):
"""
Write data to FPGA_RST_CTRL register
<data> currently data=1 - reset on, data=0 - reset on
data can also be a list/tuple of integers, then it will be applied
in sequence (0,0xe) will turn reset on, then off
"""
if isinstance(data,int):
self.x393_mem.write_mem(FPGA_RST_CTRL,data)
else:
for d in data:
self.x393_mem.write_mem(FPGA_RST_CTRL,d)
def bitstream(self,bitfile=DEFAULT_BITFILE):
"""
Turn FPGA clock OFF, reset ON, load bitfile, turn clock ON and reset OFF
<bitfile> path to bitfile if provided, otherwise default bitfile will be used
"""
print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
print ("Reset ON")
self.reset(0)
print ("cat %s >%s"%(bitfile,FPGA_LOAD_BITSTREAM))
if not self.DRY_MODE:
l=0
with open(bitfile, 'rb') as src, open(FPGA_LOAD_BITSTREAM, 'wb') as dst:
buffer_size=1024*1024
while True:
copy_buffer=src.read(buffer_size)
if not copy_buffer:
break
dst.write(copy_buffer)
l+=len(copy_buffer)
print("sent %d bytes to FPGA"%l)
print("Loaded %d bytes to FPGA"%l)
# call(("cat",bitfile,">"+FPGA_LOAD_BITSTREAM))
print("Wait for DONE")
if not self.DRY_MODE:
for _ in range(100):
if (self.x393_mem.read_mem(INT_STS) & 4) != 0:
break
sleep(0.1)
else:
print("Timeout waiting for DONE, [0x%x]=0x%x"%(INT_STS,self.x393_mem.read_mem(INT_STS)))
return
print ("FPGA clock ON")
self.x393_mem.write_mem(FPGA0_THR_CTRL,0)
print ("Reset OFF")
self.reset(0xa)
def exp_gpio (self,
mode="in",
gpio_low=54,
gpio_high=None):
"""
Export GPIO pins connected to PL (full range is 54..117)
<mode> GPIO mode: "in" or "out"
<gpio_low> lowest GPIO to export
<gpio_hi> Highest GPIO to export. Set to <gpio_low> if not provided
"""
if gpio_high is None:
gpio_high=gpio_low
print ("Exporting as \""+mode+"\":", end=""),
for gpio_n in range (gpio_low, gpio_high + 1):
print (" %d"%gpio_n, end="")
print()
if not self.DRY_MODE:
for gpio in range (gpio_low, gpio_high + 1):
try:
with open ("/sys/class/gpio/export","w") as f:
print (gpio,file=f)
except:
print ("failed \"echo %d > /sys/class/gpio/export"%gpio)
try:
with open ("/sys/class/gpio/gpio%d/direction"%gpio,"w") as f:
print (mode,file=f)
except:
print ("failed \"echo %s > /sys/class/gpio/gpio%d/direction"%(mode,gpio))
def mon_gpio (self,
gpio_low=54,
gpio_high=None):
"""
Get state of the GPIO pins connected to PL (full range is 54..117)
<gpio_low> lowest GPIO to export
<gpio_hi> Highest GPIO to export. Set to <gpio_low> if not provided
Returns data as list of 0,1 or None
"""
if gpio_high is None:
gpio_high=gpio_low
print ("gpio %d.%d: "%(gpio_high,gpio_low), end="")
d=[]
for gpio in range (gpio_high, gpio_low-1,-1):
if gpio != gpio_high and ((gpio-gpio_low+1) % 4) == 0:
print (".",end="")
if not self.DRY_MODE:
try:
with open ("/sys/class/gpio/gpio%d/value"%gpio,"r") as f:
b=int(f.read(1))
print ("%d"%b,end="")
d.append(b)
except:
print ("X",end="")
d.append(None)
else:
print ("X",end="")
d.append(None)
print()
return d
x393.v
View file @ 27a6599b
......@@ -223,7 +223,7 @@ module x393 #(
assign gpio_in= {52'h0,tmp_debug};
assign gpio_in= {48'h0,frst,tmp_debug};
......
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