Commit 27a6599b authored by Andrey Filippov's avatar Andrey Filippov
Browse files

working on hardware testing, added utility functions to load bitstream and use GPIO for debugging

parent fad107cb

.project

+15 −15
Original line number Original line Diff line number Diff line
@@ -62,77 +62,77 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<name>vivado_logs/VivadoBitstream.log</name>

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			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150228213748063.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150311172942225.log</location>

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			<name>vivado_logs/VivadoOptPower.log</name>

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		</link>

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			<name>vivado_logs/VivadoPlace.log</name>

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			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

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			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150228213503140.dcp</location>

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		</link>

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</projectDescription>
 
</projectDescription>

includes/x393_localparams.vh

+90 −7
Original line number Original line Diff line number Diff line
@@ -19,6 +19,7 @@ 
 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

 *******************************************************************************/

// S uppressWarnings VEditor

// S uppressWarnings VEditor

  localparam [1:0] DEFAULT_STATUS_MODE = 3; // auto status on change, increase sequence number

  localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080

  localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080

  localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090

  localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090

  localparam LD_DLY_LANE1_ODELAY = DLY_LD+'h20; // 0x10a0

  localparam LD_DLY_LANE1_ODELAY = DLY_LD+'h20; // 0x10a0
@@ -26,7 +27,92 @@ 
  localparam LD_DLY_CMDA  =        DLY_LD+'h40; // 0x10c0

  localparam LD_DLY_CMDA  =        DLY_LD+'h40; // 0x10c0

  localparam LD_DLY_PHASE =        DLY_LD+'h60; // 0x10e0

  localparam LD_DLY_PHASE =        DLY_LD+'h60; // 0x10e0

  localparam DLY_SET =             MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020

  localparam DLY_SET =             MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020

// different sets of settings for the functional simulation and the actual hardware

/*

if use200Mhz:

    DLY_LANE0_DQS_WLV_IDELAY = 0xb0 # idelay dqs

    DLY_LANE1_DQS_WLV_IDELAY = 0xb0 # idelay dqs

    DLY_LANE0_ODELAY= [0x98,0x4c,0x94,0x94,0x98,0x9c,0x92,0x99,0x98,0x94] # odelay dqm, odelay ddqs, odelay dq[7:0]

    

    

    DLY_LANE0_IDELAY=      [0x40,0x13,0x14,0x14,0x1c,0x13,0x14,0x13,0x1a] # idelay dqs, idelay dq[7:0

    DLY_LANE1_ODELAY= [0x98,0x4c,0x98,0x98,0x98,0x9b,0x99,0xa8,0x9c,0x98] # odelay dqm, odelay ddqs, odelay dq[7:0]

    

    DLY_LANE1_IDELAY=      [0x40,0x2c,0x2b,0x2c,0x2c,0x34,0x30,0x33,0x30] # idelay dqs, idelay dq[7:0

    DLY_CMDA=  [0x3c,0x3c,0x3c,0x3c,0x3b,0x3a,0x39,0x38,0x34,0x34,0x34,0x34,0x33,0x32,0x31,0x30,

                0x00,0x2c,0x2c,0x2c,0x2b,0x2a,0x29,0x28,0x24,0x24,0x24,0x24,0x23,0x22,0x21,0x20] # odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0



# alternative to set same type delays to the same value    

    DLY_DQ_IDELAY =  0x20

    DLY_DQ_ODELAY =  0xa0

    DLY_DQS_IDELAY = 0x40

    DLY_DQS_ODELAY = 0x4c #should match with phase write leveling

    DLY_DM_ODELAY =  0xa0

    DLY_CMDA_ODELAY =0x50

    

else:   

    DLY_LANE0_DQS_WLV_IDELAY = 0xe8 # idelay dqs

    DLY_LANE1_DQS_WLV_IDELAY = 0xe8 # idelay dqs

    DLY_LANE0_ODELAY= [0x74,0x74,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # odelay dqm, odelay ddqs, odelay dq[7:0]

    DLY_LANE0_IDELAY=      [0xd8,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # idelay dqs, idelay dq[7:0

    DLY_LANE1_ODELAY= [0x74,0x74,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # odelay dqm, odelay ddqs, odelay dq[7:0]

    DLY_LANE1_IDELAY=      [0xd8,0x73,0x72,0x71,0x70,0x6c,0x6b,0x6a,0x69] # idelay dqs, idelay dq[7:0

    DLY_CMDA=  [0x5c,0x5c,0x5c,0x5c,0x5b,0x5a,0x59,0x58,0x54,0x54,0x54,0x54,0x53,0x52,0x51,0x50,

                0x00,0x4c,0x4c,0x4c,0x4b,0x4a,0x49,0x48,0x44,0x44,0x44,0x44,0x43,0x42,0x41,0x40] # odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0

# alternative to set same type delays to the same value    

    DLY_DQ_IDELAY =  0x20

    DLY_DQ_ODELAY =  0xa0

    DLY_DQS_IDELAY = 0x40

    DLY_DQS_ODELAY = 0x4c #should match with phase write leveling

    DLY_DM_ODELAY =  0xa0

    DLY_CMDA_ODELAY =0x50





NUM_FINE_STEPS=    5

#`endif   

    

DLY_PHASE=       0x2c # 0x1c # mmcm fine phase shift, 1/4 tCK



*/  

`ifdef TARGET_MODE 

  `ifdef use200Mhz

    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

    localparam DLY_LANE0_ODELAY= 80'h984c9494989c92999894; // odelay dqm, odelay ddqs, odelay dq[7:0]

    localparam DLY_LANE0_IDELAY= 72'h401314141c1314131a; // idelay dqs, idelay dq[7:0

    localparam DLY_LANE1_ODELAY= 80'h984c9898989b99a89c98; // odelay dqm, odelay ddqs, odelay dq[7:0]

    localparam DLY_LANE1_IDELAY= 72'h402c2b2c2c34303330;   // idelay dqs, idelay dq[7:0

    localparam DLY_CMDA= 256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0

// alternative to set same type delays to the same value    

    localparam DLY_DQ_IDELAY =  'h20 ;// 'h60;

    localparam DLY_DQ_ODELAY =  'ha0; // 'h48;

    localparam DLY_DQS_IDELAY = 'h40; // 'ha0;

    localparam DLY_DQS_ODELAY = 'h4c; // 

    localparam DLY_DM_ODELAY =  'ha0; // 'h48;

    localparam DLY_CMDA_ODELAY ='h50; // 'h30;

  `else   

    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'he8; // idelay dqs

    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'he8; // idelay dqs

    localparam DLY_LANE0_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]

    localparam DLY_LANE0_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0

    localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]

    localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0

    localparam DLY_CMDA=  256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0

// alternative to set same type delays to the same value    

/*  localparam DLY_DQ_IDELAY =  'h70;

    localparam DLY_DQ_ODELAY =  'h68;

    localparam DLY_DQS_IDELAY = 'hd8;

    localparam DLY_DQS_ODELAY = 'h74; // b0 for WLV

    localparam DLY_DM_ODELAY =  'h74;

    localparam DLY_CMDA_ODELAY ='h50; */

    localparam DLY_DQ_IDELAY =  'h20 ;// 'h60;

    localparam DLY_DQ_ODELAY =  'ha0; // 'h48;

    localparam DLY_DQS_IDELAY = 'h40; // 'ha0;

    localparam DLY_DQS_ODELAY = 'h4c; // 

    localparam DLY_DM_ODELAY =  'ha0; // 'h48;

    localparam DLY_CMDA_ODELAY ='h50; // 'h30;

  `endif   

    localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK

`else

  `ifdef use200Mhz

  `ifdef use200Mhz

    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
@@ -42,7 +128,6 @@ 
    localparam DLY_DQS_ODELAY = 'h4c; // 

    localparam DLY_DQS_ODELAY = 'h4c; // 

    localparam DLY_DM_ODELAY =  'ha0; // 'h48;

    localparam DLY_DM_ODELAY =  'ha0; // 'h48;

    localparam DLY_CMDA_ODELAY ='h50; // 'h30;

    localparam DLY_CMDA_ODELAY ='h50; // 'h30;

    

  `else   

  `else   

    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'he8; // idelay dqs

    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'he8; // idelay dqs

    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'he8; // idelay dqs

    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'he8; // idelay dqs
@@ -58,11 +143,9 @@ 
    localparam DLY_DQS_ODELAY = 'h74; // b0 for WLV

    localparam DLY_DQS_ODELAY = 'h74; // b0 for WLV

    localparam DLY_DM_ODELAY =  'h74;

    localparam DLY_DM_ODELAY =  'h74;

    localparam DLY_CMDA_ODELAY ='h50;

    localparam DLY_CMDA_ODELAY ='h50;





  `endif

  `endif

    

    localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK

    localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK

`endif

    

    

    localparam DQSTRI_FIRST=    4'h3; // DQS tri-state control word, first when enabling output 

    localparam DQSTRI_FIRST=    4'h3; // DQS tri-state control word, first when enabling output 

    localparam DQSTRI_LAST=     4'hc; // DQS tri-state control word, first after disabling output

    localparam DQSTRI_LAST=     4'hc; // DQS tri-state control word, first after disabling output

includes/x393_simulation_parameters.vh

+1 −1
Original line number Original line Diff line number Diff line
@@ -24,5 +24,5 @@ 
    parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1

    parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1

    parameter integer AXI_TASK_HOLD=1.0,

    parameter integer AXI_TASK_HOLD=1.0,

    

    

    parameter [1:0] DEFAULT_STATUS_MODE=3,

//    parameter [1:0] DEFAULT_STATUS_MODE=3,

    parameter       SIMUL_AXI_READ_WIDTH=16
 
    parameter       SIMUL_AXI_READ_WIDTH=16
 
 No newline at end of file

py393/.settings/org.eclipse.core.resources.prefs

+2 −0
Original line number Original line Diff line number Diff line 
eclipse.preferences.version=1

eclipse.preferences.version=1

encoding/exp_gpio.py=utf-8

encoding/import_verilog_parameters.py=utf-8

encoding/import_verilog_parameters.py=utf-8

encoding/mon_gpio.py=utf-8

encoding/test_mcntrl.py=utf-8
 
encoding/test_mcntrl.py=utf-8

py393/args

+1 −2
Original line number Original line Diff line number Diff line 
-v

-v

-d aaa=bbb

-d TARGET_MODE=1

-d ccc=ddd

-f ../system_defines.vh

-f ../system_defines.vh

-f ../includes/x393_parameters.vh  ../includes/x393_localparams.vh

-f ../includes/x393_parameters.vh  ../includes/x393_localparams.vh

-p NEWPAR='h3ff

-p NEWPAR='h3ff