// R/W addresses to set up memory arbiter priorities. For sensors (chn = 8..11), for compressors - 12..15
voidset_x393_mcntrl_arbiter_priority(x393_arbite_pri_td,intchn){writel(0x40000180+0x4*chn,(u32)d)};// Set memory arbiter priority (currently r/w, may become just wo)
// Write-only addresses to program memory channels for sensors (chn = 0..3), memory channels 8..11
voidx393_sens_mcntrl_scanline_mode(x393_mcntrl_mode_scan_td,intchn){writel(0x40001a00+0x40*chn,(u32)d)};// Set mode register (write last after other channel registers are set)
voidset_x393_sens_mcntrl_scanline_status_cntrl(x393_status_ctrl_td,intchn){writel(0x40001a04+0x40*chn,(u32)d)};// Set status control register (status update mode)
voidx393_sens_mcntrl_scanline_startaddr(x393_mcntrl_window_frame_sa_td,intchn){writel(0x40001a08+0x40*chn,(u32)d)};// Set frame start address
voidx393_sens_mcntrl_scanline_frame_size(x393_mcntrl_window_frame_sa_inc_td,intchn){writel(0x40001a0c+0x40*chn,(u32)d)};// Set frame size (address increment)
voidx393_sens_mcntrl_scanline_frame_last(x393_mcntrl_window_last_frame_num_td,intchn){writel(0x40001a10+0x40*chn,(u32)d)};// Set last frame number (number of frames in buffer minus 1)
voidx393_sens_mcntrl_scanline_frame_full_width(x393_mcntrl_window_full_width_td,intchn){writel(0x40001a14+0x40*chn,(u32)d)};// Set frame full(padded) width
voidx393_sens_mcntrl_scanline_window_wh(x393_mcntrl_window_width_height_td,intchn){writel(0x40001a18+0x40*chn,(u32)d)};// Set frame window size
voidx393_sens_mcntrl_scanline_window_x0y0(x393_mcntrl_window_left_top_td,intchn){writel(0x40001a1c+0x40*chn,(u32)d)};// Set frame position
voidx393_sens_mcntrl_scanline_startxy(x393_mcntrl_window_startx_starty_td,intchn){writel(0x40001a20+0x40*chn,(u32)d)};// Set startXY register
// Write-only addresses to program memory channels for compressors (chn = 0..3), memory channels 12..15
voidx393_sens_mcntrl_tiled_mode(x393_mcntrl_mode_scan_td,intchn){writel(0x40001b00+0x40*chn,(u32)d)};// Set mode register (write last after other channel registers are set)
voidset_x393_sens_mcntrl_tiled_status_cntrl(x393_status_ctrl_td,intchn){writel(0x40001b04+0x40*chn,(u32)d)};// Set status control register (status update mode)
voidx393_sens_mcntrl_tiled_startaddr(x393_mcntrl_window_frame_sa_td,intchn){writel(0x40001b08+0x40*chn,(u32)d)};// Set frame start address
voidx393_sens_mcntrl_tiled_frame_size(x393_mcntrl_window_frame_sa_inc_td,intchn){writel(0x40001b0c+0x40*chn,(u32)d)};// Set frame size (address increment)
voidx393_sens_mcntrl_tiled_frame_last(x393_mcntrl_window_last_frame_num_td,intchn){writel(0x40001b10+0x40*chn,(u32)d)};// Set last frame number (number of frames in buffer minus 1)
voidx393_sens_mcntrl_tiled_frame_full_width(x393_mcntrl_window_full_width_td,intchn){writel(0x40001b14+0x40*chn,(u32)d)};// Set frame full(padded) width
voidx393_sens_mcntrl_tiled_window_wh(x393_mcntrl_window_width_height_td,intchn){writel(0x40001b18+0x40*chn,(u32)d)};// Set frame window size
voidx393_sens_mcntrl_tiled_window_x0y0(x393_mcntrl_window_left_top_td,intchn){writel(0x40001b1c+0x40*chn,(u32)d)};// Set frame position
voidx393_sens_mcntrl_tiled_startxy(x393_mcntrl_window_startx_starty_td,intchn){writel(0x40001b20+0x40*chn,(u32)d)};// Set startXY register
voidx393_sens_mcntrl_tiled_tile_whs(x393_mcntrl_window_tile_whs_td,intchn){writel(0x40001b24+0x40*chn,(u32)d)};// Set tile size/step (tiled mode only)
// Write-only addresses to program memory channel for membridge, memory channel 1
voidx393_membridge_scanline_mode(x393_mcntrl_mode_scan_td){writel(0x40000480,(u32)d)};// Set mode register (write last after other channel registers are set)
voidset_x393_membridge_scanline_status_cntrl(x393_status_ctrl_td){writel(0x40000484,(u32)d)};// Set status control register (status update mode)
voidx393_membridge_scanline_startaddr(x393_mcntrl_window_frame_sa_td){writel(0x40000488,(u32)d)};// Set frame start address
voidx393_membridge_scanline_frame_size(x393_mcntrl_window_frame_sa_inc_td){writel(0x4000048c,(u32)d)};// Set frame size (address increment)
voidx393_membridge_scanline_frame_last(x393_mcntrl_window_last_frame_num_td){writel(0x40000490,(u32)d)};// Set last frame number (number of frames in buffer minus 1)
voidx393_membridge_scanline_frame_full_width(x393_mcntrl_window_full_width_td){writel(0x40000494,(u32)d)};// Set frame full(padded) width
voidx393_membridge_scanline_window_wh(x393_mcntrl_window_width_height_td){writel(0x40000498,(u32)d)};// Set frame window size
voidx393_membridge_scanline_window_x0y0(x393_mcntrl_window_left_top_td){writel(0x4000049c,(u32)d)};// Set frame position
voidx393_membridge_scanline_startxy(x393_mcntrl_window_startx_starty_td){writel(0x400004a0,(u32)d)};// Set startXY register
// Write-only addresses for test channels commands
voidx393_mcntrl_test01_chn2_mode(x393_test01_mode_td){writel(0x400003d0,(u32)d)};// Set command for test01 channel 2
voidx393_mcntrl_test01_chn3_mode(x393_test01_mode_td){writel(0x400003d8,(u32)d)};// Set command for test01 channel 3
voidx393_mcntrl_test01_chn4_mode(x393_test01_mode_td){writel(0x400003e0,(u32)d)};// Set command for test01 channel 4
// Read-only addresses for status information
x393_status_mcntrl_phy_tx393_mcontr_phy_status(void){return(x393_status_mcntrl_phy_t)readl(0x40002000)};// Status register for MCNTRL PHY
x393_status_mcntrl_top_tx393_mcontr_top_status(void){return(x393_status_mcntrl_top_t)readl(0x40002004)};// Status register for MCNTRL requests
x393_status_mcntrl_ps_tx393_mcntrl_ps_status(void){return(x393_status_mcntrl_ps_t)readl(0x40002008)};// Status register for MCNTRL software R/W
x393_status_mcntrl_lintile_tx393_mcntrl_chn1_status(void){return(x393_status_mcntrl_lintile_t)readl(0x40002010)};// Status register for MCNTRL CHN1 (membridge)
x393_status_mcntrl_lintile_tx393_mcntrl_chn3_status(void){return(x393_status_mcntrl_lintile_t)readl(0x40002018)};// Status register for MCNTRL CHN3 (scanline)
x393_status_mcntrl_lintile_tx393_mcntrl_chn2_status(void){return(x393_status_mcntrl_lintile_t)readl(0x40002014)};// Status register for MCNTRL CHN2 (tiled)
x393_status_mcntrl_lintile_tx393_mcntrl_chn4_status(void){return(x393_status_mcntrl_lintile_t)readl(0x4000201c)};// Status register for MCNTRL CHN4 (tiled)
x393_status_mcntrl_testchn_tx393_test01_chn2_status(void){return(x393_status_mcntrl_testchn_t)readl(0x400020f4)};// Status register for test channel 2
x393_status_mcntrl_testchn_tx393_test01_chn3_status(void){return(x393_status_mcntrl_testchn_t)readl(0x400020f8)};// Status register for test channel 3
x393_status_mcntrl_testchn_tx393_test01_chn4_status(void){return(x393_status_mcntrl_testchn_t)readl(0x400020fc)};// Status register for test channel 4
x393_status_membridge_tx393_membridge_status(void){return(x393_status_membridge_t)readl(0x400020ec)};// Status register for membridge
voidx393_sensio_jtag(x393_sensio_jpag_td,intsens_num){writel(0x40001028+0x100*sens_num,(u32)d)};// Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)
voidset_x393_sensio_width(x393_sensio_width_td,intsens_num){writel(0x4000102c+0x100*sens_num,(u32)d)};// Set sensor line in pixels (0 - use line sync from the sensor)
// Read-only addresses for sensors status information
x393_status_sens_i2c_tx393_sensi2c_status(intsens_num){return(x393_status_sens_i2c_t)readl(0x40002080+0x8*sens_num)};// Status of the sensors i2c
x393_status_sens_io_tx393_sensio_status(intsens_num){return(x393_status_sens_io_t)readl(0x40002084+0x8*sens_num)};// Status of the sensor ports I/O pins
// Compressor bitfields values
// Compressor control
voidx393_cmprs_control_reg(x393_cmprs_mode_td,intcmprs_chn){writel(0x40001800+0x40*cmprs_chn,(u32)d)};// Program compressor channel operation mode
voidset_x393_cmprs_status(x393_status_ctrl_td,intcmprs_chn){writel(0x40001804+0x40*cmprs_chn,(u32)d)};// Setup compressor status report mode
// Read-only sensors status information (pointer offset and last sequence number)
x393_afimux_status_tx393_afimux0_status(intafi_port){return(x393_afimux_status_t)readl(0x40002060+0x4*afi_port)};// Status of the AFI MUX 0 (including image pointer)
x393_afimux_status_tx393_afimux1_status(intafi_port){return(x393_afimux_status_t)readl(0x40002070+0x4*afi_port)};// Status of the AFI MUX 1 (including image pointer)
//
// GPIO contol. Each of the 10 pins can be controlled by the software - individually or simultaneously or from any of the 3 masters (other FPGA modules)
// Currently these modules are;
// A - camsync (intercamera synchronization), uses up to 4 pins
// B - reserved (not yet used) and
// C - logger (IMU, GPS, images), uses 6 pins, including separate i2c available on extension boards
// If several enabled ports try to contol the same bit, highest priority has port C, lowest - software controlled
voidx393_gpio_set_pins(x393_gpio_set_pins_td){writel(0x40001c00,(u32)d)};// State of the GPIO pins and seq. number
voidset_x393_gpio_status_control(x393_status_ctrl_td){writel(0x40001c04,(u32)d)};// GPIO status control mode
// Command sequencer multiplexer, provides current frame number for each sesnor channel and interrupt status/interrupt masks for them.
// Interrupts and interrupt masks are controlled through channel CMDFRAMESEQ module
voidset_x393_cmdseqmux_status_ctrl(x393_status_ctrl_td){writel(0x40001c08,(u32)d)};// CMDSEQMUX status control mode (status provides current frame numbers)
x393_cmdseqmux_status_tx393_cmdseqmux_status(void){return(x393_cmdseqmux_status_t)readl(0x400020e0)};// CMDSEQMUX status data (frame numbers and interrupts
// Event logger
// Event logger configuration/data is writtent to the module ising two 32-bit register locations : data and address.
// Address consists of 2 parts - 2-bit page (configuration, imu, gps, message) and a 5-bit sub-address autoincremented when writing data.
x393_logger_status_tx393_logger_status(void){return(x393_logger_status_t)readl(0x400020e4)};// Logger status data (sequence number)
// MULT SAXI DMA engine control. Of 4 channels only one (number 0) is currently used - for the event logger
voidset_x393_mult_saxi_status_ctrl(x393_status_ctrl_td){writel(0x40001ce0,(u32)d)};// MULT_SAXI status control mode (status provides current DWORD pointer)
voidx393_debug_load(void){writel(0x40001c44,0)};// Debug ring copy shift register to/from tested modules
voidx393_debug_shift(u32d){writel(0x40001c40,(u32)d)};// Debug ring shift ring by 32 bits
x393_debug_status_tx393_debug_status(void){return(x393_debug_status_t)readl(0x400023f0)};// Debug read status (watch sequence number)
u32x393_debug_read(void){return(u32)readl(0x400023f4)};// Debug read DWORD form ring register
// Write-only addresses to program memory channel 3 (test channel)
voidx393_mcntrl_chn3_scanline_mode(x393_mcntrl_mode_scan_td){writel(0x400004c0,(u32)d)};// Set mode register (write last after other channel registers are set)
voidset_x393_mcntrl_chn3_scanline_status_cntrl(x393_status_ctrl_td){writel(0x400004c4,(u32)d)};// Set status control register (status update mode)
voidx393_mcntrl_chn3_scanline_startaddr(x393_mcntrl_window_frame_sa_td){writel(0x400004c8,(u32)d)};// Set frame start address
voidx393_mcntrl_chn3_scanline_frame_size(x393_mcntrl_window_frame_sa_inc_td){writel(0x400004cc,(u32)d)};// Set frame size (address increment)
voidx393_mcntrl_chn3_scanline_frame_last(x393_mcntrl_window_last_frame_num_td){writel(0x400004d0,(u32)d)};// Set last frame number (number of frames in buffer minus 1)
voidx393_mcntrl_chn3_scanline_frame_full_width(x393_mcntrl_window_full_width_td){writel(0x400004d4,(u32)d)};// Set frame full(padded) width
voidx393_mcntrl_chn3_scanline_window_wh(x393_mcntrl_window_width_height_td){writel(0x400004d8,(u32)d)};// Set frame window size
voidx393_mcntrl_chn3_scanline_window_x0y0(x393_mcntrl_window_left_top_td){writel(0x400004dc,(u32)d)};// Set frame position
voidx393_mcntrl_chn3_scanline_startxy(x393_mcntrl_window_startx_starty_td){writel(0x400004e0,(u32)d)};// Set startXY register
// Write-only addresses to program memory channel 2 (test channel)
voidx393_mcntrl_chn2_tiled_mode(x393_mcntrl_mode_scan_td){writel(0x40000500,(u32)d)};// Set mode register (write last after other channel registers are set)
voidset_x393_mcntrl_chn2_tiled_status_cntrl(x393_status_ctrl_td){writel(0x40000504,(u32)d)};// Set status control register (status update mode)
voidx393_mcntrl_chn2_tiled_startaddr(x393_mcntrl_window_frame_sa_td){writel(0x40000508,(u32)d)};// Set frame start address
voidx393_mcntrl_chn2_tiled_frame_size(x393_mcntrl_window_frame_sa_inc_td){writel(0x4000050c,(u32)d)};// Set frame size (address increment)
voidx393_mcntrl_chn2_tiled_frame_last(x393_mcntrl_window_last_frame_num_td){writel(0x40000510,(u32)d)};// Set last frame number (number of frames in buffer minus 1)
voidx393_mcntrl_chn2_tiled_frame_full_width(x393_mcntrl_window_full_width_td){writel(0x40000514,(u32)d)};// Set frame full(padded) width
voidx393_mcntrl_chn2_tiled_window_wh(x393_mcntrl_window_width_height_td){writel(0x40000518,(u32)d)};// Set frame window size
voidx393_mcntrl_chn2_tiled_window_x0y0(x393_mcntrl_window_left_top_td){writel(0x4000051c,(u32)d)};// Set frame position
voidx393_mcntrl_chn2_tiled_startxy(x393_mcntrl_window_startx_starty_td){writel(0x40000520,(u32)d)};// Set startXY register
voidx393_mcntrl_chn2_tiled_tile_whs(x393_mcntrl_window_tile_whs_td){writel(0x40000524,(u32)d)};// Set tile size/step (tiled mode only)
// Write-only addresses to program memory channel 4 (test channel)
voidx393_mcntrl_chn4_tiled_mode(x393_mcntrl_mode_scan_td){writel(0x40000540,(u32)d)};// Set mode register (write last after other channel registers are set)
voidset_x393_mcntrl_chn4_tiled_status_cntrl(x393_status_ctrl_td){writel(0x40000544,(u32)d)};// Set status control register (status update mode)
voidx393_mcntrl_chn4_tiled_startaddr(x393_mcntrl_window_frame_sa_td){writel(0x40000548,(u32)d)};// Set frame start address
voidx393_mcntrl_chn4_tiled_frame_size(x393_mcntrl_window_frame_sa_inc_td){writel(0x4000054c,(u32)d)};// Set frame size (address increment)
voidx393_mcntrl_chn4_tiled_frame_last(x393_mcntrl_window_last_frame_num_td){writel(0x40000550,(u32)d)};// Set last frame number (number of frames in buffer minus 1)
voidx393_mcntrl_chn4_tiled_frame_full_width(x393_mcntrl_window_full_width_td){writel(0x40000554,(u32)d)};// Set frame full(padded) width
voidx393_mcntrl_chn4_tiled_window_wh(x393_mcntrl_window_width_height_td){writel(0x40000558,(u32)d)};// Set frame window size
voidx393_mcntrl_chn4_tiled_window_x0y0(x393_mcntrl_window_left_top_td){writel(0x4000055c,(u32)d)};// Set frame position
voidx393_mcntrl_chn4_tiled_startxy(x393_mcntrl_window_startx_starty_td){writel(0x40000560,(u32)d)};// Set startXY register
voidx393_mcntrl_chn4_tiled_tile_whs(x393_mcntrl_window_tile_whs_td){writel(0x40000564,(u32)d)};// Set tile size/step (tiled mode only)