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Elphel
x393
Commits
2478e215
Commit
2478e215
authored
Apr 13, 2017
by
Andrey Filippov
Browse files
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Plain Diff
merging with framepars
parents
85c297b7
d2f1b641
Changes
16
Hide whitespace changes
Inline
Side-by-side
Showing
16 changed files
with
1638 additions
and
92 deletions
+1638
-92
histogram_saxi.v
axi/histogram_saxi.v
+2
-2
x393_cocotb_03.sav
cocotb/x393_cocotb_03.sav
+232
-21
dct_tests_01.sav
dct_tests_01.sav
+417
-16
dct_iv.ods
dsp/dct_iv.ods
+0
-0
dct_iv8_1d.v
dsp/dct_iv8_1d.v
+26
-5
dct_iv_8x8.v
dsp/dct_iv_8x8.v
+615
-0
dct_tests_01.tf
dsp/dct_tests_01.tf
+116
-30
fpga_version.vh
fpga_version.vh
+5
-2
ahci_defaults.vh
includes/ahci_defaults.vh
+1
-1
ahci_localparams.vh
includes/ahci_localparams.vh
+1
-1
x393_jpeg.py
py393/x393_jpeg.py
+145
-0
sens_histogram_snglclk.v
sensor/sens_histogram_snglclk.v
+1
-0
x393_parallel.bit
x393_parallel.bit
+0
-0
ahci_top.v
x393_sata/ahci/ahci_top.v
+13
-2
oob_dev.v
x393_sata/device/oob_dev.v
+37
-3
oob.v
x393_sata/host/oob.v
+27
-9
No files found.
axi/histogram_saxi.v
View file @
2478e215
...
@@ -388,8 +388,8 @@ module histogram_saxi#(
...
@@ -388,8 +388,8 @@ module histogram_saxi#(
else
if
(
burst_done_w
&&
!
page_sent_mclk
)
pages_in_buf_wr
<=
pages_in_buf_wr
+
1
;
else
if
(
burst_done_w
&&
!
page_sent_mclk
)
pages_in_buf_wr
<=
pages_in_buf_wr
+
1
;
else
if
(
!
burst_done_w
&&
page_sent_mclk
)
pages_in_buf_wr
<=
pages_in_buf_wr
-
1
;
else
if
(
!
burst_done_w
&&
page_sent_mclk
)
pages_in_buf_wr
<=
pages_in_buf_wr
-
1
;
// grant <= en && rq_in && !buf_full && (
!started
|| busy_r); // delay grant until chn_sel is set (first cycle of started)
// grant <= en && rq_in && !buf_full && (
grant
|| busy_r); // delay grant until chn_sel is set (first cycle of started)
grant
<=
en
&&
rq_in
&&
!
buf_full
&&
(
grant
||
busy_r
)
;
// delay grant until chn_sel is set (first cycle of started)
grant
<=
en
&&
rq_in
&&
!
dav_r
&&
!
buf_full
&&
(
grant
||
busy_r
)
;
// delay grant until chn_sel is set (first cycle of started)
if
(
!
en
)
chn_grant
<=
0
;
if
(
!
en
)
chn_grant
<=
0
;
...
...
cocotb/x393_cocotb_03.sav
View file @
2478e215
[*]
[*]
[*] GTKWave Analyzer v3.3.
66 (w)1999-2015
BSI
[*] GTKWave Analyzer v3.3.
78 (w)1999-2016
BSI
[*]
Tue Nov 22 04:53:52 2016
[*]
Mon Jan 9 07:36:22 2017
[*]
[*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-201
61121203439871
.fst"
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-201
70108183700100
.fst"
[dumpfile_mtime] "
Tue Nov 22 04:52:55 2016
"
[dumpfile_mtime] "
Mon Jan 9 02:25:11 2017
"
[dumpfile_size]
442146667
[dumpfile_size]
322665780
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"
[timestart] 0
[timestart]
12360000
0
[size] 1814 1171
[size] 1814 1171
[pos] 0 0
[pos] 0 0
*-2
6.832495 36980000 -1 -1
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-2
5.086031 251800000 212597388 212637388
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.
[treeopen] x393_dut.simul_sensor12bits_2_i.
[treeopen] x393_dut.simul_sensor12bits_2_i.
[treeopen] x393_dut.simul_sensor12bits_3_i.
[treeopen] x393_dut.simul_sensor12bits_3_i.
[treeopen] x393_dut.simul_sensor12bits_i.
[treeopen] x393_dut.simul_sensor12bits_i.
[treeopen] x393_dut.x393_i.
[treeopen] x393_dut.x393_i.
[treeopen] x393_dut.x393_i.compressor393_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.
...
@@ -42,7 +41,6 @@
...
@@ -42,7 +41,6 @@
[treeopen] x393_dut.x393_i.event_logger_i.i_nmea_decoder.
[treeopen] x393_dut.x393_i.event_logger_i.i_nmea_decoder.
[treeopen] x393_dut.x393_i.event_logger_i.i_rs232_rcv.
[treeopen] x393_dut.x393_i.event_logger_i.i_rs232_rcv.
[treeopen] x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
[treeopen] x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].
...
@@ -51,27 +49,27 @@
...
@@ -51,27 +49,27 @@
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.
[treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.
[treeopen] x393_dut.x393_i.mult_saxi_wr_inbuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.
[treeopen] x393_dut.x393_i.sensors393_i.
[treeopen] x393_dut.x393_i.sensors393_i.
sensor_channel_block[0]
.
[treeopen] x393_dut.x393_i.sensors393_i.
histogram_saxi_i
.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.timing393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
[sst_width]
388
[sst_width]
465
[signals_width] 3
49
[signals_width] 3
00
[sst_expanded] 1
[sst_expanded] 1
[sst_vpaned_height] 486
[sst_vpaned_height] 486
@820
@820
...
@@ -1349,6 +1347,221 @@ x393_dut.x393_i.gpio393_i.ext_pins[9:0]
...
@@ -1349,6 +1347,221 @@ x393_dut.x393_i.gpio393_i.ext_pins[9:0]
-group_end
-group_end
@1401200
@1401200
-gpio
-gpio
@800200
-histograms
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_start_burst_w
@c00022
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
@28
(0)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(1)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(2)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(3)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(4)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(5)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(6)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(7)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(8)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(9)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(10)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(11)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(12)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(13)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(14)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(15)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(16)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(17)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(18)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(19)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(20)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(21)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(22)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(23)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(24)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(25)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(26)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(27)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(28)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(29)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(30)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
(31)x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
@1401200
-group_end
@200
-
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.en
x393_dut.x393_i.sensors393_i.histogram_saxi_i.rq_in
x393_dut.x393_i.sensors393_i.histogram_saxi_i.buf_full
x393_dut.x393_i.sensors393_i.histogram_saxi_i.busy_r
@8022
x393_dut.x393_i.sensors393_i.histogram_saxi_i.pages_in_buf_wr[2:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.pages_in_buf_rd[2:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.grant
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn0[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn1[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn2[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn3[1:0]
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data0[31:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data1[31:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data2[31:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data3[31:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_dvalid0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_dvalid1
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_dvalid2
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_dvalid3
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_grant0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_grant1
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_grant2
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_grant3
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request1
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request2
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request3
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_start_addr[31:10]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_start_page_r[19:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.inter_buf_data[31:0]
@c00022
x393_dut.x393_i.sensors393_i.histogram_saxi_i.burst[2:0]
@28
(0)x393_dut.x393_i.sensors393_i.histogram_saxi_i.burst[2:0]
(1)x393_dut.x393_i.sensors393_i.histogram_saxi_i.burst[2:0]
(2)x393_dut.x393_i.sensors393_i.histogram_saxi_i.burst[2:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.busy_w
x393_dut.x393_i.sensors393_i.histogram_saxi_i.busy_r
x393_dut.x393_i.sensors393_i.histogram_saxi_i.started
x393_dut.x393_i.sensors393_i.histogram_saxi_i.start_w
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.pri_rq[3:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.enc_rq[2:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.mux_sel[1:0]
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.chn_sel[3:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.chn_grant[3:0]
@c00022
x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
@28
(0)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(1)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(2)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(3)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(4)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(5)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(6)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(7)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
@1401200
-group_end
@c08022
x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
@28
(0)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(1)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(2)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(3)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(4)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(5)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(6)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
(7)x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wa[7:0]
@1401200
-group_end
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wr[1:0]
@8022
x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_wr[1:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.dav_r
x393_dut.x393_i.sensors393_i.histogram_saxi_i.buf_full
x393_dut.x393_i.sensors393_i.histogram_saxi_i.dav
@8028
x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_rd[1:0]
@8022
x393_dut.x393_i.sensors393_i.histogram_saxi_i.page_ra[7:0]
@200
-sens_histogram_mux
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.dv
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_histogram_mux_i.dv
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_histogram_mux_i.dv
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_histogram_mux_i.dv
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.dav_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.start_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.mux_sel[1:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.enc_rq[2:0]
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.pri_rq[3:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.dav0
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.chn_grant[3:0]
@200
-
-sens_histogram_singl_chn2
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_grant
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.en_rq_start
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rq_r
@800023
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@29
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@1001203
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_odd
@808022
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
@1009202
-group_end
@c08022
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
@1401200
-group_end
@200
-sens_histogram_snglclk
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out
@1000200
-histograms
@c00200
@c00200
-event_logger
-event_logger
@22
@22
...
@@ -2563,7 +2776,7 @@ x393_dut.IMU_SDA
...
@@ -2563,7 +2776,7 @@ x393_dut.IMU_SDA
x393_dut.IMU_TAPS[5:1]
x393_dut.IMU_TAPS[5:1]
@1401200
@1401200
-IMU_
-IMU_
@
8
00200
@
c
00200
-camsync_ext_int
-camsync_ext_int
@c00022
@c00022
x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
x393_dut.x393_i.timing393_i.camsync393_i.gpio_in[9:0]
...
@@ -2657,9 +2870,7 @@ x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_mask_w[9:0]
...
@@ -2657,9 +2870,7 @@ x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_mask_w[9:0]
@28
@28
x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition
x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition
x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_filtered
x393_dut.x393_i.timing393_i.camsync393_i.trigger_condition_filtered
@29
x393_dut.x393_i.timing393_i.camsync393_i.rcv_run_or_deaf
x393_dut.x393_i.timing393_i.camsync393_i.rcv_run_or_deaf
@28
x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_pclk
x393_dut.x393_i.timing393_i.camsync393_i.ext_int_mode_pclk
x393_dut.x393_i.timing393_i.camsync393_i.triggered_mode
x393_dut.x393_i.timing393_i.camsync393_i.triggered_mode
@22
@22
...
@@ -2705,7 +2916,7 @@ x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
...
@@ -2705,7 +2916,7 @@ x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
-group_end
-group_end
-group_end
-group_end
-group_end
-group_end
@1
000
200
@1
401
200
-camsync_ext_int
-camsync_ext_int
@800200
@800200
-sequencers_0
-sequencers_0
...
...
dct_tests_01.sav
View file @
2478e215
[*]
[*]
[*] GTKWave Analyzer v3.3.
66 (w)1999-2015
BSI
[*] GTKWave Analyzer v3.3.
78 (w)1999-2016
BSI
[*] Tue Dec
6 17:55:24
2016
[*] Tue Dec
13 19:43:18
2016
[*]
[*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-201612
0610551469
1.fst"
[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-201612
1312392150
1.fst"
[dumpfile_mtime] "Tue Dec
6 17:55:14
2016"
[dumpfile_mtime] "Tue Dec
13 19:39:21
2016"
[dumpfile_size] 103
48
[dumpfile_size] 103
386
[savefile] "/home/eyesis/git/x393-neon/dct_tests_01.sav"
[savefile] "/home/eyesis/git/x393-neon/dct_tests_01.sav"
[timestart] 0
[timestart] 0
[size] 1814 1171
[size] 1814 1171
[pos] 19
37
0
[pos] 19
12
0
*-1
8.387537 1752
000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-1
9.687614 3465
000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] dct_tests_01.
[treeopen] dct_tests_01.
[treeopen] dct_tests_01.dct_iv8_1d_i.
[treeopen] dct_tests_01.dct_iv8_1d_i.
[treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.
[treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.
[treeopen] dct_tests_01.dct_iv_8x8_i.
[treeopen] dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.
[treeopen] dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.
[sst_width] 204
[sst_width] 204
[signals_width] 30
5
[signals_width] 30
2
[sst_expanded] 1
[sst_expanded] 1
[sst_vpaned_height] 344
[sst_vpaned_height] 344
@
8
00200
@
c
00200
-top
-top
@2
5
@2
4
dct_tests_01.i
dct_tests_01.i
dct_tests_01.j
dct_tests_01.j
@28
@28
...
@@ -87,10 +90,82 @@ dct_tests_01.y_we
...
@@ -87,10 +90,82 @@ dct_tests_01.y_we
dct_tests_01.phase_y[3:0]
dct_tests_01.phase_y[3:0]
dct_tests_01.y_dct[23:0]
dct_tests_01.y_dct[23:0]
dct_tests_01.y_out[23:0]
dct_tests_01.y_out[23:0]
@1000200
dct_tests_01.dct_iv8_1d_i.y_index[2:0]
@1401200
-top
-top
@800200
@c00200
-2d-1d
@28
dct_tests_01.start
@420
dct_tests_01.x_in[23:0]
@8420
dct_tests_01.x_in[23:0]
@22
dct_tests_01.x_out[23:0]
@8420
dct_tests_01.x_out[23:0]
@28
dct_tests_01.dct_iv8_1d_i.start
@22
dct_tests_01.dct_iv8_1d_i.phase_cnt[3:0]
@8420
dct_tests_01.dct_iv8_1d_i.d_in[23:0]
@28
dct_tests_01.dct_iv8_1d_i.pre2_start_out
@8420
[color] 7
dct_tests_01.dct_iv8_1d_i.dout[23:0]
dct_tests_01.y_dct[23:0]
@22
dct_tests_01.y_wa[2:0]
@28
dct_tests_01.y_we
dct_tests_01.dct_iv8_1d_i.en_out
dct_tests_01.dct_iv8_1d_i.en_out_r
@22
dct_tests_01.dct_iv8_1d_i.y_index[2:0]
dct_tests_01.y_ra[2:0]
@28
dct_tests_01.y_dv
@8420
dct_tests_01.y_out[23:0]
@28
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.start
@22
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.phase_cnt[3:0]
@8420
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.d_in[23:0]
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.dout[23:0]
@28
[color] 7
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.en_out
@22
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.y_index[2:0]
@28
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.start
@22
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.phase_cnt[3:0]
@8420
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.d_in[23:0]
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.dout[23:0]
@28
[color] 7
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.en_out
@22
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.y_index[2:0]
@200
-
@1401200
-2d-1d
@c00200
-dct_iv8_1d
-dct_iv8_1d
@22
[color] 2
dct_tests_01.dct_iv8_1d_i.phase_cnt[3:0]
@28
dct_tests_01.dct_iv8_1d_i.en_out
dct_tests_01.dct_iv8_1d_i.run_out
@c08022
@c08022
dct_tests_01.phase_out[3:0]
dct_tests_01.phase_out[3:0]
@28
@28
...
@@ -105,8 +180,6 @@ dct_tests_01.dct_iv8_1d_i.start
...
@@ -105,8 +180,6 @@ dct_tests_01.dct_iv8_1d_i.start
dct_tests_01.dct_iv8_1d_i.restart
dct_tests_01.dct_iv8_1d_i.restart
dct_tests_01.dct_iv8_1d_i.clk
dct_tests_01.dct_iv8_1d_i.clk
@8022
@8022
[color] 2
dct_tests_01.dct_iv8_1d_i.phase_cnt[3:0]
dct_tests_01.dct_iv8_1d_i.d_in[23:0]
dct_tests_01.dct_iv8_1d_i.d_in[23:0]
dct_tests_01.dct_iv8_1d_i.dsp_ain_1[24:0]
dct_tests_01.dct_iv8_1d_i.dsp_ain_1[24:0]
@28
@28
...
@@ -124,8 +197,8 @@ dct_tests_01.dct_iv8_1d_i.dsp_ced_1
...
@@ -124,8 +197,8 @@ dct_tests_01.dct_iv8_1d_i.dsp_ced_1
@22
@22
dct_tests_01.dct_iv8_1d_i.dsp_cin_1[47:0]
dct_tests_01.dct_iv8_1d_i.dsp_cin_1[47:0]
@28
@28
dct_tests_01.dct_iv8_1d_i.dsp_cec_1
dct_tests_01.dct_iv8_1d_i.dsp_neg_m_1
dct_tests_01.dct_iv8_1d_i.dsp_neg_m_1
dct_tests_01.dct_iv8_1d_i.dsp_cec_1
dct_tests_01.dct_iv8_1d_i.dsp_post_add_1
dct_tests_01.dct_iv8_1d_i.dsp_post_add_1
dct_tests_01.dct_iv8_1d_i.dsp_accum_1
dct_tests_01.dct_iv8_1d_i.dsp_accum_1
@22
@22
...
@@ -238,7 +311,335 @@ dct_tests_01.dct_iv8_1d_i.pre2_start_out
...
@@ -238,7 +311,335 @@ dct_tests_01.dct_iv8_1d_i.pre2_start_out
dct_tests_01.dct_iv8_1d_i.rst
dct_tests_01.dct_iv8_1d_i.rst
dct_tests_01.dct_iv8_1d_i.run_in
dct_tests_01.dct_iv8_1d_i.run_in
dct_tests_01.dct_iv8_1d_i.run_out
dct_tests_01.dct_iv8_1d_i.run_out
@1
000
200
@1
401
200
-dct_iv8_1d
-dct_iv8_1d
@800200
-st22d_test
@28
dct_tests_01.CLK
dct_tests_01.RST
[color] 2
dct_tests_01.start
[color] 2
dct_tests_01.start2
@c00022
dct_tests_01.x_in_2d[23:0]
@28
(0)dct_tests_01.x_in_2d[23:0]
(1)dct_tests_01.x_in_2d[23:0]
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(3)dct_tests_01.x_in_2d[23:0]
(4)dct_tests_01.x_in_2d[23:0]
(5)dct_tests_01.x_in_2d[23:0]
(6)dct_tests_01.x_in_2d[23:0]
(7)dct_tests_01.x_in_2d[23:0]
(8)dct_tests_01.x_in_2d[23:0]
(9)dct_tests_01.x_in_2d[23:0]
(10)dct_tests_01.x_in_2d[23:0]
(11)dct_tests_01.x_in_2d[23:0]
(12)dct_tests_01.x_in_2d[23:0]
(13)dct_tests_01.x_in_2d[23:0]
(14)dct_tests_01.x_in_2d[23:0]
(15)dct_tests_01.x_in_2d[23:0]
(16)dct_tests_01.x_in_2d[23:0]
(17)dct_tests_01.x_in_2d[23:0]
(18)dct_tests_01.x_in_2d[23:0]
(19)dct_tests_01.x_in_2d[23:0]
(20)dct_tests_01.x_in_2d[23:0]
(21)dct_tests_01.x_in_2d[23:0]
(22)dct_tests_01.x_in_2d[23:0]
(23)dct_tests_01.x_in_2d[23:0]
@1401200
-group_end
@c08420
dct_tests_01.x_in_2d[23:0]
@28
(0)dct_tests_01.x_in_2d[23:0]
(1)dct_tests_01.x_in_2d[23:0]
(2)dct_tests_01.x_in_2d[23:0]
(3)dct_tests_01.x_in_2d[23:0]
(4)dct_tests_01.x_in_2d[23:0]
(5)dct_tests_01.x_in_2d[23:0]
(6)dct_tests_01.x_in_2d[23:0]
(7)dct_tests_01.x_in_2d[23:0]
(8)dct_tests_01.x_in_2d[23:0]
(9)dct_tests_01.x_in_2d[23:0]
(10)dct_tests_01.x_in_2d[23:0]
(11)dct_tests_01.x_in_2d[23:0]
(12)dct_tests_01.x_in_2d[23:0]
(13)dct_tests_01.x_in_2d[23:0]
(14)dct_tests_01.x_in_2d[23:0]
(15)dct_tests_01.x_in_2d[23:0]
(16)dct_tests_01.x_in_2d[23:0]
(17)dct_tests_01.x_in_2d[23:0]
(18)dct_tests_01.x_in_2d[23:0]
(19)dct_tests_01.x_in_2d[23:0]
(20)dct_tests_01.x_in_2d[23:0]
(21)dct_tests_01.x_in_2d[23:0]
(22)dct_tests_01.x_in_2d[23:0]
(23)dct_tests_01.x_in_2d[23:0]
@1401200
-group_end
@28
dct_tests_01.pre_busy_2d
dct_tests_01.pre_last_in_2d
dct_tests_01.pre_first_out_2d
dct_tests_01.dv_2d
@420
dct_tests_01.d_out_2d[23:0]
@8420
dct_tests_01.d_out_2d[23:0]
@28
dct_tests_01.dv_2dr
@22
dct_tests_01.d_out_2dr[23:0]
@8421
dct_tests_01.d_out_2dr[23:0]
@200
-
@800200
-dct_iv_8x8
@28
dct_tests_01.dct_iv_8x8_i.clk
dct_tests_01.dct_iv_8x8_i.start
dct_tests_01.dct_iv_8x8_i.pre_last_in
dct_tests_01.dct_iv_8x8_i.pre_busy
dct_tests_01.dct_iv_8x8_i.x_run
@c00022
dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
(1)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
(2)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
(3)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
(4)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
(5)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
@1401200
-group_end
@28
dct_tests_01.dct_iv_8x8_i.dcth_phin_start
@22
dct_tests_01.dct_iv_8x8_i.dcth_phin_run
@c00022
dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
(1)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
(2)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
(3)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
(4)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
(5)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
(6)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
@1401200
-group_end
@22
dct_tests_01.dct_iv_8x8_i.x_ra0[2:0]
dct_tests_01.dct_iv_8x8_i.x_ra1[2:0]
@28
dct_tests_01.dct_iv_8x8_i.dcth_en0
dct_tests_01.dct_iv_8x8_i.dcth_start_0_r
@22
dct_tests_01.dct_iv_8x8_i.dcth_xin0[23:0]
@28
dct_tests_01.dct_iv_8x8_i.dcth_en_out0
@22
dct_tests_01.dct_iv_8x8_i.dcth_yindex0[2:0]
dct_tests_01.dct_iv_8x8_i.dcth_dout0[23:0]
@200
-
@28
dct_tests_01.dct_iv_8x8_i.dcth_en1
dct_tests_01.dct_iv_8x8_i.dcth_start_1_r
@22
dct_tests_01.dct_iv_8x8_i.dcth_xin1[23:0]
@28
dct_tests_01.dct_iv_8x8_i.dcth_en_out1
@22
dct_tests_01.dct_iv_8x8_i.dcth_yindex1[2:0]
dct_tests_01.dct_iv_8x8_i.dcth_dout1[23:0]
@200
-
@22
dct_tests_01.dct_iv_8x8_i.transpose_start
@28
dct_tests_01.dct_iv_8x8_i.transpose_in_run
@22
dct_tests_01.dct_iv_8x8_i.transpose_w_page[1:0]
[color] 3
dct_tests_01.dct_iv_8x8_i.transpose_cntr[6:0]
@28
dct_tests_01.dct_iv_8x8_i.transpose_wa_decr
@22
dct_tests_01.dct_iv_8x8_i.transpose_wa_low[2:0]
dct_tests_01.dct_iv_8x8_i.transpose_wa_high[4:0]
dct_tests_01.dct_iv_8x8_i.transpose_wa[7:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.transpose_we[1:0]
@22
[color] 2
dct_tests_01.dct_iv_8x8_i.transpose_debug_di[7:0]
@28
dct_tests_01.dct_iv_8x8_i.transpose_out_start
@800022
dct_tests_01.dct_iv_8x8_i.transpose_out_run[2:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.transpose_out_run[2:0]
(1)dct_tests_01.dct_iv_8x8_i.transpose_out_run[2:0]
(2)dct_tests_01.dct_iv_8x8_i.transpose_out_run[2:0]
@1001200
-group_end
@c00028
dct_tests_01.dct_iv_8x8_i.transpose_r_page[1:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.transpose_r_page[1:0]
(1)dct_tests_01.dct_iv_8x8_i.transpose_r_page[1:0]
@1401200
-group_end
@c00022
dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
(1)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
(2)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
(3)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
(4)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
(5)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
(6)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
@1401200
-group_end
@22
[color] 5
dct_tests_01.dct_iv_8x8_i.transpose_ra[7:0]
@8420
dct_tests_01.dct_iv_8x8_i.transpose_reg[23:0]
dct_tests_01.dct_iv_8x8_i.transpose_out[23:0]
@c00022
dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
(1)dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
(2)dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
(3)dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
(4)dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
(5)dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
(6)dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
(7)dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
@1401200
-group_end
@22
dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
@c08022
dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
(1)dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
(2)dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
(3)dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
(4)dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
(5)dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
(6)dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
(7)dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
@1401200
-group_end
@22
dct_tests_01.dct_iv_8x8_i.t_wa[3:0]
@28
dct_tests_01.dct_iv_8x8_i.t_we0
dct_tests_01.dct_iv_8x8_i.t_we1
dct_tests_01.dct_iv_8x8_i.dctv_start_0_r
dct_tests_01.dct_iv_8x8_i.dctv_start_1_r
dct_tests_01.dct_iv_8x8_i.dctv_en0
dct_tests_01.dct_iv_8x8_i.dctv_en1
dct_tests_01.dct_iv_8x8_i.dctv_phin_start
dct_tests_01.dct_iv_8x8_i.dctv_phin_run
@c00022
[color] 2
dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
(1)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
(2)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
(3)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
(4)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
(5)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
(6)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
@1401200
-group_end
@8022
dct_tests_01.dct_iv_8x8_i.t_ra0[2:0]
dct_tests_01.dct_iv_8x8_i.t_ra1[2:0]
@22
dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
dct_tests_01.dct_iv_8x8_i.dctv_debug_xin0[7:0]
@8022
dct_tests_01.dct_iv_8x8_i.dctv_debug_xin0[7:0]
@22
dct_tests_01.dct_iv_8x8_i.dctv_debug_xin1[7:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_start_0_r
dct_tests_01.dct_iv_8x8_i.dctv_start_1_r
dct_tests_01.dct_iv_8x8_i.dctv_en0
dct_tests_01.dct_iv_8x8_i.dctv_en1
dct_tests_01.dct_iv_8x8_i.dctv_en_out0
dct_tests_01.dct_iv_8x8_i.dctv_en_out1
@8420
dct_tests_01.dct_iv_8x8_i.dctv_dout0[23:0]
@c00022
dct_tests_01.dct_iv_8x8_i.dctv_yindex0[2:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.dctv_yindex0[2:0]
(1)dct_tests_01.dct_iv_8x8_i.dctv_yindex0[2:0]
(2)dct_tests_01.dct_iv_8x8_i.dctv_yindex0[2:0]
@1401200
-group_end
@8420
dct_tests_01.dct_iv_8x8_i.dctv_dout1[23:0]
@22
dct_tests_01.dct_iv_8x8_i.dctv_yindex1[2:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_out_start
dct_tests_01.dct_iv_8x8_i.dctv_out_run
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_cntr[6:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.dctv_out_we_1[1:0]
dct_tests_01.dct_iv_8x8_i.dctv_out_sel
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_wa_1[3:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_out_start_1
dct_tests_01.dct_iv_8x8_i.dctv_out_run_1
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1[6:0]
dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1_w[3:0]
@420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_1[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_1[23:0]
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_1[2:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_out_we_2
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_wa_2[1:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_out_run_2
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_ra_2[6:0]
@420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_2[2:0]
@1000200
-dct_iv_8x8
@800200
-dct_iv_8x8r
@200
-
@1000200
-dct_iv_8x8r
-st22d_test
[pattern_trace] 1
[pattern_trace] 1
[pattern_trace] 0
[pattern_trace] 0
dsp/dct_iv.ods
View file @
2478e215
No preview for this file type
dsp/dct_iv8_1d.v
View file @
2478e215
...
@@ -71,11 +71,10 @@ module dct_iv8_1d#(
...
@@ -71,11 +71,10 @@ module dct_iv8_1d#(
output
[
OUT_WIDTH
-
1
:
0
]
dout
,
output
[
OUT_WIDTH
-
1
:
0
]
dout
,
output
reg
pre2_start_out
,
// 2 clock cycle before Y0 output, full dout sequence
output
reg
pre2_start_out
,
// 2 clock cycle before Y0 output, full dout sequence
// start_out-x-Y0-x-Y7-x-Y4-x-Y3-x-Y1-x-Y6-x-Y2-x-Y5
// start_out-x-Y0-x-Y7-x-Y4-x-Y3-x-Y1-x-Y6-x-Y2-x-Y5
output
reg
en_out
// valid at the same time slot as pre2_start_out (goes active with pre2_start_out)
output
en_out
,
// valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 2 ahead of data
output
reg
[
2
:
0
]
y_index
// for simulation - valid with dout - index of the data output
)
;
)
;
// X6-X7-X5-X2-X1-X3-X0-X4-*-X5-X1-X2-*-X4-X7-*
// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*
// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*
localparam
RSHIFT1
=
2
;
// safe right shift for stage 1
localparam
RSHIFT1
=
2
;
// safe right shift for stage 1
localparam
STAGE1_RSHIFT
=
COSINE_SHIFT
+
(
WIDTH
-
A_WIDTH
)
+
RSHIFT1
;
// divide by 4 in stage 1 - never saturates
localparam
STAGE1_RSHIFT
=
COSINE_SHIFT
+
(
WIDTH
-
A_WIDTH
)
+
RSHIFT1
;
// divide by 4 in stage 1 - never saturates
...
@@ -132,6 +131,11 @@ module dct_iv8_1d#(
...
@@ -132,6 +131,11 @@ module dct_iv8_1d#(
reg
run_in
;
// receiving input data
reg
run_in
;
// receiving input data
reg
restart
;
// restarting next block if en was active at phase=14;
reg
restart
;
// restarting next block if en was active at phase=14;
reg
run_out
;
// running output data
reg
run_out
;
// running output data
reg
en_out_r
;
reg
en_out_r2
;
assign
en_out
=
en_out_r
;
assign
dsp_ain_2
=
dsp_p_1
[
STAGE1_RSHIFT
+:
A_WIDTH
]
;
assign
dsp_ain_2
=
dsp_p_1
[
STAGE1_RSHIFT
+:
A_WIDTH
]
;
...
@@ -147,6 +151,23 @@ module dct_iv8_1d#(
...
@@ -147,6 +151,23 @@ module dct_iv8_1d#(
wire
din_zero
=
~
(
|
d_in
)
;
wire
din_zero
=
~
(
|
d_in
)
;
assign
dsp_cin_1
=
{{
P_WIDTH
-
WIDTH
-
COSINE_SHIFT
{
d_in
[
WIDTH
-
1
]
}},
d_in
,~
d_in
[
WIDTH
-
1
]
^
din_zero
,{
COSINE_SHIFT
-
1
{
d_in
[
WIDTH
-
1
]
}}};
assign
dsp_cin_1
=
{{
P_WIDTH
-
WIDTH
-
COSINE_SHIFT
{
d_in
[
WIDTH
-
1
]
}},
d_in
,~
d_in
[
WIDTH
-
1
]
^
din_zero
,{
COSINE_SHIFT
-
1
{
d_in
[
WIDTH
-
1
]
}}};
always
@
(
posedge
clk
)
begin
en_out_r2
<=
en_out_r
;
if
(
en_out_r2
)
begin
case
(
phase_cnt
[
3
:
1
])
3'h0
:
y_index
<=
0
;
3'h1
:
y_index
<=
7
;
3'h2
:
y_index
<=
4
;
3'h3
:
y_index
<=
3
;
3'h4
:
y_index
<=
1
;
3'h5
:
y_index
<=
6
;
3'h6
:
y_index
<=
2
;
3'h7
:
y_index
<=
5
;
endcase
end
else
begin
y_index
<=
'bx
;
end
end
//register files
//register files
assign
dsp_din_1
=
dsp_din_1_ram
[
dsp_din_1_ra
]
;
assign
dsp_din_1
=
dsp_din_1_ram
[
dsp_din_1_ra
]
;
...
@@ -173,7 +194,7 @@ module dct_iv8_1d#(
...
@@ -173,7 +194,7 @@ module dct_iv8_1d#(
pre2_start_out
<=
run_out
&&
(
phase_cnt
==
14
)
;
pre2_start_out
<=
run_out
&&
(
phase_cnt
==
14
)
;
en_out
<=
run_out
&&
!
phase_cnt
[
0
]
;
en_out
_r
<=
run_out
&&
!
phase_cnt
[
0
]
;
// Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand
// Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand
case
(
phase_cnt
)
case
(
phase_cnt
)
...
...
dsp/dct_iv_8x8.v
0 → 100644
View file @
2478e215
/*!
* <b>Module:</b>dct_iv_8x8
* @file dct_iv_8x8.v
* @date 2016-12-08
* @author Andrey Filippov
*
* @brief 2-d DCT-IV implementation, 1 clock/data word. Input in scanline order, output - transposed
*
* @copyright Copyright (c) 2016 Elphel, Inc.
*
* <b>License:</b>
*
*dct_iv_8x8.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dct_iv_8x8.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale
1
ns
/
1
ps
module
dct_iv_8x8
#(
parameter
INPUT_WIDTH
=
25
,
parameter
OUT_WIDTH
=
25
,
parameter
OUT_RSHIFT1
=
1
,
// overall right shift of the result from input, aligned by MSB for pass1 (>=3 will never cause saturation)
parameter
OUT_RSHIFT2
=
1
,
// if sum OUT_RSHIFT1+OUT_RSHIFT2 == 2, direct*reverse == ident (may use 3, -1) or 3,0 with wider output and saturate
parameter
TRANSPOSE_WIDTH
=
25
,
// transpose memory width
parameter
DSP_B_WIDTH
=
18
,
parameter
DSP_A_WIDTH
=
25
,
parameter
DSP_P_WIDTH
=
48
,
parameter
COSINE_SHIFT
=
17
,
parameter
COS_01_32
=
130441
,
// int(round((1<<17) * cos( 1*pi/32)))
parameter
COS_03_32
=
125428
,
// int(round((1<<17) * cos( 3*pi/32)))
parameter
COS_04_32
=
121095
,
// int(round((1<<17) * cos( 4*pi/32)))
parameter
COS_05_32
=
115595
,
// int(round((1<<17) * cos( 5*pi/32)))
parameter
COS_07_32
=
101320
,
// int(round((1<<17) * cos( 7*pi/32)))
parameter
COS_08_32
=
92682
,
// int(round((1<<17) * cos( 8*pi/32)))
parameter
COS_09_32
=
83151
,
// int(round((1<<17) * cos( 9*pi/32)))
parameter
COS_11_32
=
61787
,
// int(round((1<<17) * cos(11*pi/32)))
parameter
COS_12_32
=
50159
,
// int(round((1<<17) * cos(12*pi/32)))
parameter
COS_13_32
=
38048
,
// int(round((1<<17) * cos(13*pi/32)))
parameter
COS_15_32
=
12847
// int(round((1<<17) * cos(15*pi/32)))
)
(
input
clk
,
//!< system clock, posedge
input
rst
,
//!< sync reset
input
start
,
//!< single-cycle start pulse that goes with the first pixel data.
// Next data should be sent in bursts of 8, pause of 8 - total 128 cycles
input
signed
[
INPUT_WIDTH
-
1
:
0
]
xin
,
//!< input data
output
pre_last_in
,
//!< output high during input of the pre-last of 64 pixels in a 8x8 block (next can be start
output
reg
pre_first_out
,
//!< 1 cycle ahead of the first output in a 64 block
output
reg
dv
,
//!< data output valid. WAS: Will go high on the 94-th cycle after the start
output
signed
[
OUT_WIDTH
-
1
:
0
]
d_out
,
//!< output data
output
reg
pre_busy
)
;
//!< start should come each 64-th cycle (next after pre_last_in), and not after pre_busy)
// 1. Two 16xINPUT_WIDTH memories to feed two of the 'horizontal' 1-dct - they should provide outputs shifted by 1 clock
// 2. of the horizontal DCTs
// 3. common transpose memory plus 2 input reorder memory for each of the vertical DCT
// 4. 2 of the vertical DCTs
// 5. small memory to combine/reorder outputs (2 stages as 1 x16 memory is not enough)
// TODO make a version that uses common transpose memory (twice width) and simultaneously calculates dst-iv (invert time sequence, alternate sign)
// That can be used for lateral chromatic aberration (shift in time domain). Reverse transform does not need it - will always be just dct-iv
reg
x_run
;
reg
[
5
:
0
]
x_wa
;
wire
dcth_phin_start
=
x_run
&&
(
x_wa
[
5
:
0
]
==
6
)
;
reg
dcth_phin_run
;
reg
dcth_en0
;
reg
dcth_en1
;
reg
[
6
:
0
]
dcth_phin
;
reg
[
2
:
0
]
x_ra0
;
reg
[
2
:
0
]
x_ra1
;
reg
signed
[
INPUT_WIDTH
-
1
:
0
]
x_ram0
[
0
:
7
]
;
reg
signed
[
INPUT_WIDTH
-
1
:
0
]
x_ram1
[
0
:
7
]
;
reg
signed
[
INPUT_WIDTH
-
1
:
0
]
dcth_xin0
;
reg
signed
[
INPUT_WIDTH
-
1
:
0
]
dcth_xin1
;
wire
signed
[
TRANSPOSE_WIDTH
-
1
:
0
]
dcth_dout0
;
wire
signed
[
TRANSPOSE_WIDTH
-
1
:
0
]
dcth_dout1
;
// wire dcth_pre2_start_out0;
// wire dcth_pre2_start_out1;
wire
dcth_en_out0
;
wire
dcth_en_out1
;
wire
dcth_start_0_w
=
dcth_phin_run
&&
(
dcth_phin
[
6
:
0
]
==
0
)
;
wire
dcth_start_1_w
=
dcth_phin_run
&&
(
dcth_phin
[
6
:
0
]
==
9
)
;
reg
dcth_start_0_r
;
reg
dcth_start_1_r
;
reg
[
1
:
0
]
transpose_w_page
;
reg
[
6
:
0
]
transpose_cntr
;
// transpose memory counter, [6] == 1 when the last page is being finished
reg
transpose_in_run
;
// wire transpose_start = dcth_phin_run && (dcth_phin [6:0] == 7'h10);
wire
transpose_start
=
dcth_phin_run
&&
(
dcth_phin
[
6
:
0
]
==
7'h11
)
;
// wire transpose_start = dcth_phin_run && (dcth_phin [6:0] == 7'h12);
reg
[
2
:
0
]
transpose_wa_low
;
// [2:0] transpose memory low address bits, [3] - other group (of 16)
reg
[
4
:
0
]
transpose_wa_high
;
// high bits of transpose memory write address
wire
[
7
:
0
]
transpose_wa
=
{
transpose_wa_high
,
transpose_wa_low
};
wire
transpose_wa_decr
=
(
transpose_cntr
[
0
]
&
~
transpose_cntr
[
3
])
;
reg
[
1
:
0
]
transpose_we
;
// [1]
wire
[
TRANSPOSE_WIDTH
-
1
:
0
]
transpose_di
=
transpose_cntr
[
0
]
?
dcth_dout0
:
dcth_dout1
;
reg
[
TRANSPOSE_WIDTH
-
1
:
0
]
transpose_ram
[
0
:
255
]
;
wire
[
2
:
0
]
dcth_yindex0
;
wire
[
2
:
0
]
dcth_yindex1
;
wire
[
7
:
0
]
transpose_debug_di
=
{
transpose_wa_high
,
transpose_cntr
[
0
]
?
dcth_yindex0
:
dcth_yindex1
};
reg
[
7
:
0
]
transpose_debug_ram
[
0
:
255
]
;
reg
[
6
:
0
]
transpose_rcntr
;
// transpose read memory counter, [6] == 1 when the last page is being finished
reg
[
2
:
0
]
transpose_out_run
;
wire
transpose_out_start
=
transpose_in_run
&&
(
transpose_cntr
[
6
:
0
]
==
7'h34
)
;
// 7'h33 is actual minimum
reg
[
1
:
0
]
transpose_r_page
;
reg
signed
[
TRANSPOSE_WIDTH
-
1
:
0
]
transpose_reg
;
// internal BRAM register
reg
signed
[
TRANSPOSE_WIDTH
-
1
:
0
]
transpose_out
;
// output BRAM register
reg
[
7
:
0
]
transpose_debug_reg
;
// internal BRAM register
reg
[
7
:
0
]
transpose_debug_out
;
// output BRAM register
wire
[
7
:
0
]
transpose_ra
=
{
transpose_r_page
,
transpose_rcntr
[
2
:
0
]
,
transpose_rcntr
[
5
:
3
]
};
reg
[
3
:
0
]
t_wa
;
wire
t_we0
=
transpose_out_run
[
2
]
&&
!
t_wa
[
3
]
;
wire
t_we1
=
transpose_out_run
[
2
]
&&
t_wa
[
3
]
;
reg
signed
[
TRANSPOSE_WIDTH
-
1
:
0
]
t_ram0
[
0
:
7
]
;
reg
signed
[
TRANSPOSE_WIDTH
-
1
:
0
]
t_ram1
[
0
:
7
]
;
reg
signed
[
TRANSPOSE_WIDTH
-
1
:
0
]
dctv_xin0
;
reg
signed
[
TRANSPOSE_WIDTH
-
1
:
0
]
dctv_xin1
;
reg
signed
[
7
:
0
]
t_debug_ram0
[
0
:
7
]
;
reg
signed
[
7
:
0
]
t_debug_ram1
[
0
:
7
]
;
reg
signed
[
7
:
0
]
dctv_debug_xin0
;
// SuppressThisWarning VEditor - simulation only
reg
signed
[
7
:
0
]
dctv_debug_xin1
;
// SuppressThisWarning VEditor - simulation only
wire
signed
[
OUT_WIDTH
-
1
:
0
]
dctv_dout0
;
wire
signed
[
OUT_WIDTH
-
1
:
0
]
dctv_dout1
;
wire
dctv_en_out0
;
wire
dctv_en_out1
;
wire
[
2
:
0
]
dctv_yindex0
;
wire
[
2
:
0
]
dctv_yindex1
;
wire
dctv_phin_start
=
transpose_out_run
&&
(
transpose_rcntr
[
5
:
0
]
==
8
)
;
reg
dctv_phin_run
;
reg
dctv_en0
;
reg
dctv_en1
;
reg
[
6
:
0
]
dctv_phin
;
reg
[
2
:
0
]
t_ra0
;
reg
[
2
:
0
]
t_ra1
;
wire
dctv_start_0_w
=
dctv_phin_run
&&
(
dctv_phin
[
6
:
0
]
==
0
)
;
wire
dctv_start_1_w
=
dctv_phin_run
&&
(
dctv_phin
[
6
:
0
]
==
9
)
;
reg
dctv_start_0_r
;
reg
dctv_start_1_r
;
reg
pre_last_in_r
;
reg
[
6
:
0
]
dctv_out_cntr
;
// count output data from second (vertical) pass (bit 6 - stopping)
reg
dctv_out_run
;
//
// wire dctv_out_start = dctv_phin [6:0] == 'h10;
wire
dctv_out_start
=
dctv_phin
[
6
:
0
]
==
'h11
;
reg
[
3
:
0
]
dctv_out_wa_1
;
reg
[
1
:
0
]
dctv_out_we_1
;
reg
dctv_out_sel
;
// select DCTv channel output;
reg
signed
[
OUT_WIDTH
-
1
:
0
]
dctv_out_ram_1
[
0
:
15
]
;
reg
[
2
:
0
]
dctv_out_debug_ram_1
[
0
:
15
]
;
reg
[
6
:
0
]
dctv_out_ra_1
;
wire
[
3
:
0
]
dctv_out_ra_1_w
=
{
dctv_out_ra_1
[
3
:
1
]
,
~
dctv_out_ra_1
[
0
]
};
wire
dctv_out_start_1
=
dctv_out_cntr
[
6
:
0
]
==
'h0c
;
// 'h0b;
reg
dctv_out_run_1
;
reg
signed
[
OUT_WIDTH
-
1
:
0
]
dctv_out_reg_1
;
reg
[
2
:
0
]
dctv_out_debug_reg_1
;
reg
signed
[
OUT_WIDTH
-
1
:
0
]
dctv_out_ram_2
[
0
:
3
]
;
reg
[
2
:
0
]
dctv_out_debug_ram_2
[
0
:
3
]
;
reg
dctv_out_we_2
;
reg
[
1
:
0
]
dctv_out_wa_2
;
reg
[
6
:
0
]
dctv_out_ra_2
;
wire
dctv_out_start_2
=
dctv_out_ra_1
[
6
:
0
]
==
2
;
reg
dctv_out_run_2
;
reg
signed
[
OUT_WIDTH
-
1
:
0
]
dctv_out_reg_2
;
reg
[
2
:
0
]
dctv_out_debug_reg_2
;
// SuppressThisWarning VEditor - simulation only
assign
d_out
=
dctv_out_reg_2
;
assign
pre_last_in
=
pre_last_in_r
;
always
@
(
posedge
clk
)
begin
if
(
rst
)
x_run
<=
0
;
else
if
(
start
)
x_run
<=
1
;
else
if
(
&
x_wa
[
5
:
0
])
x_run
<=
0
;
if
(
!
x_run
)
x_wa
<=
0
;
else
x_wa
<=
x_wa
+
1
;
pre_last_in_r
<=
x_run
&&
(
x_wa
[
5
:
0
]
==
'h3d
)
;
if
(
rst
)
pre_busy
<=
0
;
else
if
(
pre_last_in_r
)
pre_busy
<=
1
;
else
if
(
dcth_phin
[
5
:
0
]
==
5
)
pre_busy
<=
0
;
// check actual?
if
(
rst
)
dcth_phin_run
<=
0
;
else
if
(
dcth_phin_start
)
dcth_phin_run
<=
1
;
else
if
(
dcth_phin
[
6
:
0
]
==
7'h48
)
dcth_phin_run
<=
0
;
// check actual?
if
(
!
dcth_phin_run
||
dcth_phin_start
)
dcth_phin
<=
0
;
else
dcth_phin
<=
dcth_phin
+
1
;
if
(
rst
)
dcth_en0
<=
0
;
else
if
(
dcth_start_0_w
)
dcth_en0
<=
1
;
else
if
(
!
x_run
)
dcth_en0
<=
0
;
// maybe get rid of this signal and send start for each 8?
if
(
rst
)
dcth_en1
<=
0
;
else
if
(
dcth_start_1_w
)
dcth_en1
<=
1
;
else
if
(
dcth_phin
[
6
])
dcth_en1
<=
0
;
// maybe get rid of this signal and send start for each 8?
//write input reorder memory
if
(
x_run
&&
!
x_wa
[
3
])
x_ram0
[
x_wa
[
2
:
0
]]
<=
xin
;
if
(
x_run
&&
x_wa
[
3
])
x_ram1
[
x_wa
[
2
:
0
]]
<=
xin
;
//read input reorder memory
dcth_xin0
<=
x_ram0
[
x_ra0
[
2
:
0
]]
;
dcth_xin1
<=
x_ram1
[
x_ra1
[
2
:
0
]]
;
dcth_start_0_r
<=
dcth_start_0_w
;
dcth_start_1_r
<=
dcth_start_1_w
;
if
(
rst
)
transpose_in_run
<=
0
;
else
if
(
transpose_start
)
transpose_in_run
<=
1
;
else
if
(
transpose_cntr
[
6
:
0
]
==
7'h46
)
transpose_in_run
<=
0
;
// check actual?
if
(
!
transpose_in_run
||
transpose_start
)
transpose_cntr
<=
0
;
else
transpose_cntr
<=
transpose_cntr
+
1
;
if
(
rst
)
transpose_w_page
<=
0
;
else
if
(
transpose_in_run
&&
(
&
transpose_cntr
[
5
:
0
]))
transpose_w_page
<=
transpose_w_page
+
1
;
case
(
transpose_cntr
[
3
:
0
])
4'h0
:
transpose_wa_low
<=
0
;
4'h1
:
transpose_wa_low
<=
1
;
4'h2
:
transpose_wa_low
<=
7
;
4'h3
:
transpose_wa_low
<=
6
;
4'h4
:
transpose_wa_low
<=
4
;
4'h5
:
transpose_wa_low
<=
2
;
4'h6
:
transpose_wa_low
<=
3
;
4'h7
:
transpose_wa_low
<=
5
;
4'h8
:
transpose_wa_low
<=
1
;
4'h9
:
transpose_wa_low
<=
0
;
4'ha
:
transpose_wa_low
<=
6
;
4'hb
:
transpose_wa_low
<=
7
;
4'hc
:
transpose_wa_low
<=
2
;
4'hd
:
transpose_wa_low
<=
4
;
4'he
:
transpose_wa_low
<=
5
;
4'hf
:
transpose_wa_low
<=
3
;
endcase
transpose_wa_high
<=
{
transpose_w_page
,
transpose_cntr
[
5
:
4
]
,
transpose_cntr
[
0
]
}
-
{
transpose_wa_decr
,
1'b0
};
transpose_we
<=
{
transpose_we
[
0
]
,
dcth_en_out0
|
dcth_en_out1
};
// Write transpose memory)
if
(
transpose_we
[
1
])
transpose_ram
[
transpose_wa
]
<=
transpose_di
;
if
(
transpose_we
[
1
])
transpose_debug_ram
[
transpose_wa
]
<=
transpose_debug_di
;
// if (transpose_we[1]) $display("%d %d @%t",transpose_cntr, transpose_wa, $time) ;
if
(
rst
)
transpose_out_run
[
0
]
<=
0
;
else
if
(
transpose_out_start
)
transpose_out_run
[
0
]
<=
1
;
else
if
(
&
transpose_rcntr
[
5
:
0
])
transpose_out_run
[
0
]
<=
0
;
// check actual?
transpose_out_run
[
2
:
1
]
<=
transpose_out_run
[
1
:
0
]
;
if
(
!
transpose_out_run
[
0
]
||
transpose_out_start
)
transpose_rcntr
<=
0
;
else
transpose_rcntr
<=
transpose_rcntr
+
1
;
if
(
transpose_out_start
)
transpose_r_page
<=
transpose_w_page
;
// Read transpose memory to 2 small reorder memories, use BRAM register
if
(
transpose_out_run
[
0
])
transpose_reg
<=
transpose_ram
[
transpose_ra
]
;
if
(
transpose_out_run
[
1
])
transpose_out
<=
transpose_reg
;
if
(
transpose_out_run
[
0
])
transpose_debug_reg
<=
transpose_debug_ram
[
transpose_ra
]
;
if
(
transpose_out_run
[
1
])
transpose_debug_out
<=
transpose_debug_reg
;
if
(
!
transpose_out_run
[
2
])
t_wa
<=
0
;
else
t_wa
<=
t_wa
+
1
;
if
(
rst
)
dctv_phin_run
<=
0
;
else
if
(
dctv_phin_start
)
dctv_phin_run
<=
1
;
else
if
(
dctv_phin
[
6
:
0
]
==
7'h48
)
dctv_phin_run
<=
0
;
// check actual?
if
(
!
dctv_phin_run
||
dctv_phin_start
)
dctv_phin
<=
0
;
else
dctv_phin
<=
dctv_phin
+
1
;
if
(
rst
)
dctv_en0
<=
0
;
else
if
(
dctv_start_0_w
)
dctv_en0
<=
1
;
else
if
(
!
transpose_out_run
[
2
])
dctv_en0
<=
0
;
// maybe get rid of this signal and send satrt for each 8?
if
(
rst
)
dctv_en1
<=
0
;
else
if
(
dctv_start_1_w
)
dctv_en1
<=
1
;
else
if
(
dctv_phin
[
6
])
dctv_en1
<=
0
;
// maybe get rid of this signal and send satrt for each 8?
if
(
t_we0
||
t_we1
)
$
display
(
"%d %d"
,
transpose_rcntr
-
2
,
transpose_out
)
;
//write vertical dct input reorder memory
if
(
t_we0
)
t_ram0
[
t_wa
[
2
:
0
]]
<=
transpose_out
;
if
(
t_we1
)
t_ram1
[
t_wa
[
2
:
0
]]
<=
transpose_out
;
if
(
t_we0
)
t_debug_ram0
[
t_wa
[
2
:
0
]]
<=
transpose_debug_out
;
if
(
t_we1
)
t_debug_ram1
[
t_wa
[
2
:
0
]]
<=
transpose_debug_out
;
//read vertical dct input reorder memory
dctv_xin0
<=
t_ram0
[
t_ra0
[
2
:
0
]]
;
dctv_xin1
<=
t_ram1
[
t_ra1
[
2
:
0
]]
;
dctv_start_0_r
<=
dctv_start_0_w
;
dctv_start_1_r
<=
dctv_start_1_w
;
dctv_debug_xin0
<=
t_debug_ram0
[
t_ra0
[
2
:
0
]]
;
dctv_debug_xin1
<=
t_debug_ram1
[
t_ra1
[
2
:
0
]]
;
// Reordering data from a pair of vertical DCTs - 2 steps, 1 is not enough
if
(
rst
)
dctv_out_run
<=
0
;
else
if
(
dctv_out_start
)
dctv_out_run
<=
1
;
else
if
(
dctv_out_cntr
[
6
:
0
]
==
'h47
)
dctv_out_run
<=
0
;
if
(
!
dctv_out_run
||
dctv_out_start
)
dctv_out_cntr
<=
0
;
else
dctv_out_cntr
<=
dctv_out_cntr
+
1
;
dctv_out_we_1
<=
{
dctv_out_we_1
[
0
]
,
dctv_en_out0
|
dctv_en_out1
};
dctv_out_sel
<=
dctv_out_cntr
[
0
]
;
case
(
dctv_out_cntr
[
3
:
0
])
4'h0
:
dctv_out_wa_1
<=
0
;
4'h1
:
dctv_out_wa_1
<=
9
;
4'h2
:
dctv_out_wa_1
<=
7
;
4'h3
:
dctv_out_wa_1
<=
14
;
4'h4
:
dctv_out_wa_1
<=
4
;
4'h5
:
dctv_out_wa_1
<=
10
;
4'h6
:
dctv_out_wa_1
<=
3
;
4'h7
:
dctv_out_wa_1
<=
13
;
4'h8
:
dctv_out_wa_1
<=
1
;
4'h9
:
dctv_out_wa_1
<=
8
;
4'ha
:
dctv_out_wa_1
<=
6
;
4'hb
:
dctv_out_wa_1
<=
15
;
4'hc
:
dctv_out_wa_1
<=
2
;
4'hd
:
dctv_out_wa_1
<=
12
;
4'he
:
dctv_out_wa_1
<=
5
;
4'hf
:
dctv_out_wa_1
<=
11
;
endcase
// write first stage of output reordering
if
(
dctv_out_we_1
[
1
])
dctv_out_ram_1
[
dctv_out_wa_1
]
<=
dctv_out_sel
?
dctv_dout1
:
dctv_dout0
;
if
(
dctv_out_we_1
[
1
])
dctv_out_debug_ram_1
[
dctv_out_wa_1
]
<=
dctv_out_sel
?
dctv_yindex1
:
dctv_yindex0
;
if
(
rst
)
dctv_out_run_1
<=
0
;
else
if
(
dctv_out_start_1
)
dctv_out_run_1
<=
1
;
else
if
(
&
dctv_out_ra_1
[
5
:
0
])
dctv_out_run_1
<=
0
;
if
(
!
dctv_out_run_1
||
dctv_out_start_1
)
dctv_out_ra_1
<=
0
;
else
dctv_out_ra_1
<=
dctv_out_ra_1
+
1
;
// reading first stage of output reorder RAM
if
(
dctv_out_run_1
)
dctv_out_reg_1
<=
dctv_out_ram_1
[
dctv_out_ra_1_w
]
;
if
(
dctv_out_run_1
)
dctv_out_debug_reg_1
<=
dctv_out_debug_ram_1
[
dctv_out_ra_1_w
]
;
// last stage of the output reordering - 4 register memory
dctv_out_we_2
<=
dctv_out_run_1
;
dctv_out_wa_2
<=
dctv_out_ra_1_w
[
1
:
0
]
;
// write first stage of output reordering
if
(
dctv_out_we_2
)
dctv_out_ram_2
[
dctv_out_wa_2
]
<=
dctv_out_reg_1
;
if
(
dctv_out_we_2
)
dctv_out_debug_ram_2
[
dctv_out_wa_2
]
<=
dctv_out_debug_reg_1
;
if
(
rst
)
dctv_out_run_2
<=
0
;
else
if
(
dctv_out_start_2
)
dctv_out_run_2
<=
1
;
else
if
(
&
dctv_out_ra_2
[
5
:
0
])
dctv_out_run_2
<=
0
;
if
(
!
dctv_out_run_2
||
dctv_out_start_2
)
dctv_out_ra_2
<=
0
;
else
dctv_out_ra_2
<=
dctv_out_ra_2
+
1
;
// reading first stage of output reorder RAM
if
(
dctv_out_run_2
)
dctv_out_reg_2
<=
dctv_out_ram_2
[
dctv_out_ra_2
[
1
:
0
]]
;
if
(
dctv_out_run_2
)
dctv_out_debug_reg_2
<=
dctv_out_debug_ram_2
[
dctv_out_ra_2
[
1
:
0
]]
;
pre_first_out
<=
dctv_out_ra_1
[
6
:
0
]
==
2
;
dv
<=
dctv_out_run_2
;
end
always
@
(
posedge
clk
)
begin
//X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*
case
(
dcth_phin
[
3
:
0
])
4'h0
:
x_ra0
<=
2
;
4'h1
:
x_ra0
<=
7
;
4'h2
:
x_ra0
<=
3
;
4'h3
:
x_ra0
<=
4
;
4'h4
:
x_ra0
<=
5
;
4'h5
:
x_ra0
<=
6
;
4'h6
:
x_ra0
<=
0
;
4'h7
:
x_ra0
<=
1
;
4'h8
:
x_ra0
<=
'bx
;
4'h9
:
x_ra0
<=
3
;
4'ha
:
x_ra0
<=
5
;
4'hb
:
x_ra0
<=
4
;
4'hc
:
x_ra0
<=
'bx
;
4'hd
:
x_ra0
<=
6
;
4'he
:
x_ra0
<=
7
;
4'hf
:
x_ra0
<=
'bx
;
endcase
case
(
dcth_phin
[
3
:
0
])
4'h0
:
x_ra1
<=
1
;
4'h1
:
x_ra1
<=
'bx
;
4'h2
:
x_ra1
<=
3
;
4'h3
:
x_ra1
<=
5
;
4'h4
:
x_ra1
<=
4
;
4'h5
:
x_ra1
<=
'bx
;
4'h6
:
x_ra1
<=
6
;
4'h7
:
x_ra1
<=
7
;
4'h8
:
x_ra1
<=
'bx
;
4'h9
:
x_ra1
<=
2
;
4'ha
:
x_ra1
<=
7
;
4'hb
:
x_ra1
<=
3
;
4'hc
:
x_ra1
<=
4
;
4'hd
:
x_ra1
<=
5
;
4'he
:
x_ra1
<=
6
;
4'hf
:
x_ra1
<=
0
;
endcase
end
always
@
(
posedge
clk
)
begin
//X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*
case
(
dctv_phin
[
3
:
0
])
4'h0
:
t_ra0
<=
2
;
4'h1
:
t_ra0
<=
7
;
4'h2
:
t_ra0
<=
3
;
4'h3
:
t_ra0
<=
4
;
4'h4
:
t_ra0
<=
5
;
4'h5
:
t_ra0
<=
6
;
4'h6
:
t_ra0
<=
0
;
4'h7
:
t_ra0
<=
1
;
4'h8
:
t_ra0
<=
'bx
;
4'h9
:
t_ra0
<=
3
;
4'ha
:
t_ra0
<=
5
;
4'hb
:
t_ra0
<=
4
;
4'hc
:
t_ra0
<=
'bx
;
4'hd
:
t_ra0
<=
6
;
4'he
:
t_ra0
<=
7
;
4'hf
:
t_ra0
<=
'bx
;
endcase
case
(
dctv_phin
[
3
:
0
])
4'h0
:
t_ra1
<=
1
;
4'h1
:
t_ra1
<=
'bx
;
4'h2
:
t_ra1
<=
3
;
4'h3
:
t_ra1
<=
5
;
4'h4
:
t_ra1
<=
4
;
4'h5
:
t_ra1
<=
'bx
;
4'h6
:
t_ra1
<=
6
;
4'h7
:
t_ra1
<=
7
;
4'h8
:
t_ra1
<=
'bx
;
4'h9
:
t_ra1
<=
2
;
4'ha
:
t_ra1
<=
7
;
4'hb
:
t_ra1
<=
3
;
4'hc
:
t_ra1
<=
4
;
4'hd
:
t_ra1
<=
5
;
4'he
:
t_ra1
<=
6
;
4'hf
:
t_ra1
<=
0
;
endcase
end
dct_iv8_1d
#(
.
WIDTH
(
INPUT_WIDTH
)
,
.
OUT_WIDTH
(
TRANSPOSE_WIDTH
)
,
.
OUT_RSHIFT
(
OUT_RSHIFT1
)
,
.
B_WIDTH
(
DSP_B_WIDTH
)
,
.
A_WIDTH
(
DSP_A_WIDTH
)
,
.
P_WIDTH
(
DSP_P_WIDTH
)
,
.
COSINE_SHIFT
(
COSINE_SHIFT
)
,
.
COS_01_32
(
COS_01_32
)
,
.
COS_03_32
(
COS_03_32
)
,
.
COS_04_32
(
COS_04_32
)
,
.
COS_05_32
(
COS_05_32
)
,
.
COS_07_32
(
COS_07_32
)
,
.
COS_08_32
(
COS_08_32
)
,
.
COS_09_32
(
COS_09_32
)
,
.
COS_11_32
(
COS_11_32
)
,
.
COS_12_32
(
COS_12_32
)
,
.
COS_13_32
(
COS_13_32
)
,
.
COS_15_32
(
COS_15_32
)
)
dct_iv8_1d_pass1_0_i
(
.
clk
(
clk
)
,
// input
.
rst
(
rst
)
,
// input
.
en
(
dcth_en0
)
,
// input
.
d_in
(
dcth_xin0
)
,
// input[23:0]
.
start
(
dcth_start_0_r
)
,
// input
.
dout
(
dcth_dout0
)
,
// output[23:0]
.
pre2_start_out
()
,
// output reg
.
en_out
(
dcth_en_out0
)
,
// output reg
.
y_index
(
dcth_yindex0
)
// output[2:0] reg
)
;
dct_iv8_1d
#(
.
WIDTH
(
INPUT_WIDTH
)
,
.
OUT_WIDTH
(
TRANSPOSE_WIDTH
)
,
.
OUT_RSHIFT
(
OUT_RSHIFT1
)
,
.
B_WIDTH
(
DSP_B_WIDTH
)
,
.
A_WIDTH
(
DSP_A_WIDTH
)
,
.
P_WIDTH
(
DSP_P_WIDTH
)
,
.
COSINE_SHIFT
(
COSINE_SHIFT
)
,
.
COS_01_32
(
COS_01_32
)
,
.
COS_03_32
(
COS_03_32
)
,
.
COS_04_32
(
COS_04_32
)
,
.
COS_05_32
(
COS_05_32
)
,
.
COS_07_32
(
COS_07_32
)
,
.
COS_08_32
(
COS_08_32
)
,
.
COS_09_32
(
COS_09_32
)
,
.
COS_11_32
(
COS_11_32
)
,
.
COS_12_32
(
COS_12_32
)
,
.
COS_13_32
(
COS_13_32
)
,
.
COS_15_32
(
COS_15_32
)
)
dct_iv8_1d_pass1_1_i
(
.
clk
(
clk
)
,
// input
.
rst
(
rst
)
,
// input
.
en
(
dcth_en1
)
,
// input
.
d_in
(
dcth_xin1
)
,
// input[23:0]
.
start
(
dcth_start_1_r
)
,
// input
.
dout
(
dcth_dout1
)
,
// output[23:0]
.
pre2_start_out
()
,
// output reg
.
en_out
(
dcth_en_out1
)
,
// output reg
.
y_index
(
dcth_yindex1
)
// output[2:0] reg
)
;
//dcth_phin_run && (dcth_phin [6:0] ==9)
dct_iv8_1d
#(
.
WIDTH
(
TRANSPOSE_WIDTH
)
,
.
OUT_WIDTH
(
OUT_WIDTH
)
,
.
OUT_RSHIFT
(
OUT_RSHIFT2
)
,
.
B_WIDTH
(
DSP_B_WIDTH
)
,
.
A_WIDTH
(
DSP_A_WIDTH
)
,
.
P_WIDTH
(
DSP_P_WIDTH
)
,
.
COSINE_SHIFT
(
COSINE_SHIFT
)
,
.
COS_01_32
(
COS_01_32
)
,
.
COS_03_32
(
COS_03_32
)
,
.
COS_04_32
(
COS_04_32
)
,
.
COS_05_32
(
COS_05_32
)
,
.
COS_07_32
(
COS_07_32
)
,
.
COS_08_32
(
COS_08_32
)
,
.
COS_09_32
(
COS_09_32
)
,
.
COS_11_32
(
COS_11_32
)
,
.
COS_12_32
(
COS_12_32
)
,
.
COS_13_32
(
COS_13_32
)
,
.
COS_15_32
(
COS_15_32
)
)
dct_iv8_1d_pass2_0_i
(
.
clk
(
clk
)
,
// input
.
rst
(
rst
)
,
// input
.
en
(
dctv_en0
)
,
// input
.
d_in
(
dctv_xin0
)
,
// input[23:0]
.
start
(
dctv_start_0_r
)
,
// input
.
dout
(
dctv_dout0
)
,
// output[23:0]
.
pre2_start_out
()
,
// output reg
.
en_out
(
dctv_en_out0
)
,
// output reg
.
y_index
(
dctv_yindex0
)
// output[2:0] reg
)
;
dct_iv8_1d
#(
.
WIDTH
(
TRANSPOSE_WIDTH
)
,
.
OUT_WIDTH
(
OUT_WIDTH
)
,
.
OUT_RSHIFT
(
OUT_RSHIFT2
)
,
.
B_WIDTH
(
DSP_B_WIDTH
)
,
.
A_WIDTH
(
DSP_A_WIDTH
)
,
.
P_WIDTH
(
DSP_P_WIDTH
)
,
.
COSINE_SHIFT
(
COSINE_SHIFT
)
,
.
COS_01_32
(
COS_01_32
)
,
.
COS_03_32
(
COS_03_32
)
,
.
COS_04_32
(
COS_04_32
)
,
.
COS_05_32
(
COS_05_32
)
,
.
COS_07_32
(
COS_07_32
)
,
.
COS_08_32
(
COS_08_32
)
,
.
COS_09_32
(
COS_09_32
)
,
.
COS_11_32
(
COS_11_32
)
,
.
COS_12_32
(
COS_12_32
)
,
.
COS_13_32
(
COS_13_32
)
,
.
COS_15_32
(
COS_15_32
)
)
dct_iv8_1d_pass2_1_i
(
.
clk
(
clk
)
,
// input
.
rst
(
rst
)
,
// input
.
en
(
dctv_en1
)
,
// input
.
d_in
(
dctv_xin1
)
,
// input[23:0]
.
start
(
dctv_start_1_r
)
,
// input
.
dout
(
dctv_dout1
)
,
// output[23:0]
.
pre2_start_out
()
,
// output reg
.
en_out
(
dctv_en_out1
)
,
// output reg
.
y_index
(
dctv_yindex1
)
// output[2:0] reg
)
;
endmodule
dsp/dct_tests_01.tf
View file @
2478e215
...
@@ -40,7 +40,7 @@
...
@@ -40,7 +40,7 @@
`
timescale
1
ns
/
1
ps
`
timescale
1
ns
/
1
ps
// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
// will reduce needed resources
// will reduce needed resources
//
`define DCT_INPUT_UNITY
`
define
DCT_INPUT_UNITY
module
dct_tests_01
();
module
dct_tests_01
();
// parameter fstname="dct_tests_01.fst";
// parameter fstname="dct_tests_01.fst";
`
ifdef
IVERILOG
`
ifdef
IVERILOG
...
@@ -61,11 +61,16 @@ module dct_tests_01 ();
...
@@ -61,11 +61,16 @@ module dct_tests_01 ();
`
endif
// CVC
`
endif
// CVC
`
endif
// IVERILOG
`
endif
// IVERILOG
parameter
CLK_PERIOD
=
10
;
// ns
parameter
CLK_PERIOD
=
10
;
// ns
parameter
WIDTH
=
24
;
// input data width
parameter
WIDTH
=
24
;
// input data width
// parameter OUT_WIDTH = 16; // output data width
// parameter OUT_WIDTH = 16; // output data width
parameter
OUT_WIDTH
=
24
;
// output data width
parameter
OUT_WIDTH
=
24
;
// output data width
parameter
OUT_RSHIFT
=
3
;
// overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter
TRANSPOSE_WIDTH
=
24
;
// width of the transpose memory (intermediate results)
parameter
OUT_RSHIFT
=
2
;
// overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter
OUT_RSHIFT2
=
0
;
// overall right shift for the second (vertical) pass
parameter
DCT_GAP
=
16
;
// between runs
reg
RST
=
1
'b1;
reg
RST
=
1
'b1;
reg CLK = 1'
b0
;
reg CLK = 1'
b0
;
...
@@ -83,15 +88,17 @@ module dct_tests_01 ();
...
@@ -83,15 +88,17 @@ module dct_tests_01 ();
wire
x_we
=
!
phase_in
[
3
]
&&
run_in
;
wire
x_we
=
!
phase_in
[
3
]
&&
run_in
;
reg
[
WIDTH
-
1
:
0
]
x_in
;
reg
[
WIDTH
-
1
:
0
]
x_in
;
reg
[
WIDTH
-
1
:
0
]
x_in_2d
;
reg
[
WIDTH
-
1
:
0
]
x_out
;
reg
[
WIDTH
-
1
:
0
]
x_out
;
reg
[
WIDTH
-
1
:
0
]
x_ram
[
0
:
7
]
;
reg
[
WIDTH
-
1
:
0
]
x_ram
[
0
:
7
]
;
wire
[
WIDTH
-
1
:
0
]
x_out_w
=
x_ram
[
x_ra
]
;
wire
[
WIDTH
-
1
:
0
]
x_out_w
=
x_ram
[
x_ra
]
;
reg
start
=
0
;
reg
start
=
0
;
reg
start2
=
0
;
// second start for 2d
wire
[
OUT_WIDTH
-
1
:
0
]
y_dct
;
// S uppressThisWarning VEditor - simulation only
wire
[
OUT_WIDTH
-
1
:
0
]
y_dct
;
wire
pre2_start_out
;
// S uppressThisWarning VEditor - simulation only
wire
pre2_start_out
;
wire
en_out
;
// S uppressThisWarning VEditor - simulation only
wire
en_out
;
reg
y_pre_we
;
reg
y_pre_we
;
reg
y_we
;
reg
y_we
;
...
@@ -103,13 +110,27 @@ module dct_tests_01 ();
...
@@ -103,13 +110,27 @@ module dct_tests_01 ();
wire
signed
[
OUT_WIDTH
-
1
:
0
]
y_out
=
y_ram
[
y_ra
]
;
// SuppressThisWarning VEditor - simulation only
wire
signed
[
OUT_WIDTH
-
1
:
0
]
y_out
=
y_ram
[
y_ra
]
;
// SuppressThisWarning VEditor - simulation only
reg
signed
[
WIDTH
-
1
:
0
]
data_in
[
0
:
63
]
;
reg
signed
[
WIDTH
-
1
:
0
]
data_in
[
0
:
63
]
;
reg
signed
[
OUT_WIDTH
-
1
:
0
]
data_out
[
0
:
63
]
;
reg
signed
[
OUT_WIDTH
-
1
:
0
]
data_out
[
0
:
63
]
;
integer
i
,
j
;
wire
pre_last_in_2d
;
// SuppressThisWarning VEditor - simulation only
wire
pre_first_out_2d
;
// SuppressThisWarning VEditor - simulation only
wire
pre_busy_2d
;
// SuppressThisWarning VEditor - simulation only
wire
dv_2d
;
// SuppressThisWarning VEditor - simulation only
wire
signed
[
OUT_WIDTH
-
1
:
0
]
d_out_2d
;
wire
pre_last_in_2dr
;
// SuppressThisWarning VEditor - simulation only
wire
pre_first_out_2dr
;
// SuppressThisWarning VEditor - simulation only
wire
pre_busy_2dr
;
// SuppressThisWarning VEditor - simulation only
wire
dv_2dr
;
// SuppressThisWarning VEditor - simulation only
wire
signed
[
OUT_WIDTH
-
1
:
0
]
d_out_2dr
;
// SuppressThisWarning VEditor - simulation only
integer
i
,
j
,
i1
;
initial
begin
initial
begin
for
(
i
=
0
;
i
<
64
;
i
=
i
+
1
)
begin
for
(
i
=
0
;
i
<
64
;
i
=
i
+
1
)
begin
`
ifdef
DCT_INPUT_UNITY
`
ifdef
DCT_INPUT_UNITY
data_in
[
i
]
=
(
i
[
2
:
0
]
==
i
[
5
:
3
]
)
?
{
2
'b1,{WIDTH-2{1'
b0
}
}}
:
0
;
data_in
[
i
]
=
(
i
[
2
:
0
]
==
i
[
5
:
3
]
)
?
{
2
'b1,{WIDTH-2{1'
b0
}
}}
:
0
;
`
else
`
else
data_in
[
i
]
=
$random
;
data_in
[
i
]
=
$random
;
`
endif
`
endif
end
end
$display
(
"Input data in line-scan order:"
);
$display
(
"Input data in line-scan order:"
);
...
@@ -147,23 +168,6 @@ module dct_tests_01 ();
...
@@ -147,23 +168,6 @@ module dct_tests_01 ();
if
(&
i
[
2
:
0
]
)
repeat
(
8
)
@(
posedge
CLK
);
if
(&
i
[
2
:
0
]
)
repeat
(
8
)
@(
posedge
CLK
);
end
end
#1 x_in = 0;
#1 x_in = 0;
/*
// running 'one' - just make a period == 17
repeat (7) begin
@(posedge CLK);
#1 x_in = {2'b1,{WIDTH-2{1'b0}}}; // >>x_wa;
@(posedge CLK);
#1 x_in = 0;
repeat (15) @(posedge CLK); // 16+1= 17, non-zero will go through all of the 8 x[i]
end
begin
@(posedge CLK);
#1 x_in = {2'b1,{WIDTH-2{1'b0}}};
@(posedge CLK);
#1 x_in = 0;
en_x = 0;
end
*/
repeat
(
64
)
@(
posedge
CLK
);
repeat
(
64
)
@(
posedge
CLK
);
$display
(
""
);
$display
(
""
);
...
@@ -173,8 +177,44 @@ module dct_tests_01 ();
...
@@ -173,8 +177,44 @@ module dct_tests_01 ();
data_out
[
i
+
4
]
,
data_out
[
i
+
5
]
,
data_out
[
i
+
6
]
,
data_out
[
i
+
7
]
);
data_out
[
i
+
4
]
,
data_out
[
i
+
5
]
,
data_out
[
i
+
6
]
,
data_out
[
i
+
7
]
);
end
end
// repeat (64) @(posedge CLK);
// $finish;
end
initial
begin
wait
(!
RST
);
while
(!
start
)
begin
@(
posedge
CLK
);
#1;
end
for
(
i1
=
0
;
i1
<
64
;
i1
=
i1
+
1
)
begin
@(
posedge
CLK
);
#1;
x_in_2d
=
data_in
[
i1
]
;
if
(
i1
==
63
)
start2
=
1
;
end
for
(
i1
=
0
;
i1
<
64
;
i1
=
i1
+
1
)
begin
@(
posedge
CLK
);
#1;
start2
=
0
;
x_in_2d
=
data_in
[
i1
]
;
end
repeat
(
DCT_GAP
)
@(
posedge
CLK
);
#1;
start2
=
1
;
for
(
i1
=
0
;
i1
<
64
;
i1
=
i1
+
1
)
begin
@(
posedge
CLK
);
#1;
start2
=
0
;
x_in_2d
=
data_in
[
63
-
i1
]
;
end
repeat
(
300
)
@(
posedge
CLK
);
$finish
;
$finish
;
end
end
initial
j
=
0
;
initial
j
=
0
;
always
@
(
posedge
CLK
)
begin
always
@
(
posedge
CLK
)
begin
...
@@ -285,7 +325,53 @@ module dct_tests_01 ();
...
@@ -285,7 +325,53 @@ module dct_tests_01 ();
.start (start), // input
.start (start), // input
.dout (y_dct), // output[15:0]
.dout (y_dct), // output[15:0]
.pre2_start_out (pre2_start_out), // output reg
.pre2_start_out (pre2_start_out), // output reg
.en_out (en_out) // output reg
.en_out (en_out), // output reg
.y_index () // output[2:0] reg
);
);
dct_iv_8x8 #(
.INPUT_WIDTH (WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.OUT_RSHIFT1 (OUT_RSHIFT),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.DSP_B_WIDTH (18),
.DSP_A_WIDTH (25),
.DSP_P_WIDTH (48)
) dct_iv_8x8_i (
.clk (CLK), // input
.rst (RST), // input
.start (start || start2), // input
.xin (x_in_2d), // input[24:0] signed
.pre_last_in (pre_last_in_2d), // output reg
.pre_first_out (pre_first_out_2d), // output
.dv (dv_2d), // output
.d_out (d_out_2d), // output[24:0] signed
.pre_busy (pre_busy_2d) // output reg
);
dct_iv_8x8 #(
.INPUT_WIDTH (WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.OUT_RSHIFT1 (OUT_RSHIFT),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.DSP_B_WIDTH (18),
.DSP_A_WIDTH (25),
.DSP_P_WIDTH (48)
) dct_iv_8x8r_i (
.clk (CLK), // input
.rst (RST), // input
.start (pre_first_out_2d), // input
.xin (d_out_2d), // input[24:0] signed
.pre_last_in (pre_last_in_2dr), // output reg
.pre_first_out (pre_first_out_2dr), // output
.dv (dv_2dr), // output
.d_out (d_out_2dr), // output[24:0] signed
.pre_busy (pre_busy_2dr) // output reg
);
endmodule
endmodule
fpga_version.vh
View file @
2478e215
...
@@ -35,8 +35,11 @@
...
@@ -35,8 +35,11 @@
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*/
*/
parameter FPGA_VERSION = 32'h039300d7; //parallel - updated SATA (v12) all met, 80.32%
parameter FPGA_VERSION = 32'h039300da; //parallel - sata v.13 - tolerating elidle from device during comreset/cominit -0.014 /1, 81.38%,
// parameter FPGA_VERSION = 32'h039300d6; //parallel - more SATA debug link layer -0.127/18, 80.03% -> -0.002/4, 80.26%
// parameter FPGA_VERSION = 32'h039300d9; //parallel - correcting histograms -0.022/1, 79.60%
// parameter FPGA_VERSION = 32'h039300d8; //parallel - SATA is now logging irq on/off -0.054 /16, 80.50%
// parameter FPGA_VERSION = 32'h039300d7; //parallel - updated SATA (v12) all met, 80.32%
// parameter FPGA_VERSION = 32'h039300d6; //parallel - more SATA debug link layer -0.127/18, 80.03% -> -0.002/4, 80.26%
// parameter FPGA_VERSION = 32'h039300d5; //parallel - more SATA debug (v.0xd) -0.021/8 80.20 %
// parameter FPGA_VERSION = 32'h039300d5; //parallel - more SATA debug (v.0xd) -0.021/8 80.20 %
// parameter FPGA_VERSION = 32'h039300d4; //parallel - more SATA debug (v.0xd) -0.064 /24 80.77%
// parameter FPGA_VERSION = 32'h039300d4; //parallel - more SATA debug (v.0xd) -0.064 /24 80.77%
// parameter FPGA_VERSION = 32'h039300d3; //parallel - Updated SATA (v.0xb) -0.073/22
// parameter FPGA_VERSION = 32'h039300d3; //parallel - Updated SATA (v.0xb) -0.073/22
...
...
includes/ahci_defaults.vh
View file @
2478e215
...
@@ -2,6 +2,6 @@
...
@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h00000000000000000000000000000000000000000101001
1
001000000001FFFE)
, .INIT_0C (256'h00000000000000000000000000000000000000000101001
3
001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh
View file @
2478e215
...
@@ -97,7 +97,7 @@
...
@@ -97,7 +97,7 @@
// RO: HBA Revision ID
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h1
1
;
localparam PCI_Header__RID__RID__DFLT = 'h1
3
;
// RO: Base Class Code: 1 - Mass Storage Device
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
...
...
py393/x393_jpeg.py
View file @
2478e215
...
@@ -3045,6 +3045,151 @@ set_sensor_lens_flat_parameters 3 0 None None None None None 0x1d00 0x1d00 0x
...
@@ -3045,6 +3045,151 @@ set_sensor_lens_flat_parameters 3 0 None None None None None 0x1d00 0x1d00 0x
jpeg_sim_multi 4
jpeg_sim_multi 4
################## Simulate Parallel 18 - debugging histograms ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
#set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#use EOF instead of SOF for i2c sequencer advance
set_sensor_i2c_command all False None None None None None None True
#just testing
set_gpio_ports 1 1 # enable software gpio pins and porta (camsync)
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
##### write_control_register 0x480 0x400 # disable sensor chn 2
reset_camsync_inout 1 # reset all outputs
set_camsync_period 31 # set bit duration
set_camsync_period 0 # disable
set_camsync_delay 0 400
set_camsync_delay 1 300
set_camsync_delay 2 200
set_camsync_delay 3 150
#set_camsync_inout <is_out> <bit_number> <active_positive>
###set_camsync_inout 1 8 0
###set_camsync_inout 0 7 0
reset_camsync_inout 0 # start with internal trigger
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
set_camsync_mode 1 1 1 1 0 0xf
set_camsync_period 0 # so next setting period will immadiately trigger
set_camsync_period 8000 # 80 usec #and issue first trigger
##set_sensor_histogram_window 0 0 4 4 25 21
##set_sensor_histogram_window 1 0 4 4 41 21
##set_sensor_histogram_window 2 0 4 4 25 41
##set_sensor_histogram_window 3 0 4 4 41 41
set_sensor_histogram_window 0 0 4 4 41 21
set_sensor_histogram_window 1 0 4 4 41 41
set_sensor_histogram_window 2 0 4 4 41 41
set_sensor_histogram_window 3 0 4 4 41 41
r
read_control_register 0x430
read_control_register 0x431
write_cmd_frame_sequencer 0 1 2 0x600 0x48 # compressor q page = 1 // too late for frame 2
set_qtables 0 0 80
set_qtables 0 1 70
#irq coming, image not changing - yes
###write_cmd_frame_sequencer 0 1 1 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 #enable abort
#write_cmd_frame_sequencer 0 1 1 0x6c6 0x300006 #save 4 more lines that compressor has
###write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
###write_cmd_frame_sequencer 0 1 2 0x680 0x5405 # stop sensor memory (+0) // sensor memory should be controlled first, (9 commands
###write_cmd_frame_sequencer 0 1 2 0x6c0 0x5c49 # stop compressor memory (+0)
###write_cmd_frame_sequencer 0 1 3 0x686 0x240005 # correct lines
###write_cmd_frame_sequencer 0 1 3 0x680 0x5507 # run sensor memory (+1) Can not be 0
###write_cmd_frame_sequencer 0 1 4 0x686 0x280005 #save 4 more lines than sensor has
###write_cmd_frame_sequencer 0 1 4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)
###write_cmd_frame_sequencer 0 1 4 0x6c0 0x7d4b # run compressor memory (+2)
###write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (+0)
write_cmd_frame_sequencer 0 1 1 0x600 0x48 # compressor q page = 1
write_cmd_frame_sequencer 0 1 4 0x600 0x40 # compressor q page = 0
read_control_register 0x431
read_control_register 0x430
#testing histograms
write_control_register 0x409 0xc0
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
r
read_status 0x21
r
jpeg_sim_multi 4
###set_camsync_period 9000 # 90 usec # change period, skip first trigger
set_camsync_delay 0 400
set_camsync_delay 1 300
set_camsync_delay 2 200
set_camsync_delay 3 100
r
read_status 0x21
r
###jpeg_sim_multi 3
jpeg_sim_multi 4
r
read_status 0x21
r
set_camsync_delay 0 400
set_camsync_delay 1 350
set_camsync_delay 2 200
set_camsync_delay 3 50
##write_cmd_frame_sequencer 0 1 1 0x686 0x240005 # correct lines
##write_cmd_frame_sequencer 0 1 1 0x6c6 0x200006 # correct lines
##write_cmd_frame_sequencer 0 1 1 0x680 0x5507 # run sensor memory, update frame#, reset buffers
##write_cmd_frame_sequencer 0 1 1 0x6c0 0x7d4b # run compressor memory
##write_cmd_frame_sequencer 0 1 1 0x600 0x7 # run compressor
#switch to external (wired) trigger
jpeg_sim_multi 4
set_camsync_delay 0 400
set_camsync_delay 1 400
set_camsync_delay 2 200
set_camsync_delay 3 0
### set_camsync_inout 0 9 0 # external/internal trigger mode
###switch to external (wired) trigger
##set_camsync_inout 0 7 0
jpeg_sim_multi 4
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
jpeg_sim_multi 8
###set_camsync_period 8000 # 80 usec - restart while waiting for external trigger
jpeg_sim_multi 4
jpeg_sim_multi 4
################## Serial ####################
################## Serial ####################
...
...
sensor/sens_histogram_snglclk.v
View file @
2478e215
...
@@ -356,6 +356,7 @@ module sens_histogram_snglclk #(
...
@@ -356,6 +356,7 @@ module sens_histogram_snglclk #(
// prevent starting rq if grant is still on (back-to-back)
// prevent starting rq if grant is still on (back-to-back)
if
(
!
hist_out
)
en_rq_start
<=
0
;
if
(
!
hist_out
)
en_rq_start
<=
0
;
else
if
(
!
hist_grant
)
en_rq_start
<=
1
;
else
if
(
!
hist_grant
)
en_rq_start
<=
1
;
hist_rq_r
<=
!
hist_rst
&
en_mclk
&&
hist_out
&&
!
(
&
hist_raddr
)
&&
en_rq_start
;
hist_rq_r
<=
!
hist_rst
&
en_mclk
&&
hist_out
&&
!
(
&
hist_raddr
)
&&
en_rq_start
;
if
(
!
hist_out
||
(
&
hist_raddr
[
7
:
0
]))
hist_re
[
0
]
<=
0
;
if
(
!
hist_out
||
(
&
hist_raddr
[
7
:
0
]))
hist_re
[
0
]
<=
0
;
...
...
x393_parallel.bit
View file @
2478e215
No preview for this file type
x393_sata/ahci/ahci_top.v
View file @
2478e215
...
@@ -1217,6 +1217,7 @@ wire [9:0] xmit_dbg_01;
...
@@ -1217,6 +1217,7 @@ wire [9:0] xmit_dbg_01;
.
d2h_ready
(
d2h_ready
)
,
// input
.
d2h_ready
(
d2h_ready
)
,
// input
.
debug_link_send_data
(
debug_link_send_data
)
,
// input
.
debug_link_send_data
(
debug_link_send_data
)
,
// input
.
debug_link_dmatp
(
debug_link_dmatp
)
,
// link received DMATp from device
.
debug_link_dmatp
(
debug_link_dmatp
)
,
// link received DMATp from device
.
irq
(
irq
)
,
// system IRQ
.
datascope_clk
(
datascope_clk
)
,
// output
.
datascope_clk
(
datascope_clk
)
,
// output
.
datascope_waddr
(
datascope_waddr
)
,
// output[9:0] reg
.
datascope_waddr
(
datascope_waddr
)
,
// output[9:0] reg
.
datascope_we
(
datascope_we
)
,
// output
.
datascope_we
(
datascope_we
)
,
// output
...
@@ -1350,6 +1351,7 @@ module datascope_timing #(
...
@@ -1350,6 +1351,7 @@ module datascope_timing #(
input
debug_link_send_data
,
// @posedge mclk (sata_clk, 75MHz) - last symbol was data output (to count sent out)
input
debug_link_send_data
,
// @posedge mclk (sata_clk, 75MHz) - last symbol was data output (to count sent out)
input
debug_link_dmatp
,
// link received DMATp from device
input
debug_link_dmatp
,
// link received DMATp from device
input
irq
,
// system irq
output
datascope_clk
,
output
datascope_clk
,
output
reg
[
ADDRESS_BITS
-
1
:
0
]
datascope_waddr
,
output
reg
[
ADDRESS_BITS
-
1
:
0
]
datascope_waddr
,
output
datascope_we
,
output
datascope_we
,
...
@@ -1408,6 +1410,10 @@ module datascope_timing #(
...
@@ -1408,6 +1410,10 @@ module datascope_timing #(
reg
reset_link_count
;
// data FIS from dma command until
reg
reset_link_count
;
// data FIS from dma command until
reg
was_link_dmatp
;
//
reg
was_link_dmatp
;
//
reg
irq_r
;
reg
irq_was
;
wire
we_w
=
write_punch_time
||
fis_start
||
(
fis_we
?
pre_we_r
:
(
!
fis_run
&&
(
fis_run_d
||
fis_run_d2
||
fis_run_d3
||
fis_run_d4
||
fis_run_d5
)))
;
// 3 after
wire
we_irq
=
(
irq_was
^
irq_r
)
&&
!
we_w
;
// only when not irq
// input debug_link_dmatp, // link received DMATp from device
// input debug_link_dmatp, // link received DMATp from device
...
@@ -1436,11 +1442,11 @@ module datascope_timing #(
...
@@ -1436,11 +1442,11 @@ module datascope_timing #(
else
if
(
!
fis_run_d2
&&
fis_run_d3
)
datascope_di
<=
{
8'h55
,
last_dma_cmd
};
else
if
(
!
fis_run_d2
&&
fis_run_d3
)
datascope_di
<=
{
8'h55
,
last_dma_cmd
};
else
if
(
!
fis_run_d3
&&
fis_run_d4
)
datascope_di
<=
non_dma_act
;
else
if
(
!
fis_run_d3
&&
fis_run_d4
)
datascope_di
<=
non_dma_act
;
else
if
(
!
fis_run_d4
&&
fis_run_d5
)
datascope_di
<=
{
h2d_nready_cntr
[
7
:
0
]
,
was_link_dmatp
,
1'b0
,
link_count_latched
};
else
if
(
!
fis_run_d4
&&
fis_run_d5
)
datascope_di
<=
{
h2d_nready_cntr
[
7
:
0
]
,
was_link_dmatp
,
1'b0
,
link_count_latched
};
else
if
(
we_irq
)
datascope_di
<=
{
3'h7
,
irq_r
,
cur_time
};
pre_we_r
<=
pre_we_w
||
fis_start
;
pre_we_r
<=
pre_we_w
||
fis_start
;
// we_r <= write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && fis_run_d));
// we_r <= write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && fis_run_d));
we_r
<=
w
rite_punch_time
||
fis_start
||
(
fis_we
?
pre_we_r
:
(
!
fis_run
&&
(
fis_run_d
||
fis_run_d2
||
fis_run_d3
||
fis_run_d4
||
fis_run_d5
)))
;
// 3 after
we_r
<=
w
e_w
||
we_irq
;
if
(
fis_start
)
fis_left
<=
FIS_LEN
-
1
;
if
(
fis_start
)
fis_left
<=
FIS_LEN
-
1
;
else
if
(
pre_we_w
)
fis_left
<=
fis_left
-
1
;
else
if
(
pre_we_w
)
fis_left
<=
fis_left
-
1
;
...
@@ -1509,6 +1515,11 @@ module datascope_timing #(
...
@@ -1509,6 +1515,11 @@ module datascope_timing #(
if
(
rst
)
datascope_waddr
<=
0
;
if
(
rst
)
datascope_waddr
<=
0
;
else
if
(
we_r
)
datascope_waddr
<=
datascope_waddr
+
1
;
else
if
(
we_r
)
datascope_waddr
<=
datascope_waddr
+
1
;
irq_r
<=
irq
;
if
(
rst
)
irq_was
<=
0
;
else
if
(
we_irq
)
irq_was
<=
irq_r
;
end
end
endmodule
endmodule
...
...
x393_sata/device/oob_dev.v
View file @
2478e215
...
@@ -44,7 +44,10 @@
...
@@ -44,7 +44,10 @@
// All references to doc = to SerialATA_Revision_2_6_Gold.pdf
// All references to doc = to SerialATA_Revision_2_6_Gold.pdf
module
oob_dev
#(
module
oob_dev
#(
parameter
DATA_BYTE_WIDTH
=
4
,
parameter
DATA_BYTE_WIDTH
=
4
,
parameter
CLK_SPEED_GRADE
=
2
// 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
parameter
CLK_SPEED_GRADE
=
2
,
// 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
parameter
TEST_ELIDLE
=
2
,
// test transmitting eidle between data rates (number of times)
parameter
ELIDLE_DELAY
=
'h28
,
// 80, // counter cycles
parameter
ELIDLE_DURATION
=
'h80
// counter cycles
)
)
(
(
// sata clk = usrclk2
// sata clk = usrclk2
...
@@ -83,15 +86,21 @@ localparam STATE_CALIBRATE = 4;
...
@@ -83,15 +86,21 @@ localparam STATE_CALIBRATE = 4;
localparam
STATE_COMWAKE
=
5
;
localparam
STATE_COMWAKE
=
5
;
localparam
STATE_RECAL
=
55
;
localparam
STATE_RECAL
=
55
;
localparam
STATE_SENDALIGN
=
6
;
localparam
STATE_SENDALIGN
=
6
;
localparam
STATE_EIDLE_RATE
=
65
;
localparam
STATE_READY
=
7
;
localparam
STATE_READY
=
7
;
localparam
STATE_PARTIAL
=
8
;
localparam
STATE_PARTIAL
=
8
;
localparam
STATE_SLUMBER
=
9
;
localparam
STATE_SLUMBER
=
9
;
localparam
STATE_REDUCESPEED
=
10
;
localparam
STATE_REDUCESPEED
=
10
;
localparam
STATE_ERROR
=
11
;
localparam
STATE_ERROR
=
11
;
reg
[
31
:
0
]
rate_change_cntr
;
reg
was_txelecidle
;
reg
[
9
:
0
]
state
;
reg
[
9
:
0
]
state
;
wire
retry_interval_elapsed
;
wire
retry_interval_elapsed
;
wire
wait_interval_elapsed
;
wire
wait_interval_elapsed
;
wire
elidle_rate_delay_elapsed
;
wire
elidle_rate_duration_elapsed
;
wire
nocomwake
;
wire
nocomwake
;
wire
[
31
:
0
]
align
;
wire
[
31
:
0
]
align
;
wire
[
31
:
0
]
sync
;
wire
[
31
:
0
]
sync
;
...
@@ -110,9 +119,21 @@ always @ (posedge clk)
...
@@ -110,9 +119,21 @@ always @ (posedge clk)
retry_timer
<=
rst
|
~
(
state
==
STATE_AWAITCOMWAKE
)
?
32'h0
:
retry_timer
+
1'b1
;
retry_timer
<=
rst
|
~
(
state
==
STATE_AWAITCOMWAKE
)
?
32'h0
:
retry_timer
+
1'b1
;
reg
[
31
:
0
]
wait_timer
;
reg
[
31
:
0
]
wait_timer
;
assign
wait_interval_elapsed
=
wait_timer
==
32'd4096
;
assign
wait_interval_elapsed
=
wait_timer
==
32'd4096
;
assign
elidle_rate_delay_elapsed
=
wait_timer
==
ELIDLE_DELAY
;
always
@
(
posedge
clk
)
always
@
(
posedge
clk
)
wait_timer
<=
rst
|
~
(
state
==
STATE_SENDALIGN
)
?
32'h0
:
wait_timer
+
1'b1
;
wait_timer
<=
rst
|
~
(
state
==
STATE_SENDALIGN
)
?
32'h0
:
wait_timer
+
1'b1
;
reg
[
31
:
0
]
elidle_timer
;
assign
elidle_rate_duration_elapsed
=
elidle_timer
==
ELIDLE_DURATION
;
always
@
(
posedge
clk
)
elidle_timer
<=
rst
|
~
(
state
==
STATE_EIDLE_RATE
)
?
32'h0
:
elidle_timer
+
1'b1
;
always
@
(
posedge
clk
)
begin
was_txelecidle
<=
txelecidle
;
if
(
rst
)
rate_change_cntr
<=
0
;
else
if
(
txelecidle
&&
!
was_txelecidle
)
rate_change_cntr
<=
rate_change_cntr
+
1
;
end
reg
[
31
:
0
]
data
;
reg
[
31
:
0
]
data
;
reg
[
3
:
0
]
isk
;
reg
[
3
:
0
]
isk
;
...
@@ -218,6 +239,7 @@ always @ (posedge clk)
...
@@ -218,6 +239,7 @@ always @ (posedge clk)
end
end
STATE_SENDALIGN:
STATE_SENDALIGN:
begin
begin
txelecidle
<=
1'b0
;
data
<=
align
;
data
<=
align
;
isk
<=
4'h1
;
isk
<=
4'h1
;
if
(
aligndet
)
if
(
aligndet
)
...
@@ -225,9 +247,21 @@ always @ (posedge clk)
...
@@ -225,9 +247,21 @@ always @ (posedge clk)
else
else
if
(
wait_interval_elapsed
)
if
(
wait_interval_elapsed
)
state
<=
STATE_ERROR
;
state
<=
STATE_ERROR
;
else
else
if
((
rate_change_cntr
<
TEST_ELIDLE
)
&&
elidle_rate_delay_elapsed
)
state
<=
STATE_EIDLE_RATE
;
else
state
<=
STATE_SENDALIGN
;
state
<=
STATE_SENDALIGN
;
end
end
STATE_EIDLE_RATE:
begin
txelecidle
<=
1'b1
;
data
<=
0
;
// align; // 'bz;
isk
<=
4'h1
;
if
(
elidle_rate_duration_elapsed
)
state
<=
STATE_SENDALIGN
;
end
STATE_READY:
STATE_READY:
begin
begin
txelecidle
<=
1'b0
;
txelecidle
<=
1'b0
;
...
...
x393_sata/host/oob.v
View file @
2478e215
...
@@ -223,7 +223,11 @@ always @ (posedge clk) begin
...
@@ -223,7 +223,11 @@ always @ (posedge clk) begin
else
rxdlysreset_r
<=
rxdlysreset_r
<<
1
;
else
rxdlysreset_r
<=
rxdlysreset_r
<<
1
;
end
end
reg
was_rxelecidle_waiting_reset
;
always
@
(
posedge
clk
)
begin
if
(
rst
||
set_wait_eidle
)
was_rxelecidle_waiting_reset
<=
0
;
else
if
(
state_wait_rxrst
&&
rxelecidle
)
was_rxelecidle_waiting_reset
<=
1
;
end
assign
state_idle
=
~
state_wait_cominit
&
assign
state_idle
=
~
state_wait_cominit
&
~
state_wait_comwake
&
~
state_wait_comwake
&
~
state_wait_align
&
~
state_wait_align
&
...
@@ -253,11 +257,17 @@ end
...
@@ -253,11 +257,17 @@ end
assign
set_wait_cominit
=
state_idle
&
oob_start
&
~
cominit_req
;
assign
set_wait_cominit
=
state_idle
&
oob_start
&
~
cominit_req
;
assign
set_wait_comwake
=
state_idle
&
cominit_req_l
&
cominit_allow
&
rxcominit_done
|
state_wait_cominit
&
rxcominitdet_l
&
rxcominit_done
;
assign
set_wait_comwake
=
state_idle
&
cominit_req_l
&
cominit_allow
&
rxcominit_done
|
state_wait_cominit
&
rxcominitdet_l
&
rxcominit_done
;
assign
set_recal_tx
=
state_wait_comwake
&
rxcomwakedet_l
&
rxcomwake_done
;
assign
set_recal_tx
=
state_wait_comwake
&
rxcomwakedet_l
&
rxcomwake_done
;
assign
set_wait_eidle
=
state_recal_tx
&
recal_tx_done
;
///assign set_wait_eidle = state_recal_tx & recal_tx_done;
assign
set_wait_eidle
=
(
state_recal_tx
&
recal_tx_done
)
|
(
rxelecidle
&
(
state_wait_align
|
state_wait_clk_align
|
state_wait_align2
|
(
state_wait_rxrst
&
rxreset_ack
&
was_rxelecidle_waiting_reset
)
))
;
assign
set_wait_rxrst
=
state_wait_eidle
&
eidle_timer_done
;
assign
set_wait_rxrst
=
state_wait_eidle
&
eidle_timer_done
;
assign
set_wait_align
=
state_wait_rxrst
&
rxreset_ack
;
///assign set_wait_align = state_wait_rxrst & rxreset_ack;
assign
set_wait_clk_align
=
state_wait_align
&
(
detected_alignp_r
)
;
///assign set_wait_clk_align = state_wait_align & (detected_alignp_r);
assign
set_wait_align2
=
state_wait_clk_align
&
clk_phase_align_ack
;
///assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack;
assign
set_wait_align
=
state_wait_rxrst
&
rxreset_ack
&
~
rxelecidle
;
assign
set_wait_clk_align
=
state_wait_align
&
(
detected_alignp_r
)
&
~
rxelecidle
;
assign
set_wait_align2
=
state_wait_clk_align
&
clk_phase_align_ack
&
~
rxelecidle
;
...
@@ -278,10 +288,18 @@ assign clr_wait_cominit = set_wait_comwake | set_error;
...
@@ -278,10 +288,18 @@ assign clr_wait_cominit = set_wait_comwake | set_error;
assign
clr_wait_comwake
=
set_recal_tx
|
set_error
;
assign
clr_wait_comwake
=
set_recal_tx
|
set_error
;
assign
clr_recal_tx
=
set_wait_eidle
|
set_error
;
assign
clr_recal_tx
=
set_wait_eidle
|
set_error
;
assign
clr_wait_eidle
=
set_wait_rxrst
|
set_error
;
assign
clr_wait_eidle
=
set_wait_rxrst
|
set_error
;
assign
clr_wait_rxrst
=
set_wait_align
|
set_error
;
///assign clr_wait_rxrst = set_wait_align | set_error;
assign
clr_wait_align
=
set_wait_clk_align
|
set_error
;
assign
clr_wait_rxrst
=
state_wait_rxrst
&
rxreset_ack
;
assign
clr_wait_clk_align
=
set_wait_align2
|
set_error
;
assign
clr_wait_align2
=
set_wait_synp
|
set_error
;
///assign clr_wait_align = set_wait_clk_align | set_error;
///assign clr_wait_clk_align = set_wait_align2 | set_error;
///assign clr_wait_align2 = set_wait_synp | set_error;
assign
clr_wait_align
=
set_wait_clk_align
|
set_error
|
rxelecidle
;
assign
clr_wait_clk_align
=
set_wait_align2
|
set_error
|
rxelecidle
;
assign
clr_wait_align2
=
set_wait_synp
|
set_error
|
rxelecidle
;
assign
clr_wait_synp
=
set_wait_linkup
|
set_error
;
assign
clr_wait_synp
=
set_wait_linkup
|
set_error
;
assign
clr_wait_linkup
=
state_wait_linkup
;
//TODO not so important, but still have to trace 3 back-to-back non alignp primitives
assign
clr_wait_linkup
=
state_wait_linkup
;
//TODO not so important, but still have to trace 3 back-to-back non alignp primitives
assign
clr_error
=
state_error
;
assign
clr_error
=
state_error
;
...
...
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