Commit 23b51938 authored by Raimundas Bastys's avatar Raimundas Bastys

changed to zynq ODDR and minor fixes in to file sensor/sensor_spi_io.v

parent 0c3fc4d2
......@@ -37,7 +37,7 @@
* with at least one of the Free Software programs.
*/
//v0.0 working on s6lx4-3 10-40MHz clock with PCB CS01, not passing to datasheet CMV300 - extra clock to end spi enable period
//to do v0.1 change ODDR2(s6) to ODDR(zynq)
//v0.1 change ODDR2(s6) to ODDR(zynq)
`timescale 1ns/1ps
......@@ -50,6 +50,7 @@ input rd_en, //read from sensor enable, one clock period input signal
input wr_en, //write to sensor enable, one clock period input signal
input [7:0] wr_data, //data to spi address be write
output reg [7:0] reg_data, //data from spi address will read
output reg spi_ready, //spi available for command
input pin_spi_out, //SPI interface pin: data out, direction from sensor to FPGA
output reg pin_spi_in, //SPI interface pin: data in, direction from FPGA to sensor
output reg pin_spi_en, //SPI interface pin: data enable, direction from FPGA to sensor
......@@ -59,7 +60,8 @@ output pin_spi_clk //SPI interface pin: data clock, direction from FPGA to sens
reg [7:0] sfst;
reg [3:0] sfst_ciklu;
reg [15:0] spi_word;
reg [15:0] spi_word_rd;
reg [15:0] spi_word_wr;
reg read_bit;
reg [3:0] sfst_bits;
reg [7:0] sfst_byte;
......@@ -87,6 +89,7 @@ if ( reset ) begin
sfst_bits[3:0] <= 4'b0000;
sfst_byte[7:0] <= 8'h00;
reg_data[7:0] <= 8'h00;
spi_ready <= 1'b1;
end else begin
......@@ -96,24 +99,29 @@ end else begin
pin_spi_in <= 1'b0;
sfst_ciklu[3:0] <= 4'hf;
read_bit <= 1'b0;
if (rd_en)
spi_word_rd[15:0] <= {1'b0, addr[6:0], 8'h00};
spi_word_wr[15:0] <= {1'b1, addr[6:0], wr_data[7:0]};
if (rd_en) begin
spi_ready <= 1'b0;
sfst <= `S_FST_RD0;
if (wr_en)
end
if (wr_en) begin
spi_ready <= 1'b0;
sfst <= `S_FST_WR0;
end
end
`S_FST_RD0 : begin
pin_spi_en <= 1'b0;
pin_spi_in <= 1'b0;
sfst_ciklu[3:0] <= 4'hf;
read_bit <= 1'b0;
spi_word[15:0] <= {1'b0, addr[6:0], 8'h00};
sfst <= `S_FST_RD1;
end
`S_FST_RD1 : begin
pin_spi_en <= 1'b1;
read_bit <= 1'b0;
pin_spi_in <= spi_word[15];
spi_word[15:1] <= spi_word[14:0];
pin_spi_in <= spi_word_rd[15];
spi_word_rd[15:1] <= spi_word_rd[14:0];
if ( sfst_ciklu[3:0] == 4'b0000) begin
read_bit <= 1'b0;
sfst <= `S_FST_END;
......@@ -131,13 +139,12 @@ end else begin
pin_spi_en <= 1'b0;
pin_spi_in <= 1'b0;
sfst_ciklu[3:0] <= 4'hf;
spi_word[15:0] <= {1'b1, addr[6:0], wr_data[7:0]};
sfst <= `S_FST_WR1;
end
`S_FST_WR1 : begin
pin_spi_en <= 1'b1;
pin_spi_in <= spi_word[15];
spi_word[15:1] <= spi_word[14:0];
pin_spi_in <= spi_word_wr[15];
spi_word_wr[15:1] <= spi_word_wr[14:0];
if ( sfst_ciklu[3:0] == 4'b0000) begin
sfst <= `S_FST_END;
end else begin
......@@ -149,6 +156,7 @@ end else begin
pin_spi_in <= 1'b0;
sfst_ciklu[3:0] <= 4'hf;
read_bit <= 1'b0;
spi_ready <= 1'b1;
sfst <= `S_FST_000;
end
endcase
......@@ -169,17 +177,21 @@ end //if
end //always
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
ODDR #(
// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_sens (
.Q(pin_spi_clk), // 1-bit DDR output data
.C0(clk0), // 1-bit clock input
.C1(!clk0), // 1-bit clock input
.C(clk0), // 1-bit clock input
// .C0(clk0), // 1-bit clock input
// .C1(!clk0), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b0), // 1-bit data input (associated with C0)
.D1(1'b1), // 1-bit data input (associated with C1)
// .D0(1'b0), // 1-bit data input (associated with C0)
// .D1(1'b1), // 1-bit data input (associated with C1)
.D1(1'b0), // 1-bit data input
.D2(1'b1), // 1-bit data input
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
......
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