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Commit 2008d6d4 authored by Andrey Filippov's avatar Andrey Filippov
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working on i2c driver

parent 5c0b4692
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Showing with 86 additions and 32 deletions
.settings/org.eclipse.core.resources.prefs
View file @ 2008d6d4
...@@ -3,3 +3,5 @@ encoding//helpers/convert_data_to_params.py=utf-8 ...@@ -3,3 +3,5 @@ encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8 encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8 encoding//helpers/convert_zigzag_rom.py=utf-8
encoding//py393/test_mcntrl.py=utf-8 encoding//py393/test_mcntrl.py=utf-8
encoding//py393/x393_i2c.py.test=utf-8
encoding//py393/x393_init_usb_hub.py=utf-8
py393/init_jtag.sh
View file @ 2008d6d4
#!/bin/sh #!/bin/sh
#mkdir -p /lib/modules #mkdir -p /lib/modules
#ln -sf /usr/local/lib /lib/modules/4.0.0-xilinx #ln -sf /usr/local/lib /lib/modules/4.0.0-xilinx
insmod /usr/local/lib/fpgajtag.ko #insmod /usr/local/lib/fpgajtag.ko
#mknod -m 0666 /dev/fjtag c 132 2 #mknod -m 0666 /dev/fjtag c 132 2
mknod -m 0666 /dev/fpgaresetjtag c 132 0 mknod -m 0666 /dev/fpgaresetjtag c 132 0
mknod -m 0666 /dev/jtagraw c 132 0 mknod -m 0666 /dev/jtagraw c 132 0
......
py393/x393_export_c.py
View file @ 2008d6d4
...@@ -1684,7 +1684,7 @@ class X393ExportC(object): ...@@ -1684,7 +1684,7 @@ class X393ExportC(object):
dw=[] dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO")) dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
dw.append(("i2c_fifo_nempty", 8, 1,0, "I2C read FIFO has data")) dw.append(("i2c_fifo_nempty", 8, 1,0, "I2C read FIFO has data"))
dw.append(("i2c_fifo_cntrl", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)")) dw.append(("i2c_fifo_lsb", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)"))
dw.append(("busy", 10, 1,0, "I2C sequencer busy")) dw.append(("busy", 10, 1,0, "I2C sequencer busy"))
dw.append(("alive_fs", 11, 1,0, "Sensor generated frame sync since last status update")) dw.append(("alive_fs", 11, 1,0, "Sensor generated frame sync since last status update"))
dw.append(("frame_num", 12, 4,0, "I2C sequencer frame number")) dw.append(("frame_num", 12, 4,0, "I2C sequencer frame number"))
...@@ -1720,7 +1720,7 @@ class X393ExportC(object): ...@@ -1720,7 +1720,7 @@ class X393ExportC(object):
def _enc_i2c_tbl_addr(self): def _enc_i2c_tbl_addr(self):
dw=[] dw=[]
dw.append(("tbl_addr", 0, 8,0, "Address/length in 64-bit words (<<3 to get byte address)")) dw.append(("tbl_addr", 0, 8,0, "I2C table index"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2,3, "Should be 3 to select table address write mode")) dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2,3, "Should be 3 to select table address write mode"))
return dw return dw
...@@ -1738,7 +1738,7 @@ class X393ExportC(object): ...@@ -1738,7 +1738,7 @@ class X393ExportC(object):
dw=[] dw=[]
dw.append(("rah", vrlg.SENSI2C_TBL_RAH, vrlg.SENSI2C_TBL_RAH_BITS, 0, "High byte of the i2c register address")) dw.append(("rah", vrlg.SENSI2C_TBL_RAH, vrlg.SENSI2C_TBL_RAH_BITS, 0, "High byte of the i2c register address"))
dw.append(("rnw", vrlg.SENSI2C_TBL_RNWREG, 1, 0, "Read/not write i2c register, should be 1 here")) dw.append(("rnw", vrlg.SENSI2C_TBL_RNWREG, 1, 0, "Read/not write i2c register, should be 1 here"))
dw.append(("nbrd", vrlg.SENSI2C_TBL_NBRD, vrlg.SENSI2C_TBL_NBRD_BITS,0, "Number of bytes to read (1..18, 0 means '8')")) dw.append(("nbrd", vrlg.SENSI2C_TBL_NBRD, vrlg.SENSI2C_TBL_NBRD_BITS,0, "Number of bytes to read (1..8, 0 means '8')"))
dw.append(("nabrd", vrlg.SENSI2C_TBL_NABRD, 1, 0, "Number of address bytes for read (0 - one byte, 1 - two bytes)")) dw.append(("nabrd", vrlg.SENSI2C_TBL_NABRD, 1, 0, "Number of address bytes for read (0 - one byte, 1 - two bytes)"))
dw.append(("dly", vrlg.SENSI2C_TBL_DLY, vrlg.SENSI2C_TBL_DLY_BITS, 0, "Bit delay - number of mclk periods in 1/4 of the SCL period")) dw.append(("dly", vrlg.SENSI2C_TBL_DLY, vrlg.SENSI2C_TBL_DLY_BITS, 0, "Bit delay - number of mclk periods in 1/4 of the SCL period"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2, 2, "Should be 2 to select table data write mode")) dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2, 2, "Should be 2 to select table data write mode"))
......
py393/x393_jpeg.py
View file @ 2008d6d4
...@@ -972,6 +972,7 @@ measure_all "*DI" ...@@ -972,6 +972,7 @@ measure_all "*DI"
program_status_sensor_io all 1 0 program_status_sensor_io all 1 0
print_status_sensor_io all print_status_sensor_io all
setup_all_sensors True None 0x4
################## Parallel ################## ################## Parallel ##################
cd /usr/local/verilog/; test_mcntrl.py @hargs cd /usr/local/verilog/; test_mcntrl.py @hargs
...@@ -981,7 +982,8 @@ setup_all_sensors True None 0xf ...@@ -981,7 +982,8 @@ setup_all_sensors True None 0xf
#set quadrants #set quadrants
set_sensor_io_ctl 0 None None None None None 0 0xe set_sensor_io_ctl 0 None None None None None 0 0xe
set_sensor_io_ctl 1 None None None None None 0 0xe set_sensor_io_ctl 1 None None None None None 0 0xe
set_sensor_io_ctl 2 None None None None None 0 0x4 #set_sensor_io_ctl 2 None None None None None 0 0x4
set_sensor_io_ctl 2 None None None None None 0 0xe
set_sensor_io_ctl 3 None None None None None 0 0xe set_sensor_io_ctl 3 None None None None None 0 0xe
# Set Bayer = 3 (probably #1 and #3 need different hact/pxd delays to use the same compressor bayer for all channels) # Set Bayer = 3 (probably #1 and #3 need different hact/pxd delays to use the same compressor bayer for all channels)
compressor_control all None None None None None 3 compressor_control all None None None None None 3
...@@ -1018,8 +1020,8 @@ write_sensor_i2c all 1 0 0x90090797 ...@@ -1018,8 +1020,8 @@ write_sensor_i2c all 1 0 0x90090797
#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors) #run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
compressor_control all 2 compressor_control all 2
jpeg_write "img.jpeg" 0 #jpeg_write "img.jpeg" 0
#jpeg_write "img.jpeg" All jpeg_write "img.jpeg" All
#changing quality (example 85%): #changing quality (example 85%):
set_qtables all 0 85 set_qtables all 0 85
......
py393/x393_mcntrl_adjust.py
View file @ 2008d6d4
...@@ -1530,7 +1530,9 @@ class X393McntrlAdjust(object): ...@@ -1530,7 +1530,9 @@ class X393McntrlAdjust(object):
self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dly),quiet=quiet) self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dly),quiet=quiet)
wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1)) wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1))
if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?) if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?)
raise Exception("Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized") # raise Exception("Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized")
#disabling check 04.09.2016
print ("raise Exception Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized. Phase: %d, cmda_odly_lin=%d"%(phase,cmda_odly_lin))
dqso_cache[dly] = wlev_rslt dqso_cache[dly] = wlev_rslt
if quiet < 1: if quiet < 1:
print ('measure_dqso(%d) - new measurement'%(dly)) print ('measure_dqso(%d) - new measurement'%(dly))
...@@ -3242,13 +3244,13 @@ class X393McntrlAdjust(object): ...@@ -3242,13 +3244,13 @@ class X393McntrlAdjust(object):
dqsi_safe_phase=dqsi_safe_phase, dqsi_safe_phase=dqsi_safe_phase,
ra = ra, # 0, ra = ra, # 0,
ba = ba, # 0, ba = ba, # 0,
quiet=quiet+1, #1, quiet=quiet, #+1, #1,
single=True) # single=False) single=True) # single=False)
pass2=self.measure_addr_odelay(safe_phase=safe_phase, #0.25, # 0 strictly follow cmda_odelay, >0 -program with this fraction of clk period from the margin pass2=self.measure_addr_odelay(safe_phase=safe_phase, #0.25, # 0 strictly follow cmda_odelay, >0 -program with this fraction of clk period from the margin
dqsi_safe_phase=dqsi_safe_phase, dqsi_safe_phase=dqsi_safe_phase,
ra = ra ^ ((1 << vrlg.ADDRESS_NUMBER)-1), # 0, ra = ra ^ ((1 << vrlg.ADDRESS_NUMBER)-1), # 0,
ba = ba ^ ((1 << num_ba)-1), # 0, ba = ba ^ ((1 << num_ba)-1), # 0,
quiet=quiet+1, #1, quiet=quiet, #+1, #1,
single=True) # single=False) single=True) # single=False)
self.adjustment_state['addr_meas']=[pass1,pass2] self.adjustment_state['addr_meas']=[pass1,pass2]
if (quiet<4): if (quiet<4):
...@@ -3279,6 +3281,9 @@ class X393McntrlAdjust(object): ...@@ -3279,6 +3281,9 @@ class X393McntrlAdjust(object):
print ("?", end=" ") print ("?", end=" ")
print() print()
return [pass1,pass2] return [pass1,pass2]
if quiet<3:
print("Writing good data to ra=0x%x, ba = 0x%x" %(ra,ba))
dly_steps=self.x393_mcntrl_timing.get_dly_steps() dly_steps=self.x393_mcntrl_timing.get_dly_steps()
numPhaseSteps= int(dly_steps['SDCLK_PERIOD']/dly_steps['PHASE_STEP']+0.5) numPhaseSteps= int(dly_steps['SDCLK_PERIOD']/dly_steps['PHASE_STEP']+0.5)
...@@ -3297,6 +3302,10 @@ class X393McntrlAdjust(object): ...@@ -3297,6 +3302,10 @@ class X393McntrlAdjust(object):
inv_ra=ra ^ ((1 << vrlg.ADDRESS_NUMBER)-1) inv_ra=ra ^ ((1 << vrlg.ADDRESS_NUMBER)-1)
ca= ra & ((1 << vrlg.COLADDR_NUMBER) -1) ca= ra & ((1 << vrlg.COLADDR_NUMBER) -1)
inv_ba=ba ^ ((1 << num_ba)-1) inv_ba=ba ^ ((1 << num_ba)-1)
print ("quiet=",quiet)
if quiet<4:
print("Writing good data to ra=0x%x, ba = 0x%x, ca = 0x%x, refresh will use: inv_ra = 0x%x, inv_ba=0x%x" %(ra,ba,ca,inv_ra,inv_ba))
if not "cmda_bspe" in self.adjustment_state: if not "cmda_bspe" in self.adjustment_state:
raise Exception ("No cmda_odelay data is available. 'adjust_cmda_odelay 0 1 0.1 3' command should run first.") raise Exception ("No cmda_odelay data is available. 'adjust_cmda_odelay 0 1 0.1 3' command should run first.")
#create a list of None/optimal cmda determined earlier #create a list of None/optimal cmda determined earlier
...@@ -3325,7 +3334,12 @@ class X393McntrlAdjust(object): ...@@ -3325,7 +3334,12 @@ class X393McntrlAdjust(object):
good_patt=0xaaaa good_patt=0xaaaa
bad_patt = good_patt ^ 0xffff bad_patt = good_patt ^ 0xffff
# find first suitable phase # find first suitable phase
for phase in range(numPhaseSteps): """
phase=0 seems to be bad (during wlev), ***temporarily*** just start from 90 degrees shift
"""
# for phase in range(numPhaseSteps):
for phase_tmp in range(numPhaseSteps):
phase = (phase_tmp + (numPhaseSteps//4)) % numPhaseSteps
try: try:
ph_dlys= self.get_all_delays(phase=phase, ph_dlys= self.get_all_delays(phase=phase,
filter_cmda= DFLT_DLY_FILT, # may be special case: 'S<safe_phase_as_float_number> filter_cmda= DFLT_DLY_FILT, # may be special case: 'S<safe_phase_as_float_number>
...@@ -3336,7 +3350,7 @@ class X393McntrlAdjust(object): ...@@ -3336,7 +3350,7 @@ class X393McntrlAdjust(object):
cost= None, cost= None,
forgive_missing=False, forgive_missing=False,
maxPhaseErrorsPS = maxPhaseErrorsPS, #CMDA, DQSI, DQSO maxPhaseErrorsPS = maxPhaseErrorsPS, #CMDA, DQSI, DQSO
quiet= quiet) quiet= quiet-1) # quiet)
if not ph_dlys is None: if not ph_dlys is None:
break break
except: except:
...@@ -3353,8 +3367,11 @@ class X393McntrlAdjust(object): ...@@ -3353,8 +3367,11 @@ class X393McntrlAdjust(object):
inv_ba, inv_ba,
0) # verbose=0 0) # verbose=0
# set usable timing, enable refresh # set usable timing, enable refresh
if quiet <3 : # if quiet <3 :
if quiet < 4 :
print ("+++ dqsi_safe_phase=",dqsi_safe_phase) print ("+++ dqsi_safe_phase=",dqsi_safe_phase)
print ("Setting all delays to write good/bad data, phase=",phase)
used_delays=self.set_delays(phase=phase, used_delays=self.set_delays(phase=phase,
filter_cmda=DFLT_DLY_FILT, # may be special case: 'S<safe_phase_as_float_number> filter_cmda=DFLT_DLY_FILT, # may be special case: 'S<safe_phase_as_float_number>
filter_dqsi=DFLT_DLY_FILT, filter_dqsi=DFLT_DLY_FILT,
...@@ -3365,15 +3382,15 @@ class X393McntrlAdjust(object): ...@@ -3365,15 +3382,15 @@ class X393McntrlAdjust(object):
refresh=True, refresh=True,
forgive_missing=True, forgive_missing=True,
maxPhaseErrorsPS=maxPhaseErrorsPS, maxPhaseErrorsPS=maxPhaseErrorsPS,
quiet=quiet) quiet=0) # quiet) # To see what delays where used when writing
if used_delays is None: if used_delays is None:
raise Exception("measure_addr_odelay(): failed to set phase = %d"%(phase)) # raise Exception("measure_addr_odelay(): failed to set phase = %d"%(phase)) #
#Write 0xaaaa pattern to correct block (all used words), address number - to all with a single bit different #Write 0xaaaa pattern to correct block (all used words), address number - to all with a single bit different
self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+3,sel_wr) self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+3,sel_wr)
#prepare and writ 'correct' block: #prepare and writ 'correct' block:
wdata16_good=(good_patt,)*(8*(nbursts+3)) wdata16_good=(good_patt,)*(8*(nbursts+7)) #3))
wdata32_good=convert_mem16_to_w32(wdata16_good) wdata32_good=convert_mem16_to_w32(wdata16_good)
wdata16_bad=(bad_patt,)*(8*(nbursts+3)) wdata16_bad=(bad_patt,)*(8*(nbursts+7)) #3))
wdata32_bad=convert_mem16_to_w32(wdata16_bad) wdata32_bad=convert_mem16_to_w32(wdata16_bad)
# comp32_good= wdata32_good[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32 # comp32_good= wdata32_good[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
# comp32_bad= wdata32_bad[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32 # comp32_bad= wdata32_bad[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
...@@ -3381,10 +3398,17 @@ class X393McntrlAdjust(object): ...@@ -3381,10 +3398,17 @@ class X393McntrlAdjust(object):
comp32_bad= wdata32_bad[4:(nbursts*4)+2] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32 comp32_bad= wdata32_bad[4:(nbursts*4)+2] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_good,quiet) # fill block memory (channel, page, number) # self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_good,quiet) # fill block memory (channel, page, number)
self.x393_pio_sequences.set_write_block(ba,ra,ca,nbursts+3,extraTgl,sel_wr) # set sequence to write 'correct' block self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_good,0 ) # fill block memory (channel, page, number)
self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+3,sel_rd) # set sequence to read block (will always be the same address) self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_good,0 ) # fill block memory (channel, page, number)
self.x393_pio_sequences.set_write_block(ba,ra,ca,nbursts+7,extraTgl,sel_wr) # 3,extraTgl,sel_wr) # set sequence to write 'correct' block
self.x393_pio_sequences.set_write_block(ba,ra,ca,nbursts+7,extraTgl,sel_wr) #3,extraTgl,sel_wr)# set sequence to write 'correct' block ######
# self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+3,sel_rd) # set sequence to read block (will always be the same address)
self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+7,sel_rd) # set sequence to read block (will always be the same address)
self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write 'correct' block self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write 'correct' block
self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write 'correct' block ################# Repeat
#prepare and write all alternative blocks (different by one address/bank #prepare and write all alternative blocks (different by one address/bank
self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_bad,quiet) # fill block memory (channel, page, number) self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_bad,quiet) # fill block memory (channel, page, number)
raba_bits=[] raba_bits=[]
...@@ -3393,12 +3417,15 @@ class X393McntrlAdjust(object): ...@@ -3393,12 +3417,15 @@ class X393McntrlAdjust(object):
for addr_bit in range(vrlg.ADDRESS_NUMBER): for addr_bit in range(vrlg.ADDRESS_NUMBER):
raba_bits.append((addr_bit,None)) raba_bits.append((addr_bit,None))
ra_alt=ra ^ (1<<addr_bit) ra_alt=ra ^ (1<<addr_bit)
self.x393_pio_sequences.set_write_block(ba,ra_alt,ca,nbursts+3,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block # self.x393_pio_sequences.set_write_block(ba,ra_alt,ca,nbursts+3,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block
self.x393_pio_sequences.set_write_block(ba,ra_alt,ca,nbursts+7,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block
self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write alternative block self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write alternative block
for bank_bit in range(num_ba): for bank_bit in range(num_ba):
raba_bits.append((None,bank_bit)) raba_bits.append((None,bank_bit))
ba_alt=ra ^ (1<<bank_bit) # ba_alt=ra ^ (1<<bank_bit) # Bug? 04.10.2016
self.x393_pio_sequences.set_write_block(ba_alt,ra,ca,nbursts+3,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block ba_alt=ba ^ (1<<bank_bit)
# self.x393_pio_sequences.set_write_block(ba_alt,ra,ca,nbursts+3,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block
self.x393_pio_sequences.set_write_block(ba_alt,ra,ca,nbursts+7,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block
self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write alternative block self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write alternative block
# For each valid phase, set valid delays, then find marginal delay for one bit (start with the longest available delay? # For each valid phase, set valid delays, then find marginal delay for one bit (start with the longest available delay?
# if got for one bit - try other bits in vicinity # if got for one bit - try other bits in vicinity
...@@ -3431,14 +3458,12 @@ class X393McntrlAdjust(object): ...@@ -3431,14 +3458,12 @@ class X393McntrlAdjust(object):
elif buf==comp32_bad: elif buf==comp32_bad:
meas=False meas=False
else: else:
print ("Inconclusive result for comparing read data for phase=%d, addr_bit=%s, bank_bit=%s dly=%d"%(phase,str(addr_bit),str(bank_bit),dly)) print ("Inconclusive result for comparing read data for phase=%d, addr_bit=%s, bank_bit=%s dly=%d"%(phase,str(addr_bit),str(bank_bit),dly), end = " ")
# print ("Data read from memory=",buf, "(",convert_w32_to_mem16(buf),")") # print ("Data read from memory=",buf, "(",convert_w32_to_mem16(buf),")")
print ("Data read from memory=%s(%s)"%(self.hex_list(buf),self.hex_list(convert_w32_to_mem16(buf)))) print ("Data read from memory=%s(%s)"%(self.hex_list(buf),self.hex_list(convert_w32_to_mem16(buf))))
#hex_list #hex_list
# print ("Expected 'good' data=",comp32_good, "(",convert_w32_to_mem16(comp32_good),")") # print ("Expected 'good' data=%s(%s)"%(self.hex_list(comp32_good),self.hex_list(convert_w32_to_mem16(comp32_good))))
print ("Expected 'good' data=%s(%s)"%(self.hex_list(comp32_good),self.hex_list(convert_w32_to_mem16(comp32_good)))) # print ("Expected 'bad' data=%s(%s)"%(self.hex_list(comp32_bad),self.hex_list(convert_w32_to_mem16(comp32_bad))))
# print ("Expected 'bad' data=", comp32_bad, "(",convert_w32_to_mem16(comp32_bad),")")
print ("Expected 'bad' data=%s(%s)"%(self.hex_list(comp32_bad),self.hex_list(convert_w32_to_mem16(comp32_bad))))
meas=None meas=None
meas_cache[dly]=meas meas_cache[dly]=meas
if not meas is None: if not meas is None:
...@@ -5727,6 +5752,10 @@ write_settings= { ...@@ -5727,6 +5752,10 @@ write_settings= {
Calculate finedelay corrections and finally optimal delay value for each line each phase Calculate finedelay corrections and finally optimal delay value for each line each phase
""" """
# self.load_hardcoded_data() # TODO: TEMPORARY - remove later # self.load_hardcoded_data() # TODO: TEMPORARY - remove later
quiet = 0 # 04.10.2016
try: try:
# addr_odelay=self.adjustment_state['addr_odelay_meas'] # addr_odelay=self.adjustment_state['addr_odelay_meas']
addr_odelay=self.adjustment_state['addr_meas'] addr_odelay=self.adjustment_state['addr_meas']
......
py393/x393_pio_sequences.py
View file @ 2008d6d4
...@@ -1152,7 +1152,8 @@ class X393PIOSequences(object): ...@@ -1152,7 +1152,8 @@ class X393PIOSequences(object):
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately) self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
buf=self.x393_mcntrl_buffers.read_block_buf_chn (0, 0, numBufWords, (0,1)[quiet<1]) # chn=0, page=0, number of 32-bit words=32, show_rslt buf=self.x393_mcntrl_buffers.read_block_buf_chn (0, 0, numBufWords, (0,1)[quiet<1]) # chn=0, page=0, number of 32-bit words=32, show_rslt
#calculate 1-s ratio for both lanes #calculate 1-s ratio for both lanes
rslt=[0.0,0.0,0.0] # last word - number of "problem" bytes that have non-ones in bits [7:1] # rslt=[0.0,0.0,0.0] # last word - number of "problem" bytes that have non-ones in bits [7:1]
rslt=[0.0,0.0,0.0,0.0] # last 2 words - number of "problem" bytes that have non-ones in bits [7:1] or byte is not the same
for i in range(0,numBufWords): for i in range(0,numBufWords):
rslt[i & 1] += ((buf[i] & 1) + rslt[i & 1] += ((buf[i] & 1) +
...@@ -1164,11 +1165,25 @@ class X393PIOSequences(object): ...@@ -1164,11 +1165,25 @@ class X393PIOSequences(object):
(0,1)[(buf[i] & 0xfe00) != 0]+ (0,1)[(buf[i] & 0xfe00) != 0]+
(0,1)[(buf[i] & 0xfe0000) != 0]+ (0,1)[(buf[i] & 0xfe0000) != 0]+
(0,1)[(buf[i] & 0xfe000000) != 0]) (0,1)[(buf[i] & 0xfe000000) != 0])
bm = buf[i] & 0x01010101
bm |= (bm << 1)
bm |= (bm << 2)
bm |= (bm << 4)
bm ^= buf[i]
rslt[3] += ((0,1)[(bm & 0xfe) != 0]+
(0,1)[(bm & 0xfe00) != 0]+
(0,1)[(bm & 0xfe0000) != 0]+
(0,1)[(bm & 0xfe000000) != 0])
for i in range(2): for i in range(2):
rslt[i]/=2*numBufWords rslt[i]/=2*numBufWords
rslt[2]/=4*numBufWords rslt[2]/=4*numBufWords
rslt[3]/=4*numBufWords
if quiet <1: if quiet <1:
print ("WLEV lanes ratios: %f %f, non 0x00/0x01 bytes: %f"%(rslt[0],rslt[1],rslt[2])) print ("WLEV lanes ratios: %f %f, non 0x00/0x01 byte: %f, non 0x00/0xffs: %f"%(rslt[0],rslt[1],rslt[2],rslt[3]))
if (rslt[3] < rslt[2]):
rslt[2] = rslt[3]
return rslt return rslt
def read_levelling(self, def read_levelling(self,
......
py393/x393_sensor.py
View file @ 2008d6d4
...@@ -299,7 +299,7 @@ class X393Sensor(object): ...@@ -299,7 +299,7 @@ class X393Sensor(object):
else: else:
return 3 return 3
if verbose>0: if verbose>1:
print ("func_sensor_i2c_command(): rst_cmd= ",rst_cmd,", run_cmd=",run_cmd,", active_sda = ",active_sda,", early_release_0 = ",early_release_0, print ("func_sensor_i2c_command(): rst_cmd= ",rst_cmd,", run_cmd=",run_cmd,", active_sda = ",active_sda,", early_release_0 = ",early_release_0,
", sda=",sda,", scl=",scl) ", sda=",sda,", scl=",scl)
...@@ -1279,13 +1279,19 @@ $boards=array ( ...@@ -1279,13 +1279,19 @@ $boards=array (
'1' => array ('model' => '10359', 'scl' =>280,'sda' => 296) // H6, J5 '1' => array ('model' => '10359', 'scl' =>280,'sda' => 296) // H6, J5
); );
cd /usr/local/verilog/; test_mcntrl.py -x @hargs #cd /usr/local/verilog/; test_mcntrl.py -x @hargs
cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "PAR12" setupSensorsPower "PAR12"
measure_all "*DI" measure_all "*DI"
program_status_sensor_io all 1 0 program_status_sensor_io all 1 0
print_status_sensor_io all print_status_sensor_io all
setSensorClock setSensorClock
checkSclSda 1
cat /usr/local/verilog/x359.bit > /dev/sfpgaconfjtag1
#jtag_set_pgm_mode 0 1 #jtag_set_pgm_mode 0 1
#jtag_set_pgm_mode 1 1 #jtag_set_pgm_mode 1 1
#jtag_set_pgm_mode 2 1 #jtag_set_pgm_mode 2 1
...@@ -1437,7 +1443,7 @@ drivers/elphel/fpgajtag353.c:1416 [fpgajtag]fpga_jtag_exit =_ "unregistering dri ...@@ -1437,7 +1443,7 @@ drivers/elphel/fpgajtag353.c:1416 [fpgajtag]fpga_jtag_exit =_ "unregistering dri
root@elphel393:/sys/kernel/debug/dynamic_debug# echo 'file drivers/elphel/fpgajtag353.c +p' > control root@elphel393:/sys/kernel/debug/dynamic_debug# echo 'file drivers/elphel/fpgajtag353.c +p' > control
afpgaconfjtag jtagraw memory_bandwidth mtd4ro ram2 stderr tty18 tty30 tty43 tty56 ttyS1 afpgaconfjtag jtagraw memory_bandwidth mtd4ro ram2 stderr tty18 tty30 tty43 tty56 ttyS1
block kmem mmcblk0 mtdblock0 ram3 stdin tty19 tty31 tty44 tty57 ttyS2 block kmem mmcblk0 mtdblock0 ram3 stdin tty19 tty31 tty44 tty57 ttyS2
char kmsg mmcblk0p1 mtdblock1 random stdout tty2 tty32 tty45 tty58 ttyS3 char kmsg mmcblk0p1 mtdblock1 random stdout tty2 tty32 tty45 tty58 ttyS3
console log mmcblk0p2 mtdblock2 rtc0 tty tty20 tty33 tty46 tty59 ubi_ctrl console log mmcblk0p2 mtdblock2 rtc0 tty tty20 tty33 tty46 tty59 ubi_ctrl
......
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