Commit 1ec7dca8 authored by Andrey Filippov's avatar Andrey Filippov

fixing texts

parent 445798f8
......@@ -10,195 +10,195 @@
[size] 1814 1171
[pos] 0 40
*-15.492632 1795000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] dct_tests_03.
[treeopen] dct_tests_03.dtt_iv_8x8_i.
[treeopen] dct_tests_03.dtt_iv_8x8r_i.
[treeopen] dct_tests_04.
[treeopen] dct_tests_04.dtt_iv_8x8_i.
[treeopen] dct_tests_04.dtt_iv_8x8r_i.
[sst_width] 318
[signals_width] 284
[sst_expanded] 1
[sst_vpaned_height] 344
@420
dct_tests_03.i
dct_tests_03.i1
dct_tests_03.j
dct_tests_04.i
dct_tests_04.i1
dct_tests_04.j
@28
dct_tests_03.CLK
dct_tests_03.RST
dct_tests_04.CLK
dct_tests_04.RST
[color] 2
dct_tests_03.start
dct_tests_04.start
[color] 2
dct_tests_03.start2
dct_tests_04.start2
@22
dct_tests_03.mode_in[1:0]
dct_tests_04.mode_in[1:0]
@8420
dct_tests_03.x_in_2d[24:0]
dct_tests_04.x_in_2d[24:0]
@22
dct_tests_03.mode_out[1:0]
dct_tests_04.mode_out[1:0]
@8420
dct_tests_03.d_out_2dr[24:0]
dct_tests_04.d_out_2dr[24:0]
@800200
-dtt_iv8x8_direct
@28
dct_tests_03.dtt_iv_8x8_i.rst
dct_tests_03.dtt_iv_8x8_i.clk
dct_tests_03.dtt_iv_8x8_i.start
dct_tests_04.dtt_iv_8x8_i.rst
dct_tests_04.dtt_iv_8x8_i.clk
dct_tests_04.dtt_iv_8x8_i.start
@22
dct_tests_03.dtt_iv_8x8_i.mode[1:0]
dct_tests_04.dtt_iv_8x8_i.mode[1:0]
@28
dct_tests_03.dtt_iv_8x8_i.pre_last_in
dct_tests_03.dtt_iv_8x8_i.pre_busy
dct_tests_04.dtt_iv_8x8_i.pre_last_in
dct_tests_04.dtt_iv_8x8_i.pre_busy
@c00200
-debug
@28
dct_tests_03.dtt_iv_8x8_i.transpose_start
dct_tests_04.dtt_iv_8x8_i.transpose_start
@22
dct_tests_03.dtt_iv_8x8_i.transpose_debug_di[7:0]
dct_tests_04.dtt_iv_8x8_i.transpose_debug_di[7:0]
@8022
dct_tests_03.dtt_iv_8x8_i.transpose_debug_di[7:0]
dct_tests_04.dtt_iv_8x8_i.transpose_debug_di[7:0]
@c00022
dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
@28
(0)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(1)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(2)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(3)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(4)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(5)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(6)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(7)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
@28
(0)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(1)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(2)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(3)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(4)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(5)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(6)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(7)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
@1401200
-group_end
@c08022
dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
@28
(0)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(1)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(2)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(3)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(4)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(5)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(6)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
(7)dct_tests_03.dtt_iv_8x8_i.transpose_wa[7:0]
dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
@28
(0)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(1)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(2)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(3)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(4)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(5)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(6)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
(7)dct_tests_04.dtt_iv_8x8_i.transpose_wa[7:0]
@1401200
-group_end
@28
(0)dct_tests_03.dtt_iv_8x8_i.transpose_we[1:0]
dct_tests_03.dtt_iv_8x8_i.pre_dsth
(0)dct_tests_04.dtt_iv_8x8_i.transpose_we[1:0]
dct_tests_04.dtt_iv_8x8_i.pre_dsth
@8022
dct_tests_03.dtt_iv_8x8_i.transpose_cntr[6:0]
dct_tests_04.dtt_iv_8x8_i.transpose_cntr[6:0]
@22
dct_tests_03.dtt_iv_8x8_i.transpose_ra[7:0]
dct_tests_04.dtt_iv_8x8_i.transpose_ra[7:0]
@28
dct_tests_03.dtt_iv_8x8_i.dctv_start_0_r
dct_tests_03.dtt_iv_8x8_i.dctv_start_1_r
dct_tests_04.dtt_iv_8x8_i.dctv_start_0_r
dct_tests_04.dtt_iv_8x8_i.dctv_start_1_r
@800028
dct_tests_03.dtt_iv_8x8_i.pre2_dstv[1:0]
dct_tests_04.dtt_iv_8x8_i.pre2_dstv[1:0]
@28
(0)dct_tests_03.dtt_iv_8x8_i.pre2_dstv[1:0]
(1)dct_tests_03.dtt_iv_8x8_i.pre2_dstv[1:0]
(0)dct_tests_04.dtt_iv_8x8_i.pre2_dstv[1:0]
(1)dct_tests_04.dtt_iv_8x8_i.pre2_dstv[1:0]
@1001200
-group_end
@c00028
[color] 2
dct_tests_03.dtt_iv_8x8_i.dctv_out_we[1:0]
dct_tests_04.dtt_iv_8x8_i.dctv_out_we[1:0]
@28
(0)dct_tests_03.dtt_iv_8x8_i.dctv_out_we[1:0]
(1)dct_tests_03.dtt_iv_8x8_i.dctv_out_we[1:0]
(0)dct_tests_04.dtt_iv_8x8_i.dctv_out_we[1:0]
(1)dct_tests_04.dtt_iv_8x8_i.dctv_out_we[1:0]
@1401200
-group_end
@28
dct_tests_03.dtt_iv_8x8_i.pre_dstv
dct_tests_04.dtt_iv_8x8_i.pre_dstv
@200
-alt
@28
dct_tests_03.dtt_iv_8x8_i.dstv
dct_tests_03.dtt_iv_8x8_i.out_sel
dct_tests_03.dtt_iv_8x8_i.out_run
dct_tests_04.dtt_iv_8x8_i.dstv
dct_tests_04.dtt_iv_8x8_i.out_sel
dct_tests_04.dtt_iv_8x8_i.out_run
@22
dct_tests_03.dtt_iv_8x8_i.out_cntr[6:0]
dct_tests_04.dtt_iv_8x8_i.out_cntr[6:0]
@28
dct_tests_03.dtt_iv_8x8_i.out_sel
dct_tests_04.dtt_iv_8x8_i.out_sel
@c00022
dct_tests_03.dtt_iv_8x8_i.out_wa[3:0]
dct_tests_04.dtt_iv_8x8_i.out_wa[3:0]
@28
(0)dct_tests_03.dtt_iv_8x8_i.out_wa[3:0]
(1)dct_tests_03.dtt_iv_8x8_i.out_wa[3:0]
(2)dct_tests_03.dtt_iv_8x8_i.out_wa[3:0]
(3)dct_tests_03.dtt_iv_8x8_i.out_wa[3:0]
(0)dct_tests_04.dtt_iv_8x8_i.out_wa[3:0]
(1)dct_tests_04.dtt_iv_8x8_i.out_wa[3:0]
(2)dct_tests_04.dtt_iv_8x8_i.out_wa[3:0]
(3)dct_tests_04.dtt_iv_8x8_i.out_wa[3:0]
@1401200
-group_end
@28
dct_tests_03.dtt_iv_8x8_i.out_we
dct_tests_03.dtt_iv_8x8_i.sub16
dct_tests_03.dtt_iv_8x8_i.inc16
dct_tests_03.dtt_iv_8x8_i.start_out
dct_tests_04.dtt_iv_8x8_i.out_we
dct_tests_04.dtt_iv_8x8_i.sub16
dct_tests_04.dtt_iv_8x8_i.inc16
dct_tests_04.dtt_iv_8x8_i.start_out
@200
-top
@22
dct_tests_03.out_ram_wa[4:0]
dct_tests_04.out_ram_wa[4:0]
@28
dct_tests_03.out_ram_cntr
dct_tests_03.out_ram_wah
dct_tests_04.out_ram_cntr
dct_tests_04.out_ram_wah
@22
dct_tests_03.out_wa[3:0]
dct_tests_04.out_wa[3:0]
@28
dct_tests_03.out_we
dct_tests_03.out_ram_ren
dct_tests_03.out_ram_regen
dct_tests_04.out_we
dct_tests_04.out_ram_ren
dct_tests_04.out_ram_regen
@22
dct_tests_03.out_ram_ra[5:0]
dct_tests_04.out_ram_ra[5:0]
@28
dct_tests_03.out_pre_first
dct_tests_03.out_ram_dv
dct_tests_04.out_pre_first
dct_tests_04.out_ram_dv
@1401200
-debug
@22
dct_tests_03.dtt_iv_8x8_i.mode_out[1:0]
dct_tests_04.dtt_iv_8x8_i.mode_out[1:0]
@28
dct_tests_03.dtt_iv_8x8_i.pre_busy
dct_tests_04.dtt_iv_8x8_i.pre_busy
@c00200
-direct_internal
@28
dct_tests_03.dtt_iv_8x8_i.dcth_en0
dct_tests_03.dtt_iv_8x8_i.dcth_en1
dct_tests_03.dtt_iv_8x8_i.dcth_start_0_r
dct_tests_03.dtt_iv_8x8_i.dcth_start_1_r
dct_tests_04.dtt_iv_8x8_i.dcth_en0
dct_tests_04.dtt_iv_8x8_i.dcth_en1
dct_tests_04.dtt_iv_8x8_i.dcth_start_0_r
dct_tests_04.dtt_iv_8x8_i.dcth_start_1_r
@22
dct_tests_03.dtt_iv_8x8_i.mode[1:0]
dct_tests_03.dtt_iv_8x8_i.mode_h[1:0]
dct_tests_03.dtt_iv_8x8_i.mode_h_late[1:0]
dct_tests_03.dtt_iv_8x8_i.mode_v[1:0]
dct_tests_03.dtt_iv_8x8_i.mode_out[1:0]
dct_tests_04.dtt_iv_8x8_i.mode[1:0]
dct_tests_04.dtt_iv_8x8_i.mode_h[1:0]
dct_tests_04.dtt_iv_8x8_i.mode_h_late[1:0]
dct_tests_04.dtt_iv_8x8_i.mode_v[1:0]
dct_tests_04.dtt_iv_8x8_i.mode_out[1:0]
@28
dct_tests_03.dtt_iv_8x8_i.dctv_start_0_w
dct_tests_04.dtt_iv_8x8_i.dctv_start_0_w
@22
dct_tests_03.dtt_iv_8x8_i.dctv_start_1_w
dct_tests_04.dtt_iv_8x8_i.dctv_start_1_w
@800028
dct_tests_03.dtt_iv_8x8_i.pre2_dsth[1:0]
dct_tests_04.dtt_iv_8x8_i.pre2_dsth[1:0]
@28
(0)dct_tests_03.dtt_iv_8x8_i.pre2_dsth[1:0]
(1)dct_tests_03.dtt_iv_8x8_i.pre2_dsth[1:0]
(0)dct_tests_04.dtt_iv_8x8_i.pre2_dsth[1:0]
(1)dct_tests_04.dtt_iv_8x8_i.pre2_dsth[1:0]
@1001200
-group_end
@200
-
@800028
dct_tests_03.dtt_iv_8x8_i.pre2_dstv[1:0]
dct_tests_04.dtt_iv_8x8_i.pre2_dstv[1:0]
@28
(0)dct_tests_03.dtt_iv_8x8_i.pre2_dstv[1:0]
(1)dct_tests_03.dtt_iv_8x8_i.pre2_dstv[1:0]
(0)dct_tests_04.dtt_iv_8x8_i.pre2_dstv[1:0]
(1)dct_tests_04.dtt_iv_8x8_i.pre2_dstv[1:0]
@800200
-g3
@28
dct_tests_03.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.start
dct_tests_03.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.dst_in
dct_tests_03.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.dst_out
dct_tests_04.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.start
dct_tests_04.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.dst_in
dct_tests_04.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.dst_out
@1000200
-g3
@28
dct_tests_03.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.start
dct_tests_03.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.dst_in
dct_tests_03.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.dst_out
dct_tests_04.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.start
dct_tests_04.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.dst_in
dct_tests_04.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.dst_out
@200
-
@1001200
......@@ -210,11 +210,11 @@ dct_tests_03.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.dst_out
@800200
-dtt_iv8x8_inv
@29
dct_tests_03.dtt_iv_8x8r_i.clk
dct_tests_04.dtt_iv_8x8r_i.clk
@28
dct_tests_03.dtt_iv_8x8r_i.start
dct_tests_03.dtt_iv_8x8r_i.mode[1:0]
dct_tests_03.dtt_iv_8x8r_i.mode_out[1:0]
dct_tests_04.dtt_iv_8x8r_i.start
dct_tests_04.dtt_iv_8x8r_i.mode[1:0]
dct_tests_04.dtt_iv_8x8r_i.mode_out[1:0]
@800200
-inv_internals
@200
......
/*!
* <b>Module:</b>dct_tests_03
* @file dct_tests_03.tf
* <b>Module:</b>dct_tests_04
* @file dct_tests_04.tf
* @date 2016-12-02
* @author Andrey Filippov
*
......@@ -11,12 +11,12 @@
*
* <b>License:</b>
*
*dct_tests_03.tf is free software; you can redistribute it and/or modify
*dct_tests_04.tf is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dct_tests_03.tf is distributed in the hope that it will be useful,
* dct_tests_04.tf is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
......@@ -41,11 +41,11 @@
// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
// will reduce needed resources
//`define DCT_INPUT_UNITY
module dct_tests_03 ();
// parameter fstname="dct_tests_03.fst";
module dct_tests_04 ();
// parameter fstname="dct_tests_04.fst";
`ifdef IVERILOG
`ifdef NON_VDT_ENVIROMENT
parameter fstname="dct_tests_03.fst";
parameter fstname="dct_tests_04.fst";
`else
`include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT
......@@ -57,7 +57,7 @@ module dct_tests_03 ();
`include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT
`else
parameter fstname = "dct_tests_03.fst";
parameter fstname = "dct_tests_04.fst";
`endif // CVC
`endif // IVERILOG
......@@ -158,7 +158,7 @@ module dct_tests_03 ();
always #(CLK_PERIOD/2) CLK = ~CLK;
initial begin
$dumpfile(fstname);
$dumpvars(0,dct_tests_03); // SuppressThisWarning VEditor
$dumpvars(0,dct_tests_04); // SuppressThisWarning VEditor
#100;
RST = 0;
#100;
......
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