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Commit 1db76b02 authored by Andrey Filippov's avatar Andrey Filippov
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Comparing mclt Bayer with Java results, fixing bugs

parent 84e3107c
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dsp/mclt16x16_bayer.v
View file @ 1db76b02
......@@ -41,7 +41,7 @@
module mclt16x16_bayer#(
parameter SHIFT_WIDTH = 7, // bits in shift (7 bits - fractional)
parameter PIX_ADDR_WIDTH = 9, // number of pixel address width
// parameter EXT_PIX_LATENCY = 2, // external pixel buffer a->d latency
parameter EXT_PIX_LATENCY = 2, // external pixel buffer a->d latency (may increase to 4 for gamma)
parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM
parameter PIXEL_WIDTH = 16, // input pixel width (unsigned)
parameter WND_WIDTH = 18, // input pixel width (unsigned)
......@@ -104,12 +104,12 @@ module mclt16x16_bayer#(
reg inv_checker_r3;
reg inv_checker_r4;
wire [1:0] signs; //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
wire [6:0] phases; //!< other signals
wire [1:0] signs; //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
wire [6:0] phases; //!< other signals
wire signed [WND_WIDTH-1:0] window_w;
wire signed [WND_WIDTH-1:0] window_w;
wire signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
wire signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
reg [6:0] dtt_in_cntr; //
......@@ -175,7 +175,7 @@ module mclt16x16_bayer#(
end
// if (!phases[14]) dtt_in_cntr <= 0;
if (!dtt_we) dtt_in_cntr <= 0;
if (!dtt_we) dtt_in_cntr <= 0;
else dtt_in_cntr <= dtt_in_cntr + 1;
start_dtt <= dtt_in_cntr == DTT_IN_DELAY;
......@@ -199,23 +199,20 @@ module mclt16x16_bayer#(
end
`ifdef DSP_ACCUM_FOLD
localparam ADDR_DLYL = 4 - EXT_PIX_LATENCY; // 4'h2; // 3 for mpy, 2 - for dsp
`else
localparam ADDR_DLYL = 5 - EXT_PIX_LATENCY; // 4'h3; // 3 for mpy, 2 - for dsp
`endif
mclt_bayer_fold #(
.SHIFT_WIDTH (SHIFT_WIDTH),
.PIX_ADDR_WIDTH (PIX_ADDR_WIDTH),
.ADDR_DLY (4'h1), // 2 for mpy, 1 - for dsp
.ADDR_DLY (ADDR_DLYL), // 3 for mpy, 2 - for dsp
.COORD_WIDTH (COORD_WIDTH),
// .PIXEL_WIDTH (PIXEL_WIDTH),
.WND_WIDTH (WND_WIDTH)
// .OUT_WIDTH (OUT_WIDTH),
// .DTT_IN_WIDTH (DTT_IN_WIDTH),
// .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
// .OUT_RSHIFT (OUT_RSHIFT),
// .OUT_RSHIFT2 (OUT_RSHIFT2),
// .DSP_B_WIDTH (DSP_B_WIDTH),
// .DSP_A_WIDTH (DSP_A_WIDTH),
// .DSP_P_WIDTH (DSP_P_WIDTH),
// .DEAD_CYCLES (DEAD_CYCLES)
) mclt_bayer_fold_i (
.clk (clk), // input
.rst (rst), // input
......@@ -233,7 +230,6 @@ module mclt16x16_bayer#(
.signs (signs), // output[1:0]
.phases (phases), // output[7:0]
.var_pre2_first(var_pre2_first), // output
// .var_first (), // var_first), // output reg
.pre_last_in (pre_last_in_w)// output reg
);
......@@ -268,9 +264,11 @@ module mclt16x16_bayer#(
wire dtt_inc16;
reg [4:0] dtt_out_ram_cntr;
reg [4:0] dtt_out_ram_wah;
reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to
reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to
reg [1:0] dtt_out_ram_wpage2; // later by 1 DTT
wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
reg dtt_start_first_fill;
reg dtt_start_second_fill;
reg [1:0] dtt_start_out; // start read out to sin/cos rotator
......@@ -305,7 +303,11 @@ module mclt16x16_bayer#(
dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;
if (dtt_start_first_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3];
dtt_start_second_fill<= dtt_start_fill & ~dtt_first_quad_out;
if (dtt_start_first_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3];
if (dtt_start_second_fill) dtt_out_ram_wpage2 <= dtt_out_ram_wpage;
if (rst) dtt_dly_cntr <= 0;
else if (dtt_start_first_fill) dtt_dly_cntr <= DTT_OUT_DELAY;
......@@ -320,21 +322,10 @@ module mclt16x16_bayer#(
if (rst) dtt_rd_regen_dv[3:1] <= 0;
else dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];
if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number
// if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number
if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage2, 7'b0}; //copy page number
else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
/*
dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5],
dtt_rd_cntr_pre[5]? (~dtt_rd_cntr_pre[4:0]) : dtt_rd_cntr_pre[4:0],
dtt_rd_cntr_pre[5]};
dtt_rd_ra1 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5],
dtt_rd_cntr_pre[5]? (~dtt_rd_cntr_pre[4:0]) : dtt_rd_cntr_pre[4:0],
~dtt_rd_cntr_pre[5]};
*/
dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[0]? (~dtt_rd_cntr_pre[6:2]) : dtt_rd_cntr_pre[6:2],
......@@ -362,8 +353,8 @@ module mclt16x16_bayer#(
.pix_sgn (signs), // input[1:0]
.window (window_w), // input[17:0] signed
.var_pre2_first (var_pre2_first), // input
.dtt_in (data_dtt_in), // output[24:0] signed
.dtt_in_dv (dtt_we) // output reg
.dtt_in (data_dtt_in), // output[24:0] signed
.dtt_in_dv (dtt_we) // output reg
);
......
dsp/mclt_baeyer_fold_accum.v
View file @ 1db76b02
......@@ -37,7 +37,7 @@
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
`define DSP_ACCUM_FOLD 1
//`define DSP_ACCUM_FOLD 1
module mclt_baeyer_fold_accum # (
parameter PIXEL_WIDTH = 16, // input pixel width (unsigned)
parameter WND_WIDTH = 18, // input pixel width (unsigned)
......@@ -49,15 +49,13 @@ module mclt_baeyer_fold_accum # (
)(
input clk,
input rst,
// input [5:0] phases,
input pre_phase,
input signed [PIXEL_WIDTH-1:0] pix_d, //!< pixel data
input signed [PIXEL_WIDTH-1:0] pix_d, //!< pixel data (should be 1 cycle later for `undef DSP_ACCUM_FOLD
input [1:0] pix_sgn, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
input signed [WND_WIDTH-1:0] window,
input var_pre2_first,
output signed [DTT_IN_WIDTH-1:0] dtt_in,
output dtt_in_dv
);
reg var_pre_first;
reg var_first;
......@@ -65,43 +63,6 @@ module mclt_baeyer_fold_accum # (
reg [6:0] phases;
`ifdef DSP_ACCUM_FOLD
reg dtt_in_dv_dsp_r;
reg signed [DTT_IN_WIDTH-1:0] dtt_in_dsp;
`else
wire [ 1:0] pix_sgn_d;
reg [PIXEL_WIDTH-1:0] pix_dr; // only for mpy to match dsp
reg signed [WND_WIDTH-1:0] window_r;
reg signed [PIXEL_WIDTH-1:0] pix_d_r; // registered pixel data (to be absorbed by MPY)
reg [ 1:0] pix_sgn_r;
reg signed [PIXEL_WIDTH + WND_WIDTH - 1:0] pix_wnd_r; // MSB not used: positive[PIXEL_WIDTH]*positive[WND_WIDTH]->positive[PIXEL_WIDTH+WND_WIDTH-1]
reg signed [DTT_IN_WIDTH-1:0] pix_wnd_r2; // pixels (positive) multiplied by window(positive), two MSBs == 2'b0 to prevent overflow
// rounding
// wire signed [DTT_IN_WIDTH-3:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]
wire signed [DTT_IN_WIDTH-2:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 1]
`ifdef ROUND
// + pix_wnd_r[PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH]
+ pix_wnd_r[PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH -1]
`endif
;
reg signed [DTT_IN_WIDTH-1:0] data_cc_r;
reg signed [DTT_IN_WIDTH-1:0] data_sc_r;
reg signed [DTT_IN_WIDTH-1:0] data_sc_r2; // data_sc_r delayed by 1 cycle
reg mode_mux;
reg dtt_in_dv_r;
reg signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
`endif
`ifdef DSP_ACCUM_FOLD
assign dtt_in = dtt_in_dsp;
assign dtt_in_dv = dtt_in_dv_dsp_r;
`else
assign dtt_in = data_dtt_in;
assign dtt_in_dv = dtt_in_dv_r;
`endif
always @ (posedge clk) begin
phases <= {phases[5:0], pre_phase};
......@@ -119,6 +80,12 @@ module mclt_baeyer_fold_accum # (
`ifdef DSP_ACCUM_FOLD
reg dtt_in_dv_dsp_r;
reg signed [DTT_IN_WIDTH-1:0] dtt_in_dsp;
assign dtt_in = dtt_in_dsp;
assign dtt_in_dv = dtt_in_dv_dsp_r;
always @ (posedge clk) begin
if (rst) dtt_in_dv_dsp_r <= 0;
else dtt_in_dv_dsp_r <= phases[5];
......@@ -223,13 +190,40 @@ module mclt_baeyer_fold_accum # (
);
`else
wire [ 1:0] pix_sgn_d;
/// reg [PIXEL_WIDTH-1:0] pix_dr; // only for mpy to match dsp
reg signed [WND_WIDTH-1:0] window_r;
reg signed [PIXEL_WIDTH-1:0] pix_d_r; // registered pixel data (to be absorbed by MPY)
reg [ 1:0] pix_sgn_r;
reg signed [PIXEL_WIDTH + WND_WIDTH - 1:0] pix_wnd_r; // MSB not used: positive[PIXEL_WIDTH]*positive[WND_WIDTH]->positive[PIXEL_WIDTH+WND_WIDTH-1]
reg signed [DTT_IN_WIDTH-1:0] pix_wnd_r2; // pixels (positive) multiplied by window(positive), two MSBs == 2'b0 to prevent overflow
// rounding
// wire signed [DTT_IN_WIDTH-3:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]
wire signed [DTT_IN_WIDTH-2:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 1]
`ifdef ROUND
// + pix_wnd_r[PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH]
+ pix_wnd_r[PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH -1]
`endif
;
reg signed [DTT_IN_WIDTH-1:0] data_cc_r;
reg signed [DTT_IN_WIDTH-1:0] data_sc_r;
reg signed [DTT_IN_WIDTH-1:0] data_sc_r2; // data_sc_r delayed by 1 cycle
reg mode_mux;
reg dtt_in_dv_r;
reg signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
assign dtt_in = data_dtt_in;
assign dtt_in_dv = dtt_in_dv_r;
always @ (posedge clk) begin
if (rst) dtt_in_dv_r <= 0;
else dtt_in_dv_r <= phases[6];
pix_dr <= pix_d;
/// pix_dr <= pix_d;
if (phases[1]) begin
pix_d_r <= pix_dr;
/// pix_d_r <= pix_dr;
pix_d_r <= pix_d;
window_r <= window;
end
if (phases[2]) pix_wnd_r <= pix_d_r * window_r; // 1 MSB is extra
......
dsp/mclt_bayer_fold.v
View file @ 1db76b02
......@@ -41,20 +41,9 @@
module mclt_bayer_fold#(
parameter SHIFT_WIDTH = 7, // bits in shift (7 bits - fractional)
parameter PIX_ADDR_WIDTH = 9, // number of pixel address width
// parameter EXT_PIX_LATENCY = 2, // external pixel buffer a->d latency
parameter ADDR_DLY = 4'h2, // extra delay of pixel address to match window delay
parameter ADDR_DLY = 4'h3, // extra delay of pixel address to match window delay
parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM
// parameter PIXEL_WIDTH = 16, // input pixel width (unsigned)
parameter WND_WIDTH = 18 // input pixel width (unsigned)
// parameter OUT_WIDTH = 25, // bits in dtt output
// parameter DTT_IN_WIDTH = 25, // bits in DTT input
// parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)
// parameter OUT_RSHIFT = 2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
// parameter OUT_RSHIFT2 = 0, // overall right shift for the second (vertical) pass
// parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
// parameter DSP_A_WIDTH = 25,
// parameter DSP_P_WIDTH = 48,
// parameter DEAD_CYCLES = 14 // start next block immedaitely, or with longer pause
)(
input clk, //!< system clock, posedge
input rst, //!< sync reset
......@@ -71,14 +60,12 @@ module mclt_bayer_fold#(
output pix_page, //!< copy pixel page (should be externally combined with first color)
output signed [WND_WIDTH-1:0] window, //!< msb==0, always positive
output [1:0] signs, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
// output [14:0] phases, //!< other signals
output [6:0] phases, //!< other signals
output var_pre2_first,//!< two ahead of first of 2 fold variants (4 for monochrome, 2 left for checker)
// output reg var_first, //!< first of 2 fold variants (4 for monochrome, 2 left for checker)
output reg pre_last_in //!< pre last data in
);
reg [6:0] in_cntr; // input phase counter
// reg [14:0] run_r; // run phase
reg [6:0] run_r; // run phase
reg [1:0] tile_size_r; // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
......@@ -86,9 +73,11 @@ module mclt_bayer_fold#(
reg [7:0] top_left_r0; // index of the 16x16 top left corner
reg [7:0] top_left_r; // index of the 16x16 top left corner
reg [1:0] valid_rows_r0;// 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels
// reg [1:0] valid_rows_r ;// correct latency for window rom
/// wire [ 9:0] fold_addr= {tile_size_r,inv_checker_r, in_cntr[0],in_cntr[6:1]};
wire [ 9:0] fold_addr= {tile_size_r,inv_checker_r, (valid_rows_r0==3)?in_cntr[0]:valid_rows_r0[0],in_cntr[6:1]};
wire [ 9:0] fold_addr= {tile_size_r,inv_checker_r, (valid_rows_r0==3)?
in_cntr[0]:
// valid_rows_r0[0],
~valid_rows_r0[0],
in_cntr[6:1]};
reg [SHIFT_WIDTH-1:0] x_shft_r0; // tile pixel X fractional shift (valid @ start)
reg [SHIFT_WIDTH-1:0] y_shft_r0; // tile pixel Y fractional shift (valid @ start)
reg [SHIFT_WIDTH-1:0] x_shft_r; // matching delay
......@@ -100,28 +89,16 @@ module mclt_bayer_fold#(
wire [PIX_ADDR_WIDTH-1:0] pix_a_w = {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};
reg [PIX_ADDR_WIDTH-1:0] pix_a_r;
wire [ 1:0] sgn_w = fold_rom_out[16 +: 2];
// reg blank_r; // blank window (latency 1 from fold_rom_out)
// wire blank_d; // delayed to matchwindow rom regrst
wire pre_page = in_cntr == 2; // valid 1 cycle before fold_rom_out
wire var_first_d; // adding subtracting first variant of 2 folds
// reg var_pre_first;
assign phases = run_r;
assign var_pre2_first = var_first_d;
// wire [ 3:0] bayer_1hot = { mpix_a_w[4] & mpix_a_w[0],
// mpix_a_w[4] & ~mpix_a_w[0],
// ~mpix_a_w[4] & mpix_a_w[0],
// ~mpix_a_w[4] & ~mpix_a_w[0]};
// wire mpix_use = |(bayer_d & bayer_1hot); //not disabled by bayer, valid with mpix_a_w
// wire mpix_use_d; // delayed
// reg mpix_use_r; // delayed
always @ (posedge clk) begin
if (rst) run_r <= 0;
// else run_r <= {run_r[13:0], start | (run_r[0] & ~(&in_cntr[6:0]))};
else run_r <= {run_r[5:0], start | (run_r[0] & ~(&in_cntr[6:0]))};
if (!run_r[0]) in_cntr <= 0;
......@@ -145,18 +122,6 @@ module mclt_bayer_fold#(
if (run_r[2]) pix_a_r <= pix_a_w + {1'b0, top_left_r};
/// if (in_cntr == 2) valid_rows_r <= valid_rows_r0;
/// blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]);
/// if (run_r[9]) var_pre_first <= var_first_d;
/// if (run_r[10]) begin
// var_first <= var_first_d;
/// var_first <= var_pre_first;
/// end
pre_last_in <= in_cntr[6:0] == 7'h7d;
......@@ -192,18 +157,25 @@ module mclt_bayer_fold#(
);
// Matching window latency with pixel data latency
wire [3:0] addr_dly = ADDR_DLY;
dly_var #(
.WIDTH(11),
.DLY_WIDTH(4)
) dly_pixel_addr_i (
.clk (clk), // input
.rst (rst), // input
// .dly (4'h2), // input[3:0] Delay for external memory latency = 2, reduce for higher
.dly (addr_dly), // input[3:0] Delay for external memory latency = 2, reduce for higher
.din ({pre_page, run_r[3], pix_a_r}), // input[0:0]
.dout ({pix_page, pix_re, pix_addr}) // output[0:0]
);
generate
if (ADDR_DLY !=0) begin
wire [3:0] addr_dly = ADDR_DLY - 1; // iverilog problem mitigation
dly_var #(
.WIDTH(11),
.DLY_WIDTH(4)
) dly_pixel_addr_i (
.clk (clk), // input
.rst (rst), // input
.dly (addr_dly), // input[3:0] Delay for external memory latency = 2, reduce for higher
.din ({pre_page, run_r[3], pix_a_r}), // input[0:0]
.dout ({pix_page, pix_re, pix_addr}) // output[0:0]
);
end else begin
assign pix_page = pre_page;
assign pix_re = run_r[3];
assign pix_addr = pix_a_r;
end
endgenerate
// Latency = 6
mclt_wnd_mul #(
......@@ -238,13 +210,10 @@ module mclt_bayer_fold#(
) dly_var_first_i (
.clk (clk), // input
.rst (rst), // input
// .dly (4'h9), // input[3:0]
.dly (4'h8), // input[3:0]
.din (run_r[0] && (in_cntr[0] == 0)), // input[0:0]
.dout (var_first_d) // output[0:0]
);
//
endmodule
dsp/mclt_test_03.tf
View file @ 1db76b02
......@@ -508,7 +508,9 @@ module mclt_test_03 ();
);
localparam PIX_ADDR_WIDTH = 9;
localparam ADDR_DLY = 2;
// localparam ADDR_DLY = 2;
localparam EXT_PIX_LATENCY = 2; // external pixel buffer a->d latency (may increase to 4 for gamma)
reg [1:0] TILE_SIZE = 3; // 22;
reg INV_CHECKER = 0;
reg [7:0] TOP_LEFT = 69; // center
......@@ -540,6 +542,7 @@ module mclt_test_03 ();
mclt16x16_bayer #(
.SHIFT_WIDTH (SHIFT_WIDTH),
.PIX_ADDR_WIDTH (PIX_ADDR_WIDTH),
.EXT_PIX_LATENCY (EXT_PIX_LATENCY), // 2), // external pixel buffer a->d latency (may increase to 4 for gamma)
.COORD_WIDTH (COORD_WIDTH),
.PIXEL_WIDTH (PIXEL_WIDTH),
.WND_WIDTH (WND_WIDTH),
......@@ -552,7 +555,7 @@ module mclt_test_03 ();
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
.DEAD_CYCLES (DEAD_CYCLES)
) mclt_bayer_fold_i (
) mclt16x16_bayer_i (
.clk (CLK), // input
.rst (RST), // input
.start (start), // input
......@@ -565,7 +568,16 @@ module mclt_test_03 ();
.pix_addr (PIX_ADDR9), // output[8:0]
.pix_re (PIX_RE), // output
.pix_page (PIX_PAGE), // output
.pix_d (PIX_D) // input[15:0]
.pix_d (PIX_D), // input[15:0]
.pre_busy (), // output
.pre_last_in (), // output
.pre_first_out (), // output
.pre_last_out (), // output
.out_addr (), // output[7:0]
.dv (), // output
.dout0 (), // output[24:0] signed
.dout1 () // output[24:0] signed
);
......
mclt_test_03.sav
View file @ 1db76b02
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sun Dec 24 18:15:09 2017
[*] Tue Dec 26 08:13:54 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_03-20171224110948170.fst"
[dumpfile_mtime] "Sun Dec 24 18:09:53 2017"
[dumpfile_size] 1509130
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_03-20171224112306105.fst"
[dumpfile_mtime] "Sun Dec 24 18:23:11 2017"
[dumpfile_size] 1510126
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_03.sav"
[timestart] 1522000
[size] 1814 1171
[timestart] 0
[size] 1824 1171
[pos] 1920 0
*-19.476400 3647300 355000 2885000 325000 7455000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-21.424982 10430000 355000 2885000 325000 7455000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_03.
[treeopen] mclt_test_03.mclt16x16_bayer_i.
[treeopen] mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.
[treeopen] mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.
[treeopen] mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.
[treeopen] mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.
[treeopen] mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.
[treeopen] mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.
[treeopen] mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.
[treeopen] mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.
[treeopen] mclt_test_03.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i.
[treeopen] mclt_test_03.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i.
[treeopen] mclt_test_03.mclt16x16_i.mclt_wnd_i.
......@@ -19,15 +28,6 @@
[treeopen] mclt_test_03.mclt16x16_i.phase_rotator_i.
[treeopen] mclt_test_03.mclt16x16_i.phase_rotator_i.dsp_2_i.
[treeopen] mclt_test_03.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.
[treeopen] mclt_test_03.mclt_bayer_fold_i.
[treeopen] mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.
[treeopen] mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.
[treeopen] mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.
[treeopen] mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.
[treeopen] mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.
[treeopen] mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.
[treeopen] mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.
[treeopen] mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.
[sst_width] 280
[signals_width] 319
[sst_expanded] 1
......@@ -1267,135 +1267,140 @@ mclt_test_03.mclt16x16_i.dtt_start_out
-mclt_bayer
-top
@28
mclt_test_03.mclt_bayer_fold_i.clk
mclt_test_03.mclt_bayer_fold_i.start
mclt_test_03.mclt_bayer_fold_i.pre_last_in
mclt_test_03.mclt_bayer_fold_i.pre_last_in_w
mclt_test_03.mclt_bayer_fold_i.pre_busy
mclt_test_03.mclt_bayer_fold_i.pre_first_out
mclt_test_03.mclt_bayer_fold_i.dv
mclt_test_03.mclt16x16_bayer_i.clk
mclt_test_03.mclt16x16_bayer_i.start
mclt_test_03.mclt16x16_bayer_i.pre_last_in
mclt_test_03.mclt16x16_bayer_i.pre_last_in_w
mclt_test_03.mclt16x16_bayer_i.pre_busy
mclt_test_03.mclt16x16_bayer_i.pre_first_out
mclt_test_03.mclt16x16_bayer_i.dv
@22
mclt_test_03.mclt_bayer_fold_i.dout0[24:0]
mclt_test_03.mclt_bayer_fold_i.dout1[24:0]
mclt_test_03.mclt16x16_bayer_i.dout0[24:0]
mclt_test_03.mclt16x16_bayer_i.dout1[24:0]
[color] 7
mclt_test_03.mclt_bayer_fold_i.dbg_dout0[24:0]
mclt_test_03.mclt16x16_bayer_i.dbg_dout0[24:0]
[color] 7
mclt_test_03.mclt_bayer_fold_i.dbg_dout1[24:0]
@8421
mclt_test_03.mclt16x16_bayer_i.dbg_dout1[24:0]
@8420
[color] 7
mclt_test_03.mclt_bayer_fold_i.dbg_dout0[24:0]
mclt_test_03.mclt16x16_bayer_i.dbg_dout0[24:0]
[color] 7
mclt_test_03.mclt_bayer_fold_i.dbg_dout1[24:0]
mclt_test_03.mclt16x16_bayer_i.dbg_dout1[24:0]
@22
mclt_test_03.mclt_bayer_fold_i.dtt_rd_data0[24:0]
mclt_test_03.mclt_bayer_fold_i.dtt_rd_data1[24:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_data0[24:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_data1[24:0]
[color] 2
mclt_test_03.mclt_bayer_fold_i.dbg_dtt_rd_data0[24:0]
mclt_test_03.mclt16x16_bayer_i.dbg_dtt_rd_data0[24:0]
[color] 2
mclt_test_03.mclt_bayer_fold_i.dbg_dtt_rd_data1[24:0]
mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
mclt_test_03.mclt_bayer_fold_i.dtt_r_data[24:0]
mclt_test_03.mclt16x16_bayer_i.dbg_dtt_rd_data1[24:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_r_data[24:0]
[color] 3
mclt_test_03.mclt_bayer_fold_i.dbg_dtt_r_data[24:0]
mclt_test_03.mclt_bayer_fold_i.dtt_out_wd[24:0]
mclt_test_03.mclt16x16_bayer_i.dbg_dtt_r_data[24:0]
mclt_test_03.mclt16x16_bayer_i.dtt_out_wd[24:0]
[color] 3
mclt_test_03.mclt_bayer_fold_i.dbg_dtt_out_wd[24:0]
mclt_test_03.mclt16x16_bayer_i.dbg_dtt_out_wd[24:0]
@c00200
-fold
@28
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.start
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.start
@22
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows[1:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows[1:0]
@28
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows_r0[1:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.pre_last_in
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows_r0[1:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.pre_last_in
@22
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.wnd_a_w[7:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
@1401200
-fold
@1000200
-top
@22
mclt_test_03.mclt16x16_bayer_i.pix_addr[8:0]
@28
mclt_test_03.mclt16x16_bayer_i.pix_page
mclt_test_03.mclt16x16_bayer_i.pix_re
@200
-
@800200
-rotator0
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.start
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.start
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.start_d[5:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.fd_din[24:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.rom_a[9:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.cos_sin_w[17:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.fd_out[24:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.shift_h[6:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.shift_v[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.start_d[5:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.fd_din[24:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.rom_a[9:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.cos_sin_w[17:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.fd_out[24:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.shift_h[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.shift_v[6:0]
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.inv_checker
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.inv_checker
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.shift_hr[6:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.shift_v0[6:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.shift_vr[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.shift_hr[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.shift_v0[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.shift_vr[6:0]
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.inv_checker_r
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.inv_checker_r2
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.inv_checker_r
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.inv_checker_r2
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.shift_hv[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.shift_hv[6:0]
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.hv_sin
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.hv_sin
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.sign_cs[4:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]
@28
(12)mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.ph[16:0]
(1)mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.start_d[5:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.negm_1
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.negm_2
(12)mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(1)mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.start_d[5:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.negm_1
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.negm_2
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.cntr_h[7:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.cntr_v[7:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.cntr_h[7:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.cntr_v[7:0]
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.pre_dv
mclt_test_03.mclt_bayer_fold_i.phase_rotator0_i.pre_first_out
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.pre_dv
mclt_test_03.mclt16x16_bayer_i.phase_rotator0_i.pre_first_out
@1000200
-rotator0
@800200
-rotator1
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.start
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.start
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.start_d[5:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.fd_din[24:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.shift_h[6:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.shift_v[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.start_d[5:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.fd_din[24:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.shift_h[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.shift_v[6:0]
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.inv_checker
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.inv_checker
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.shift_hr[6:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.shift_v0[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.shift_hr[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.shift_v0[6:0]
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.inv_checker_r
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.inv_checker_r
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.shift_vr[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.shift_vr[6:0]
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.inv_checker_r2
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.inv_checker_r2
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.shift_hv[6:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.shift_hv[6:0]
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.hv_sin
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.hv_sin
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.sign_cs[4:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.sign_cs[4:0]
@28
(12)mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.ph[16:0]
(1)mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.start_d[5:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.negm_1
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.negm_2
(12)mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.ph[16:0]
(1)mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.start_d[5:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.negm_1
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.negm_2
@22
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.cntr_h[7:0]
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.cntr_v[7:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.cntr_h[7:0]
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.cntr_v[7:0]
@28
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.pre_dv
mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.pre_first_out
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.pre_dv
mclt_test_03.mclt16x16_bayer_i.phase_rotator1_i.pre_first_out
@200
-
@1000200
......@@ -1403,312 +1408,329 @@ mclt_test_03.mclt_bayer_fold_i.phase_rotator1_i.pre_first_out
@c00200
-mclt_bayer_fold
@28
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.rst
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.tile_size_r[1:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.start
@22
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.top_left_r[7:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.x_shft_r[6:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.y_shft_r[6:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.fold_rom_out[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.wnd_a_w[7:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_a_w[8:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_a_r[8:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.sgn_w[1:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.signs[1:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_addr[8:0]
@28
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_re
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_page
@22
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.window[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
@28
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.en_a
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.regen_a
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.rst
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.tile_size_r[1:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.start
@22
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.top_left_r[7:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.x_shft_r[6:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.y_shft_r[6:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_w[8:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_r[8:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.sgn_w[1:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.signs[1:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_addr[8:0]
@28
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_re
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_page
@22
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.window[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
@28
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.en_a
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.regen_a
@c00200
-mclt_wnd_mul
@22
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.x_in[3:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.y_in[3:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.x_shft[6:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.y_shft[6:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out[17:0]
@28
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.zero_in
(1)mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
(0)mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
@22
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.x_full[9:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.y_full[9:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x_r[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y_r[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_full[35:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_w[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_a[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_b[17:0]
@28
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_a
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_b
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_a
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_b
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_a
mclt_test_03.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_b
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.x_in[3:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.y_in[3:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.x_shft[6:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.y_shft[6:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out[17:0]
@28
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.zero_in
(1)mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
(0)mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
@22
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.x_full[9:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.y_full[9:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x_r[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y_r[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_full[35:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_w[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_a[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_b[17:0]
@28
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_a
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_b
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_a
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_b
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_a
mclt_test_03.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_b
@1401200
-mclt_wnd_mul
-mclt_bayer_fold
@22
mclt_test_03.mclt_bayer_fold_i.pix_d[15:0]
mclt_test_03.mclt_bayer_fold_i.window_w[17:0]
mclt_test_03.mclt_bayer_fold_i.data_dtt_in[24:0]
mclt_test_03.mclt16x16_bayer_i.pix_d[15:0]
mclt_test_03.mclt16x16_bayer_i.window_w[17:0]
mclt_test_03.mclt16x16_bayer_i.data_dtt_in[24:0]
@28
mclt_test_03.mclt_bayer_fold_i.dtt_we
mclt_test_03.mclt16x16_bayer_i.dtt_we
@22
mclt_test_03.mclt_bayer_fold_i.dtt_in_cntr[6:0]
mclt_test_03.mclt16x16_bayer_i.dtt_in_cntr[6:0]
@28
mclt_test_03.mclt_bayer_fold_i.dtt_in_page
mclt_test_03.mclt_bayer_fold_i.start_dtt
mclt_test_03.mclt16x16_bayer_i.dtt_in_page
mclt_test_03.mclt16x16_bayer_i.start_dtt
@c00200
-mclt_baeyer_fold_accum
@28
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pre_phase
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pre_phase
@c00022
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
@28
(0)mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(1)mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(2)mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(3)mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(4)mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(5)mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(6)mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
@28
(0)mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(1)mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(2)mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(3)mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(4)mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(5)mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(6)mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
@1401200
-group_end
@22
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_d[15:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.window[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pix_d[15:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.window[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
@28
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.var_pre_first
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.var_first
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.var_last
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_pre_first
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_first
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_last
@22
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dtt_in[24:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in[24:0]
@28
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dtt_in_dv
(0)mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in_dv
(0)mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
@200
-
@22
mclt_test_03.mclt_bayer_fold_i.signs[1:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
mclt_test_03.mclt16x16_bayer_i.signs[1:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
@28
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.accum1
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.neg_m1
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum1
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m1
@22
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pout1[47:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout1[47:0]
@28
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.accum2
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.neg_m2
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum2
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m2
@22
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pout2[47:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dtt_in_dsp[24:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout2[47:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in_dsp[24:0]
@800200
-dsp1
@28
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.cead
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.cead
@22
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qp_o_reg1[47:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qp_o_reg1[47:0]
@1000200
-dsp1
@800200
-dsp2
@28
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.cead
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.cead
@22
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_03.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qp_o_reg1[47:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_03.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qp_o_reg1[47:0]
@200
-
@1000200
-dsp2
@1401200
-mclt_baeyer_fold_accum
@c00200
@800200
-membuf
@29
mclt_test_03.mclt16x16_bayer_i.dtt_start_first_fill
@22
mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wpage[1:0]
@800022
mclt_test_03.mclt16x16_bayer_i.dtt_start_out[1:0]
@28
(0)mclt_test_03.mclt16x16_bayer_i.dtt_start_out[1:0]
(1)mclt_test_03.mclt16x16_bayer_i.dtt_start_out[1:0]
@1001202
-group_end
@22
mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@8022
mclt_test_03.mclt_bayer_fold_i.dbg_diff_wara_dtt_in[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@20000
-
@8022
mclt_test_03.mclt16x16_bayer_i.dbg_diff_wara_dtt_in[8:0]
@20000
-
-
-
@8022
mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_in_i.raddr[8:0]
mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_in_i.raddr[8:0]
@20000
-
@8022
mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_in_i.waddr[8:0]
mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_in_i.waddr[8:0]
@20000
-
-
@200
-
@28
mclt_test_03.mclt_bayer_fold_i.dtt_out_we
mclt_test_03.mclt16x16_bayer_i.dtt_out_we
@8022
mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@20000
-
-
@8022
mclt_test_03.mclt_bayer_fold_i.dbg_last_dtt_out_ram_wa[8:0]
mclt_test_03.mclt16x16_bayer_i.dbg_last_dtt_out_ram_wa[8:0]
@20000
-
-
-
@8022
mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@20000
-
-
@8022
mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
mclt_test_03.mclt_bayer_fold_i.dbg_diff_wara_dtt_out0[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
mclt_test_03.mclt16x16_bayer_i.dbg_diff_wara_dtt_out0[8:0]
@20000
-
-
@8022
mclt_test_03.mclt_bayer_fold_i.dbg_diff_wara_dtt_out1[8:0]
mclt_test_03.mclt16x16_bayer_i.dbg_diff_wara_dtt_out1[8:0]
@20000
-
-
@1401200
@1000200
-membuf
@22
mclt_test_03.mclt_bayer_fold_i.dtt_r_ra[8:0]
mclt_test_03.mclt_bayer_fold_i.dtt_r_data[24:0]
mclt_test_03.mclt16x16_bayer_i.dtt_r_ra[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_r_data[24:0]
@8420
mclt_test_03.mclt_bayer_fold_i.dtt_r_data[24:0]
mclt_test_03.mclt16x16_bayer_i.dtt_r_data[24:0]
@28
mclt_test_03.mclt_bayer_fold_i.dtt_start
mclt_test_03.mclt_bayer_fold_i.dtt_start_fill
mclt_test_03.mclt16x16_bayer_i.dtt_start
mclt_test_03.mclt16x16_bayer_i.dtt_start_fill
@22
mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_cntr[4:0]
mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_cntr[4:0]
@28
mclt_test_03.mclt_bayer_fold_i.dtt_start_first_fill
mclt_test_03.mclt16x16_bayer_i.dtt_start_first_fill
@22
mclt_test_03.mclt_bayer_fold_i.dtt_out_wd[24:0]
mclt_test_03.mclt16x16_bayer_i.dtt_out_wd[24:0]
@28
mclt_test_03.mclt_bayer_fold_i.dtt_out_we
mclt_test_03.mclt16x16_bayer_i.dtt_out_we
@c00022
mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
@28
(0)mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(1)mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(2)mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(3)mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(4)mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(5)mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(6)mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(7)mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(8)mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@28
(0)mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(1)mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(2)mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(3)mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(4)mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(5)mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(6)mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(7)mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(8)mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@1401200
-group_end
@22
mclt_test_03.mclt_bayer_fold_i.dtt_dly_cntr[7:0]
mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
mclt_test_03.mclt_bayer_fold_i.dtt_out_ram_wah[4:0]
mclt_test_03.mclt_bayer_fold_i.dtt_out_wa16[3:0]
mclt_test_03.mclt16x16_bayer_i.dtt_dly_cntr[7:0]
mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_out_ram_wah[4:0]
mclt_test_03.mclt16x16_bayer_i.dtt_out_wa16[3:0]
@c00022
mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
@28
(0)mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(1)mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(2)mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(3)mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(4)mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(5)mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(6)mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(7)mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(8)mclt_test_03.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@28
(0)mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(1)mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(2)mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(3)mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(4)mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(5)mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(6)mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(7)mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(8)mclt_test_03.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@1401200
-group_end
@28
mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.we
mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.we
@c00022
mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
@28
(0)mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(1)mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(2)mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(3)mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(4)mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(5)mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(6)mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(7)mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(8)mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
@28
(0)mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(1)mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(2)mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(3)mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(4)mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(5)mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(6)mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(7)mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(8)mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
@1401200
-group_end
@28
mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.ren
mclt_test_03.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.regen
mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.ren
mclt_test_03.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.regen
@c00022
mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
@28
(0)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(1)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(2)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(3)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(4)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(5)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(6)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(7)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(8)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
@28
(0)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(1)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(2)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(3)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(4)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(5)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(6)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(7)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(8)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
@1401200
-group_end
@22
mclt_test_03.mclt_bayer_fold_i.x_shft[6:0]
mclt_test_03.mclt_bayer_fold_i.x_shft_r[6:0]
mclt_test_03.mclt_bayer_fold_i.x_shft_r2[6:0]
mclt_test_03.mclt_bayer_fold_i.x_shft_r3[6:0]
mclt_test_03.mclt_bayer_fold_i.x_shft_r4[6:0]
mclt_test_03.mclt_bayer_fold_i.y_shft[6:0]
mclt_test_03.mclt_bayer_fold_i.y_shft_r2[6:0]
mclt_test_03.mclt_bayer_fold_i.y_shft_r3[6:0]
mclt_test_03.mclt_bayer_fold_i.y_shft_r4[6:0]
@28
mclt_test_03.mclt_bayer_fold_i.inv_checker
mclt_test_03.mclt_bayer_fold_i.inv_checker_r
mclt_test_03.mclt_bayer_fold_i.inv_checker_r2
mclt_test_03.mclt_bayer_fold_i.inv_checker_r3
mclt_test_03.mclt_bayer_fold_i.inv_checker_r4
mclt_test_03.mclt16x16_bayer_i.x_shft[6:0]
mclt_test_03.mclt16x16_bayer_i.x_shft_r[6:0]
mclt_test_03.mclt16x16_bayer_i.x_shft_r2[6:0]
mclt_test_03.mclt16x16_bayer_i.x_shft_r3[6:0]
mclt_test_03.mclt16x16_bayer_i.x_shft_r4[6:0]
mclt_test_03.mclt16x16_bayer_i.y_shft[6:0]
mclt_test_03.mclt16x16_bayer_i.y_shft_r2[6:0]
mclt_test_03.mclt16x16_bayer_i.y_shft_r3[6:0]
mclt_test_03.mclt16x16_bayer_i.y_shft_r4[6:0]
@28
mclt_test_03.mclt16x16_bayer_i.inv_checker
mclt_test_03.mclt16x16_bayer_i.inv_checker_r
mclt_test_03.mclt16x16_bayer_i.inv_checker_r2
mclt_test_03.mclt16x16_bayer_i.inv_checker_r3
mclt_test_03.mclt16x16_bayer_i.inv_checker_r4
@c00022
mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
@28
(0)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(1)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(2)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(3)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(4)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(5)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(6)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(7)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(8)mclt_test_03.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@28
(0)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(1)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(2)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(3)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(4)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(5)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(6)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(7)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(8)mclt_test_03.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@1401200
-group_end
@1000200
......
system_defines.vh
View file @ 1db76b02
......@@ -43,6 +43,9 @@
`define DEBUG_HISTOGRAMS
// TODO: Later compare instantiate/infer
`define INSTANTIATE_DSP48E1 // not yet tesetd/debugged otherwise
`define DSP_ACCUM_FOLD 1 // for MCLT
// https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI4-Bursts-4KB-Address-Boundary-Limitation/td-p/216413
// Interconnect does not have 4K limit, and compressed data can only go to interconnect (memory), so it is OK to violate AXI specs here
`define AXI_4K_LIMIT_DISABLE // Current x393 code (only simulation modules) does not have it implemented, defining it causes mismatch synth/sim
......
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