added paremeters to cocotb tool

.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs

+FPGA_project_0_SimulationTopFile=x393_testbench03.tf
+FPGA_project_1_SimulationTopModule=x393_testbench03
+FPGA_project_2_DUTTopFile=cocotb/x393_dut.v
+FPGA_project_2_ImplementationTopFile=x393.v
+FPGA_project_3_DUTTopModule=x393_dut
+FPGA_project_4_part=xc7z030fbg484-1
+FPGA_project_5_part=xc7z030fbg484-1
+com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs

+ISExst_170_constraints=ddrc_test01.xcf
+ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->
+com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs

+VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
+VivadoBitstream_105_force=true
+VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
+VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
+VivadoBitstream_124_force=true
+VivadoBitstream_124_rawfile=x393_hispi
+com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOpt.prefs

+VivadoOpt_123_SkipSnapshotOpt=true
+VivadoOpt_124_SkipSnapshotOpt=true
+com.elphel.store.context.VivadoOpt=VivadoOpt_123_SkipSnapshotOpt<-@\#\#@->VivadoOpt_124_SkipSnapshotOpt<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOptPhys.prefs

+VivadoOptPhys_123_SkipSnapshotOptPhys=true
+VivadoOptPhys_124_SkipSnapshotOptPhys=true
+com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_123_SkipSnapshotOptPhys<-@\#\#@->VivadoOptPhys_124_SkipSnapshotOptPhys<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOptPower.prefs

+VivadoOptPower_124_SkipSnapshotOptPower=true
+VivadoOptPower_125_SkipSnapshotOptPower=true
+com.elphel.store.context.VivadoOptPower=VivadoOptPower_124_SkipSnapshotOptPower<-@\#\#@->VivadoOptPower_125_SkipSnapshotOptPower<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoPlace.prefs

+VivadoPlace_111_verbose_place=true
+VivadoPlace_123_SkipSnapshotPlace=true
+VivadoPlace_124_SkipSnapshotPlace=true
+com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->VivadoPlace_123_SkipSnapshotPlace<-@\#\#@->VivadoPlace_124_SkipSnapshotPlace<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoRoute.prefs

+VivadoRoute_122_SkipSnapshotRoute=true
+VivadoRoute_123_SkipSnapshotRoute=true
+VivadoRoute_125_directive_route=MoreGlobalIterations
+com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->VivadoRoute_125_directive_route<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoSynthesis.prefs

+VivadoSynthesis_101_MaxMsg=10000
+VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
+VivadoSynthesis_115_flatten_hierarchy=none
+VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
+VivadoSynthesis_121_MaxMsg=5000
+VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->
+VivadoSynthesis_122_SkipSnapshotSynth=true
+VivadoSynthesis_123_ResetProject=true
+VivadoSynthesis_123_SkipSnapshotSynth=true
+VivadoSynthesis_124_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@->
+VivadoSynthesis_127_verbose=true
+VivadoSynthesis_128_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@->
+VivadoSynthesis_81_parser_mode=1
+VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
+VivadoSynthesis_95_ShowInfo=true
+com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_MaxMsg<-@\#\#@->VivadoSynthesis_128_PreTCL<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs

+VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
+VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary=true
+com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs

+VivadoTimingReportImplemented_121_DisableVivadoTiming=true
+VivadoTimingReportImplemented_122_DisableVivadoTiming=true
+com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->VivadoTimingReportImplemented_121_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_122_DisableVivadoTiming<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs

+VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
+VivadoTimingReportSynthesis_121_DisableVivadoTiming=true
+com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_121_DisableVivadoTiming<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.cocotb.prefs

+cocotb_107_CocotbDutTopFile=cocotb/x393_dut.v
+cocotb_109_CocotbRANDOM_SEED=123
+cocotb_111_CocotbMODULE=x393coco_02<-@\#\#@->
+cocotb_112_CocotbMODULE=x393coco_02<-@\#\#@->
+cocotb_112_CocotbTESTCASE=run_test<-@\#\#@->
+cocotb_113_CocotbTESTCASE=run_test<-@\#\#@->
+cocotb_116_GTKWaveSavFile=x393_cocotb_02.sav
+cocotb_117_GTKWaveSavFile=x393_cocotb_02.sav
+cocotb_118_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
+cocotb_119_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
+cocotb_122_CocotbExtraFiles=glbl.v<-@\#\#@->
+cocotb_123_CocotbExtraFiles=glbl.v<-@\#\#@->
+com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->cocotb_109_CocotbRANDOM_SEED<-@\#\#@->cocotb_112_CocotbMODULE<-@\#\#@->cocotb_113_CocotbTESTCASE<-@\#\#@->cocotb_117_GTKWaveSavFile<-@\#\#@->cocotb_123_CocotbExtraFiles<-@\#\#@->cocotb_119_CocotbIncludeDir<-@\#\#@->
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs

+com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_106_TopModulesOther<-@\#\#@->iverilog_108_ExtraFiles<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@->iverilog_109_IncludeDir<-@\#\#@->
+eclipse.preferences.version=1
+iverilog_100_TopModulesOther=glbl<-@\#\#@->
+iverilog_101_TopModulesOther=glbl<-@\#\#@->
+iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
+iverilog_102_TopModulesOther=glbl<-@\#\#@->
+iverilog_103_ExtraFiles=glbl.v<-@\#\#@->
+iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
+iverilog_103_TopModulesOther=glbl<-@\#\#@->
+iverilog_104_ExtraFiles=glbl.v<-@\#\#@->
+iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
+iverilog_105_ExtraFiles=glbl.v<-@\#\#@->
+iverilog_105_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->
+iverilog_106_IncludeDir=${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/x393/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata/includes<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
+iverilog_106_TopModulesOther=glbl<-@\#\#@->
+iverilog_108_ExtraFiles=glbl.v<-@\#\#@->
+iverilog_109_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
+iverilog_109_ShowNoProblem=true
+iverilog_110_ShowNoProblem=true
+iverilog_110_ShowWarnings=false
+iverilog_111_ShowNoProblem=true
+iverilog_113_SaveLogsPreprocessor=false
+iverilog_113_SaveLogsSimulator=true
+iverilog_114_SaveLogsSimulator=true
+iverilog_115_SaveLogsSimulator=true
+iverilog_120_GTKWaveSavFile=x393_testbench04.sav
+iverilog_121_GrepFindErrWarn=error|warning|sorry
+iverilog_123_GTKWaveSavFile=x393_testbench04.sav
+iverilog_77_Param_Exe=/usr/local/bin/iverilog
+iverilog_78_VVP_Exe=/usr/local/bin/vvp
+iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
+iverilog_81_TopModulesOther=glbl<-@\#\#@->
+iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
+iverilog_84_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
+iverilog_88_ShowNoProblem=true
+iverilog_89_ShowNoProblem=true
+iverilog_98_GTKWaveSavFile=393_testbench01.sav
+iverilog_99_GrepFindErrWarn=error|warning|sorry

.eclipse_project_setup/.settings/com.elphel.vdt.prefs

+com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
+com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
+eclipse.preferences.version=1

.eclipse_project_setup/.settings/org.eclipse.core.resources.prefs

+eclipse.preferences.version=1
+encoding//helpers/convert_data_to_params.py=utf-8
+encoding//helpers/convert_pass_init_params.py=utf-8
+encoding//helpers/convert_zigzag_rom.py=utf-8
+encoding//py393/test_mcntrl.py=utf-8
+encoding//py393/x393_i2c.py.test=utf-8
+encoding//py393/x393_init_usb_hub.py=utf-8

.settings/com.elphel.vdt.cocotb.prefs

 cocotb_107_CocotbDutTopFile=cocotb/x393_dut.v
+cocotb_109_CocotbRANDOM_SEED=123
 cocotb_111_CocotbMODULE=x393coco_02<-@\#\#@->
+cocotb_112_CocotbMODULE=x393coco_02<-@\#\#@->
 cocotb_112_CocotbTESTCASE=run_test<-@\#\#@->
+cocotb_113_CocotbTESTCASE=run_test<-@\#\#@->
 cocotb_116_GTKWaveSavFile=x393_cocotb_02.sav
+cocotb_117_GTKWaveSavFile=x393_cocotb_02.sav
 cocotb_118_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
+cocotb_119_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
 cocotb_122_CocotbExtraFiles=glbl.v<-@\#\#@->
-com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->
+cocotb_123_CocotbExtraFiles=glbl.v<-@\#\#@->
+com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->cocotb_109_CocotbRANDOM_SEED<-@\#\#@->cocotb_112_CocotbMODULE<-@\#\#@->cocotb_113_CocotbTESTCASE<-@\#\#@->cocotb_117_GTKWaveSavFile<-@\#\#@->cocotb_123_CocotbExtraFiles<-@\#\#@->cocotb_119_CocotbIncludeDir<-@\#\#@->
 eclipse.preferences.version=1

cocotb/x393coco_02.py

@@ -20,7 +20,7 @@ from __future__ import print_function
 @license:    GPLv3.0+
 @contact:    andrey@elphel.coml
 """
-
+import os
 import cocotb
 from cocotb.triggers import Timer
 from x393buses import MAXIGPMaster
@@ -31,73 +31,83 @@ from cocotb.result import ReturnValue, TestFailure, TestError, TestSuccess
 import logging
 
 class X393_cocotb_02(object):
-    def __init__(self, dut, debug=True):
+    def __init__(self, dut): # , debug=False):
+        """
+        print("os.getenv('SIM_ROOT'",os.getenv('SIM_ROOT'))
+        print("os.getenv('COCOTB_DEBUG'",os.getenv('COCOTB_DEBUG'))
+        print("os.getenv('RANDOM_SEED'",os.getenv('RANDOM_SEED'))
+        print("os.getenv('MODULE'",os.getenv('MODULE'))
+        print("os.getenv('TESTCASE'",os.getenv('TESTCASE'))
+        print("os.getenv('COCOTB_ANSI_OUTPUT'",os.getenv('COCOTB_ANSI_OUTPUT'))
+        """
+        debug = os.getenv('COCOTB_DEBUG') # None/1
+        
         self.dut = dut
         self.axiwr = MAXIGPMaster(entity=dut, name="dutm0", clock=dut.dutm0_aclk, rdlag=0, blag=0)
 #        self.clock = dut.dutm0_aclk
         
         level = logging.DEBUG if debug else logging.WARNING
         self.axiwr.log.setLevel(level)
-
+def convert_string(txt):
+    number=0
+    for c in txt:
+        number = (number << 8) + ord(c)
+    return number   
 @cocotb.coroutine
-def run_test(dut, data_in=None, config_coroutine=None, idle_inserter=None,
-             backpressure_inserter=None):
-#    self.log.info ("MAXIGPMaster._send_write_data(): released lock %s"%(W_CHN))
-
-#    self.log.info  ("run_test(): starting X393_cocotb_02(dut) init")
+def run_test(dut):
     tb = X393_cocotb_02(dut)
-#    self.log.info  ("run_test(): X393_cocotb_02(dut) done")
     yield Timer(10000)
-#    yield RisingEdge(dut.dutm0_aclk)
-#    yield ReadOnly()
-#    raise TestSuccess("All done for now")
-
 
     while dut.reset_out.value.get_binstr() != "1":
         yield Timer(10000)
 
     while dut.reset_out.value:
         yield Timer(10000)
-    yield tb.axiwr.axi_write(address = 0x1234,
-                     value = [0,1,2,3,4,5,6,7,8],
-                     byte_enable=None,
-                     address_latency=0,
-                     data_latency=0,
-                     id=0,
-                     dsize=2,
-                     burst=1)
-    dut._log.info("Almost there")
-    yield Timer(1000)
-    dut._log.info("Ok!")
-#    raise TestSuccess()
+#    dut.TEST_TITLE.buff = "WRITE"
+    dut.TEST_TITLE = convert_string("WRITE")    
+    val = yield tb.axiwr.axi_write(address =         0x1234,
+                                   value =           [8,7,6,5,4,3,2,1,0],
+                                   byte_enable =     None,
+                                   id =              0,
+                                   dsize =           2,
+                                   burst =           1,
+                                   address_latency = 0,
+                                   data_latency =    0)
+#    dut.TEST_TITLE.buff = "---"    
+    dut.TEST_TITLE = 0    
+    dut._log.info("axi_write returned => " +str(val))
+#    yield Timer(1000)
+    print("*******************************************")
+    yield Timer(11000)
+    dut.TEST_TITLE = convert_string("WRITE1")    
+    val = yield tb.axiwr.axi_write(address =         0x5678,
+                                   value =           [1,2,3,4],
+                                   byte_enable =     None,
+                                   id =              0,
+                                   dsize =           2,
+                                   burst =           1,
+                                   address_latency = 0,
+                                   data_latency =    0)
+#    dut.TEST_TITLE.buff = "---"    
+    dut.TEST_TITLE = 0    
+    dut._log.info("axi_write returned => " +str(val))
+#    yield Timer(1000)
+    print("*******************************************")
+    yield Timer(10000)
+#    dval = yield  tb.axiwr.axi_read(0x1234, 0, 4, 2, 0, 0 )
+#    dut.TEST_TITLE.buff = "READ"    
+    dut.TEST_TITLE <= convert_string("READ")    
+    dval = yield  tb.axiwr.axi_read(address =         0x1234,
+                                    id =              0,
+                                    dlen =            4,
+                                    dsize =           2,
+                                    address_latency = 0,
+                                    data_latency =    0 )
 
-#    raise TestSuccess("All done for now")
+    dut._log.info("axi_read returned => " +str(dval))
+#    dut.TEST_TITLE.buff = "---"
+    dut.TEST_TITLE <= 0
+    yield Timer(100000)
     print("*******************************************")
     cocotb.regression.tear_down()
 
-#print("Main done")    
-
-"""
-MODULE=test_endian_swapper
-
-class EndianSwapperTB(object):
-
-def convert_string(txt):
-    number=0
-    for c in txt:
-        number = (number << 8) + ord(c)
-    return number     
-    
-@cocotb.test()
-def hello_test(dut):
-    yield Timer(100)
-    for i in range (1000):
-        if i == 200:
-            dut.TEST_TITLE=convert_string("passed 200")
-        elif i == 400:
-            dut.TEST_TITLE=convert_string("passed 400")
-        dut.maxigp0arvalid=0
-        yield Timer(10000)
-        dut.maxigp0arvalid=1
-        yield Timer(10000)
-"""
\ No newline at end of file