Skip to content

X
x393
Commit 1cd46f93 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

added paremeters to cocotb tool

parent 1495fe18
Show whitespace changes
Inline Side-by-side
Showing with 345 additions and 85 deletions
.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644
View file @ 1cd46f93
FPGA_project_0_SimulationTopFile=x393_testbench03.tf
FPGA_project_1_SimulationTopModule=x393_testbench03
FPGA_project_2_DUTTopFile=cocotb/x393_dut.v
FPGA_project_2_ImplementationTopFile=x393.v
FPGA_project_3_DUTTopModule=x393_dut
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs 0 → 100644
View file @ 1cd46f93
ISExst_170_constraints=ddrc_test01.xcf
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs 0 → 100644
View file @ 1cd46f93
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_124_rawfile=x393_hispi
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOpt.prefs 0 → 100644
View file @ 1cd46f93
VivadoOpt_123_SkipSnapshotOpt=true
VivadoOpt_124_SkipSnapshotOpt=true
com.elphel.store.context.VivadoOpt=VivadoOpt_123_SkipSnapshotOpt<-@\#\#@->VivadoOpt_124_SkipSnapshotOpt<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOptPhys.prefs 0 → 100644
View file @ 1cd46f93
VivadoOptPhys_123_SkipSnapshotOptPhys=true
VivadoOptPhys_124_SkipSnapshotOptPhys=true
com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_123_SkipSnapshotOptPhys<-@\#\#@->VivadoOptPhys_124_SkipSnapshotOptPhys<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOptPower.prefs 0 → 100644
View file @ 1cd46f93
VivadoOptPower_124_SkipSnapshotOptPower=true
VivadoOptPower_125_SkipSnapshotOptPower=true
com.elphel.store.context.VivadoOptPower=VivadoOptPower_124_SkipSnapshotOptPower<-@\#\#@->VivadoOptPower_125_SkipSnapshotOptPower<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoPlace.prefs 0 → 100644
View file @ 1cd46f93
VivadoPlace_111_verbose_place=true
VivadoPlace_123_SkipSnapshotPlace=true
VivadoPlace_124_SkipSnapshotPlace=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->VivadoPlace_123_SkipSnapshotPlace<-@\#\#@->VivadoPlace_124_SkipSnapshotPlace<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoRoute.prefs 0 → 100644
View file @ 1cd46f93
VivadoRoute_122_SkipSnapshotRoute=true
VivadoRoute_123_SkipSnapshotRoute=true
VivadoRoute_125_directive_route=MoreGlobalIterations
com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->VivadoRoute_125_directive_route<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoSynthesis.prefs 0 → 100644
View file @ 1cd46f93
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_121_MaxMsg=5000
VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->
VivadoSynthesis_122_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true
VivadoSynthesis_123_SkipSnapshotSynth=true
VivadoSynthesis_124_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_128_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@->
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
VivadoSynthesis_95_ShowInfo=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_MaxMsg<-@\#\#@->VivadoSynthesis_128_PreTCL<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs 0 → 100644
View file @ 1cd46f93
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs 0 → 100644
View file @ 1cd46f93
VivadoTimingReportImplemented_121_DisableVivadoTiming=true
VivadoTimingReportImplemented_122_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->VivadoTimingReportImplemented_121_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_122_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs 0 → 100644
View file @ 1cd46f93
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
VivadoTimingReportSynthesis_121_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_121_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.cocotb.prefs 0 → 100644
View file @ 1cd46f93
cocotb_107_CocotbDutTopFile=cocotb/x393_dut.v
cocotb_109_CocotbRANDOM_SEED=123
cocotb_111_CocotbMODULE=x393coco_02<-@\#\#@->
cocotb_112_CocotbMODULE=x393coco_02<-@\#\#@->
cocotb_112_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_113_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_116_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_117_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_118_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_119_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_122_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_123_CocotbExtraFiles=glbl.v<-@\#\#@->
com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->cocotb_109_CocotbRANDOM_SEED<-@\#\#@->cocotb_112_CocotbMODULE<-@\#\#@->cocotb_113_CocotbTESTCASE<-@\#\#@->cocotb_117_GTKWaveSavFile<-@\#\#@->cocotb_123_CocotbExtraFiles<-@\#\#@->cocotb_119_CocotbIncludeDir<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs 0 → 100644
View file @ 1cd46f93
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_106_TopModulesOther<-@\#\#@->iverilog_108_ExtraFiles<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@->iverilog_109_IncludeDir<-@\#\#@->
eclipse.preferences.version=1
iverilog_100_TopModulesOther=glbl<-@\#\#@->
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=glbl.v<-@\#\#@->
iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_103_TopModulesOther=glbl<-@\#\#@->
iverilog_104_ExtraFiles=glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_105_ExtraFiles=glbl.v<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->
iverilog_106_IncludeDir=${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/x393/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata/includes<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_106_TopModulesOther=glbl<-@\#\#@->
iverilog_108_ExtraFiles=glbl.v<-@\#\#@->
iverilog_109_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_109_ShowNoProblem=true
iverilog_110_ShowNoProblem=true
iverilog_110_ShowWarnings=false
iverilog_111_ShowNoProblem=true
iverilog_113_SaveLogsPreprocessor=false
iverilog_113_SaveLogsSimulator=true
iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true
iverilog_120_GTKWaveSavFile=x393_testbench04.sav
iverilog_121_GrepFindErrWarn=error|warning|sorry
iverilog_123_GTKWaveSavFile=x393_testbench04.sav
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_84_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_98_GTKWaveSavFile=393_testbench01.sav
iverilog_99_GrepFindErrWarn=error|warning|sorry
.eclipse_project_setup/.settings/com.elphel.vdt.prefs 0 → 100644
View file @ 1cd46f93
com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
.eclipse_project_setup/.settings/org.eclipse.core.resources.prefs 0 → 100644
View file @ 1cd46f93
eclipse.preferences.version=1
encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8
encoding//py393/test_mcntrl.py=utf-8
encoding//py393/x393_i2c.py.test=utf-8
encoding//py393/x393_init_usb_hub.py=utf-8
.settings/com.elphel.vdt.cocotb.prefs
View file @ 1cd46f93
cocotb_107_CocotbDutTopFile=cocotb/x393_dut.v
cocotb_109_CocotbRANDOM_SEED=123
cocotb_111_CocotbMODULE=x393coco_02<-@\#\#@->
cocotb_112_CocotbMODULE=x393coco_02<-@\#\#@->
cocotb_112_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_113_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_116_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_117_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_118_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_119_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_122_CocotbExtraFiles=glbl.v<-@\#\#@->
com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->
cocotb_123_CocotbExtraFiles=glbl.v<-@\#\#@->
com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->cocotb_109_CocotbRANDOM_SEED<-@\#\#@->cocotb_112_CocotbMODULE<-@\#\#@->cocotb_113_CocotbTESTCASE<-@\#\#@->cocotb_117_GTKWaveSavFile<-@\#\#@->cocotb_123_CocotbExtraFiles<-@\#\#@->cocotb_119_CocotbIncludeDir<-@\#\#@->
eclipse.preferences.version=1
cocotb/x393buses.py
View file @ 1cd46f93
......@@ -170,7 +170,7 @@ class MAXIGPMaster(BusDriver):
def _send_write_address(self, address, delay, id, dlen, dsize, burst):
"""
Send write address with parameters
@param address binary byte address for burst start
@param address binary byte address for (first) burst start
@param delay Latency sending address in clock cycles
@param id transaction ID
@param dlen burst length (1..16)
......@@ -213,6 +213,53 @@ class MAXIGPMaster(BusDriver):
self.busy_channels[AW_CHN].release()
self.log.debug ("MAXIGPMaster._send_write_address(): released lock %s"%(AW_CHN))
@cocotb.coroutine
def _send_read_address(self, address, delay, id, dlen, dsize, burst):
"""
Send write address with parameters
@param address binary byte address for (first) burst start
@param delay Latency sending address in clock cycles
@param id transaction ID
@param dlen burst length (1..16)
@param dsize - data width - (1 << dsize) bytes (MAXIGP has only 2 bits while AXI specifies 3) 2 means 32 bits
@param burst burst type (0 - fixed, 1 - increment, 2 - wrap, 3 - reserved)
"""
# self.log.debug ("MAXIGPMaster._send_write_address(",address,", ",delay,", ",id,", ",dlen ,", ",dsize, ", ", burst)
yield self.busy_channels[AR_CHN].acquire()
self.log.debug ("MAXIGPMaster._send_write_address(): acquired lock")
for _ in range(delay):
yield RisingEdge(self.clock)
self.log.debug ("MAXIGPMaster._send_read_address(): delay over")
self.bus.arvalid <= 1
self.bus.arid <= id
self.bus.arsize <= dsize
self.bus.arburst <= burst
while dlen > 16:
self.bus.araddr <= address
address += 16*(1 << dsize)
dlen -= 16
self.bus.arlen <= 15
while True:
yield ReadOnly()
if self.bus.arready.value:
break
yield RisingEdge(self.clock)
yield RisingEdge(self.clock)
self.bus.araddr <= address
self.bus.arlen <= dlen -1
self.log.debug ("1.MAXIGPMaster._send_read_address(), address=0x%08x, dlen = 0x%x"%(address, dlen))
while True:
yield ReadOnly()
if self.bus.arready.value:
break
yield RisingEdge(self.clock)
yield RisingEdge(self.clock)
self.bus.arvalid <= 0
# FLoat all assigned bus signals but awvalid
self._float_signals((self.bus.araddr,self.bus.arid, self.bus.arlen, self.bus.arsize,self.bus.arburst))
self.busy_channels[AR_CHN].release()
self.log.debug ("MAXIGPMaster._send_read_address(): released lock %s"%(AW_CHN))
@cocotb.coroutine
def _send_write_data(self, data, wrstb, delay, id, dsize):
"""
......@@ -228,7 +275,7 @@ class MAXIGPMaster(BusDriver):
self.log.debug ("MAXIGPMaster._send_write_data(): acquired lock")
for cycle in range(delay):
yield RisingEdge(self.clock)
self.log.debug ("MAXIGPMaster._send_write_address(): delay over")
self.log.debug ("MAXIGPMaster._send_write_data(): delay over")
self.bus.wvalid <= 1
self.bus.wid <= id
for i,val_wstb in enumerate(zip(data,wrstb)):
......@@ -250,23 +297,68 @@ class MAXIGPMaster(BusDriver):
self._float_signals((self.bus.wdata,self.bus.wstb,self.bus.wlast))
self.busy_channels[W_CHN].release()
self.log.debug ("MAXIGPMaster._send_write_data(): released lock %s"%(W_CHN))
raise ReturnValue(dsize)
@cocotb.coroutine
def _get_read_data(self, address, id, dlen, dsize, delay):
"""
Send a data word or a list of data words (supports multi-burst)
@param address start address to read data from (just for logging)
@param id expected receive data ID
@param dlen number of words to read
@param dsize - data width - (1 << dsize) bytes (MAXIGP has only 2 bits while AXI specifies 3) 2 means 32 bits
@param delay latency in clock cycles
"""
self.log.debug ("MAXIGPMaster._get_read_data("+str(address)+", "+str(id)+", "+str(dlen)+", "+str(dsize)+", "+str(delay))
yield self.busy_channels[R_CHN].acquire()
self.log.debug ("MAXIGPMaster._get_read_data(): acquired lock")
for cycle in range(delay):
yield RisingEdge(self.clock)
self.log.debug ("MAXIGPMaster._get_read_data(): delay over")
self.bus.rready <= 1
data=[]
for i in range(dlen):
self.log.debug ("MAXIGPMaster._get_read_data(), i= %d"%(i))
while True:
yield ReadOnly()
if self.bus.rvalid.value:
data.append(self.bus.rdata.value.integer)
rid = int(self.bus.rid.value)
if rid != id:
self.log.error("Read data 0x%x ID mismatch - expected: 0x%x, got 0x%x"%(address+i,id, rid))
break
yield RisingEdge(self.clock)
yield RisingEdge(self.clock)
self.bus.rready <= 0
# FLoat all assigned bus signals but wvalid
# self._float_signals((self.bus.wdata,self.bus.wstb,self.bus.wlast))
self.busy_channels[R_CHN].release()
self.log.debug ("MAXIGPMaster._get_read_data(): released lock %s"%(R_CHN))
raise ReturnValue(data)
@cocotb.coroutine
def axi_write(self, address, value, byte_enable=None, address_latency=0,
data_latency=0,
id=0, dsize=2, burst=1):
def axi_write(self, address, value, byte_enable=None,
id=0, dsize=2, burst=1,address_latency=0,
data_latency=0):
self.log.debug("axi_write")
"""
Write a data burst.
@param address binary byte address for burst start
@param value - a value or a list of values (supports multi-burst, but no interrupts between bursts)
@param byte_enable - byte enable mask. Should be None (all enabled) or have the same number of items as data
@param address_latency latency sending address in clock cycles
@param data_latency latency sending data in clock cycles
@param id transaction ID
@param dsize - data width - (1 << dsize) bytes (MAXIGP has only 2 bits while AXI specifies 3) 2 means 32 bits
@param burst burst type (0 - fixed, 1 - increment, 2 - wrap, 3 - reserved)
@param address_latency latency sending address in clock cycles
@param data_latency latency sending data in clock cycles
"""
#Only wait if it is too late (<1/2 cycle)
if not int(self.clock):
yield RisingEdge(self.clock)
# self.log.debug ("1.MAXIGPMaster.write(",address,", ",value, ",", byte_enable,", ",address_latency,",",
# data_latency,", ",id,", ",dsize,", ", burst)
if not isinstance(value, (list,tuple)):
......@@ -297,34 +389,52 @@ class MAXIGPMaster(BusDriver):
delay= data_latency,
id = id,
dsize = dsize))
#(self, data, wrstb, delay, id, dsize)
if c_addr:
self.log.debug ("c_addr.join()")
yield c_addr.join()
if c_data:
self.log.debug ("c_data.join()")
yield c_data.join()
yield RisingEdge(self.clock)
self.log.debug ("All done, returning")
# yield RisingEdge(self.clock)
self.log.debug ("axi_write:All done")
raise ReturnValue(0)
# result = self.bus.bresp.value
# raise ReturnValue(0) #result)
@cocotb.coroutine
def axi_read(self, address, id = 0, dlen = 1, dsize = 2, burst = 1, address_latency = 0, data_latency= 0 ):
"""
# It will be to slow if to wait for response after each word sent, need to put a separate monitor on B-channel
# Wait for the response
while True:
yield ReadOnly()
if self.bus.BVALID.value and self.bus.BREADY.value:
result = self.bus.BRESP.value
break
Receive data form AXI port
@param address start address to read data from
@param id expected receive data ID
@param dlen number of words to read
@param dsize - data width - (1 << dsize) bytes (MAXIGP has only 2 bits while AXI specifies 3) 2 means 32 bits
@param burst burst type (0 - fixed, 1 - increment, 2 - wrap, 3 - reserved)
@param address_latency latency sending address in clock cycles
@param data_latency latency sending data in clock cycles
@return A list of BinaryValue objects
"""
#Only wait if it is too late (<1/2 cycle)
if not int(self.clock):
yield RisingEdge(self.clock)
yield RisingEdge(self.clock)
c_addr = cocotb.fork(self._send_read_address(address= address,
delay= address_latency,
id = id,
dlen = dlen,
dsize = dsize,
burst = burst))
if int(result):
raise AXIReadError("Write to address 0x%08x failed with BRESP: %d"
% (address, int(result)))
raise ReturnValue(result)
"""
c_data = cocotb.fork(self._get_read_data (address= address,
id = id,
dlen = dlen,
dsize = dsize,
delay = data_latency))
if c_addr:
self.log.debug ("c_addr.join()")
yield c_addr.join()
if c_data:
self.log.debug ("c_data.join()")
data_rv=yield c_data.join()
# yield RisingEdge(self.clock)
self.log.debug ("axi_read:All done, returning, data_rv="+str(data_rv))
raise ReturnValue(data_rv)
cocotb/x393coco_02.py
View file @ 1cd46f93
......@@ -20,7 +20,7 @@ from __future__ import print_function
@license: GPLv3.0+
@contact: andrey@elphel.coml
"""
import os
import cocotb
from cocotb.triggers import Timer
from x393buses import MAXIGPMaster
......@@ -31,73 +31,83 @@ from cocotb.result import ReturnValue, TestFailure, TestError, TestSuccess
import logging
class X393_cocotb_02(object):
def __init__(self, dut, debug=True):
def __init__(self, dut): # , debug=False):
"""
print("os.getenv('SIM_ROOT'",os.getenv('SIM_ROOT'))
print("os.getenv('COCOTB_DEBUG'",os.getenv('COCOTB_DEBUG'))
print("os.getenv('RANDOM_SEED'",os.getenv('RANDOM_SEED'))
print("os.getenv('MODULE'",os.getenv('MODULE'))
print("os.getenv('TESTCASE'",os.getenv('TESTCASE'))
print("os.getenv('COCOTB_ANSI_OUTPUT'",os.getenv('COCOTB_ANSI_OUTPUT'))
"""
debug = os.getenv('COCOTB_DEBUG') # None/1
self.dut = dut
self.axiwr = MAXIGPMaster(entity=dut, name="dutm0", clock=dut.dutm0_aclk, rdlag=0, blag=0)
# self.clock = dut.dutm0_aclk
level = logging.DEBUG if debug else logging.WARNING
self.axiwr.log.setLevel(level)
def convert_string(txt):
number=0
for c in txt:
number = (number << 8) + ord(c)
return number
@cocotb.coroutine
def run_test(dut, data_in=None, config_coroutine=None, idle_inserter=None,
backpressure_inserter=None):
# self.log.info ("MAXIGPMaster._send_write_data(): released lock %s"%(W_CHN))
# self.log.info ("run_test(): starting X393_cocotb_02(dut) init")
def run_test(dut):
tb = X393_cocotb_02(dut)
# self.log.info ("run_test(): X393_cocotb_02(dut) done")
yield Timer(10000)
# yield RisingEdge(dut.dutm0_aclk)
# yield ReadOnly()
# raise TestSuccess("All done for now")
while dut.reset_out.value.get_binstr() != "1":
yield Timer(10000)
while dut.reset_out.value:
yield Timer(10000)
yield tb.axiwr.axi_write(address = 0x1234,
value = [0,1,2,3,4,5,6,7,8],
byte_enable=None,
address_latency=0,
data_latency=0,
id=0,
dsize=2,
burst=1)
dut._log.info("Almost there")
yield Timer(1000)
dut._log.info("Ok!")
# raise TestSuccess()
# dut.TEST_TITLE.buff = "WRITE"
dut.TEST_TITLE = convert_string("WRITE")
val = yield tb.axiwr.axi_write(address = 0x1234,
value = [8,7,6,5,4,3,2,1,0],
byte_enable = None,
id = 0,
dsize = 2,
burst = 1,
address_latency = 0,
data_latency = 0)
# dut.TEST_TITLE.buff = "---"
dut.TEST_TITLE = 0
dut._log.info("axi_write returned => " +str(val))
# yield Timer(1000)
print("*******************************************")
yield Timer(11000)
dut.TEST_TITLE = convert_string("WRITE1")
val = yield tb.axiwr.axi_write(address = 0x5678,
value = [1,2,3,4],
byte_enable = None,
id = 0,
dsize = 2,
burst = 1,
address_latency = 0,
data_latency = 0)
# dut.TEST_TITLE.buff = "---"
dut.TEST_TITLE = 0
dut._log.info("axi_write returned => " +str(val))
# yield Timer(1000)
print("*******************************************")
yield Timer(10000)
# dval = yield tb.axiwr.axi_read(0x1234, 0, 4, 2, 0, 0 )
# dut.TEST_TITLE.buff = "READ"
dut.TEST_TITLE <= convert_string("READ")
dval = yield tb.axiwr.axi_read(address = 0x1234,
id = 0,
dlen = 4,
dsize = 2,
address_latency = 0,
data_latency = 0 )
# raise TestSuccess("All done for now")
dut._log.info("axi_read returned => " +str(dval))
# dut.TEST_TITLE.buff = "---"
dut.TEST_TITLE <= 0
yield Timer(100000)
print("*******************************************")
cocotb.regression.tear_down()
#print("Main done")
"""
MODULE=test_endian_swapper
class EndianSwapperTB(object):
def convert_string(txt):
number=0
for c in txt:
number = (number << 8) + ord(c)
return number
@cocotb.test()
def hello_test(dut):
yield Timer(100)
for i in range (1000):
if i == 200:
dut.TEST_TITLE=convert_string("passed 200")
elif i == 400:
dut.TEST_TITLE=convert_string("passed 400")
dut.maxigp0arvalid=0
yield Timer(10000)
dut.maxigp0arvalid=1
yield Timer(10000)
"""
\ No newline at end of file
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment