Commit 1495fe18 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

making cocotb to complete w/o reporting an error

parent a4c2c048

.gitignore

+3 −1
Original line number Diff line number Diff line
@@ -55,3 +55,5 @@ workingSet.psf 
*.fst

cocotb/Makefile

cocotb/sim_build

cocotb/results.xml

*.directory
 
 No newline at end of file

cocotb/x393_dut.v

+1 −3
Original line number Diff line number Diff line
@@ -743,7 +743,6 @@ assign #10 gpio_pins[9] = gpio_pins[8]; 
    wire [31:0] PS_REG_DOUT;

    reg  [31:0] PS_RDATA;  // SuppressThisWarning VEditor - not used - just view

    wire [31:0] PS_REG_DOUT1;



  initial begin

    PS_REG_ADDR <= 'bx;

    PS_REG_WR   <= 0;
@@ -1739,7 +1738,6 @@ simul_axi_hp_wr #( 
        IRQ_SATA_DONE =  0;

        #5000;

        $finish;

        

    end



assign x393_i.ps7_i.FCLKCLK=        {4{CLK}};

cocotb/x393buses.py

+6 −11
Original line number Diff line number Diff line
@@ -223,16 +223,16 @@ class MAXIGPMaster(BusDriver): 
        @param id transaction ID 

        @param dsize - data width - (1 << dsize) bytes (MAXIGP has only 2 bits while AXI specifies 3) 2 means 32 bits

        """

#        self.log.debug ("MAXIGPMaster._send_write_data(",data,", ",wrstb,", ", delay,", ",id,", ",dsize)

        self.log.debug ("MAXIGPMaster._send_write_data("+str(data)+", "+str(wrstb)+", "+str(delay)+", "+str(id)+", "+str(dsize))

        yield self.busy_channels[W_CHN].acquire()

        self.log.debug ("MAXIGPMaster._send_write_data(): acquired lock")

        for cycle in range(delay):

            yield RisingEdge(self.clock)



        self.log.debug ("MAXIGPMaster._send_write_address(): delay over")

        self.bus.wvalid <= 1

        self.bus.wid <= id

        for i,val_wstb in enumerate(zip(data,wrstb)):

#            self.log.debug ("MAXIGPMaster._send_write_data(), i= ",i,", val_wstb=",val_wstb)

            self.log.debug ("MAXIGPMaster._send_write_data(), i= %d, val_stb=%s "%(i,str(val_wstb)))

            if (i == (len(data) - 1)) or ((i % 16) == 15):

                self.bus.wlast <= 1

            else:
@@ -250,14 +250,7 @@ class MAXIGPMaster(BusDriver): 
        self._float_signals((self.bus.wdata,self.bus.wstb,self.bus.wlast))

        self.busy_channels[W_CHN].release()

        self.log.debug ("MAXIGPMaster._send_write_data(): released lock %s"%(W_CHN))

    """

    @cocotb.coroutine    

    def print_test(self):

        print ("test2, clock=",self.clock);

        yield Timer(10)

#        yield RisingEdge(self.clock)

        print ("test2, pass2, clock=",self.clock);

   """



    @cocotb.coroutine    

    def axi_write(self, address, value, byte_enable=None, address_latency=0,

              data_latency=0,
@@ -312,6 +305,8 @@ class MAXIGPMaster(BusDriver): 
            self.log.debug ("c_data.join()")

            yield c_data.join()

        yield RisingEdge(self.clock)

        self.log.debug ("All done, returning")



#        result = self.bus.bresp.value

#        raise ReturnValue(0) #result)

        """

cocotb/x393coco_02.py

+15 −19
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ from cocotb.result import ReturnValue, TestFailure, TestError, TestSuccess 


import logging





class X393_cocotb_02(object):

    def __init__(self, dut, debug=True):

        self.dut = dut
@@ -40,32 +39,25 @@ class X393_cocotb_02(object): 
        level = logging.DEBUG if debug else logging.WARNING

        self.axiwr.log.setLevel(level)



        

    def print_test(self):

        print ("test");    

@cocotb.coroutine

def run_test(dut, data_in=None, config_coroutine=None, idle_inserter=None,

             backpressure_inserter=None):

    print ("run_test(): starting X393_cocotb_02(dut) init")

#    self.log.info ("MAXIGPMaster._send_write_data(): released lock %s"%(W_CHN))



#    self.log.info  ("run_test(): starting X393_cocotb_02(dut) init")

    tb = X393_cocotb_02(dut)

    print ("run_test(): X393_cocotb_02(dut) done")

#    self.log.info  ("run_test(): X393_cocotb_02(dut) done")

    yield Timer(10000)

#    print ("run_test(): First timer wait done")

#    yield RisingEdge(dut.dutm0_aclk)

#    yield ReadOnly()

#    raise TestSuccess("All done for now")





    while dut.reset_out.value.get_binstr() != "1":

#        print ("Waiting for reset .., reset_out=",dut.reset_out.value)

        yield Timer(10000)



    while dut.reset_out.value:

#        print ("Waiting for reset ..,reset_out=",dut.reset_out.value)

        yield Timer(10000)

#    print ("Waiting for reset over...,reset_out=",dut.reset_out.value)

        

#    for i in range (10):

#        yield RisingEdge(tb.clock)

#    print ("10 clocks later: reset_out=",dut.reset_out.value)

#    tb.print_test();

#    yield tb.axiwr.print_test();

#    yield tb.axiwr.print_test();

#    yield tb.axiwr.print_test();

    yield tb.axiwr.axi_write(address = 0x1234,

                     value = [0,1,2,3,4,5,6,7,8],

                     byte_enable=None,
@@ -77,9 +69,13 @@ def run_test(dut, data_in=None, config_coroutine=None, idle_inserter=None, 
    dut._log.info("Almost there")

    yield Timer(1000)

    dut._log.info("Ok!")

#    raise TestSuccess("All done for now")

#    raise TestSuccess()

    

#    raise TestSuccess("All done for now")

    print("*******************************************")

    cocotb.regression.tear_down()



#print("Main done")    



"""

MODULE=test_endian_swapper