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Commit 1417d17e authored by Andrey Filippov's avatar Andrey Filippov
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finalized DQS input delay vs clock phase adjustment, combined all current... 

finalized DQS input delay vs clock phase adjustment, combined all current results together as a function of the clock phase
parent faaa504f
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Showing with 314 additions and 51 deletions
py393/get_test_dq_dqs_data.py
View file @ 1417d17e
...@@ -600,6 +600,58 @@ def get_dqi_dqsi(): ...@@ -600,6 +600,58 @@ def get_dqi_dqsi():
None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None,
None, None, None, None, None, None, None, None, None, None, None] None, None, None, None, None, None, None, None, None, None, None]
} }
def get_maxErrDqs():
return {
'early': [None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None,
None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None,
None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None,
None, None, None, None, None, None, None, None, None, None, None, None, None, None,
[None, 64.362368028137894], [None, 60.302194877085981], [None, 57.647859713806497], [None, 52.291423247639955], [None, 45.786023431197577], [None, 62.652894325335417],
[None, 60.557409231331356], [None, 58.408281552858178], [None, 60.999981314941245], [None, 65.421884511722794], [50.237142039106317, 63.199432286247571],
[42.318148107136068, 63.239125888953886], [41.538888443111688, 60.584790725674402], [42.889192801896911, 61.083001361402474], [43.529422881523061, 62.777005155999802],
[56.403422132681627, 64.428413897485285], [60.611820094492721, 62.691363553713224], [61.92538079530528, 61.924777990725495], [54.735888483939341, 59.743014096351125],
[56.515433497571749, 61.47385519284785], [62.748846533787678, 63.442643973329268], [54.266395693386677, 61.890510754230952], [55.579956394199009, 59.236175590951468],
[57.416067300930322, 62.333082837840841], [60.261275728468938, 64.199294894521486], [53.229213376288939, 61.945932460921625], [60.533001322865516, 63.757641247713224],
[61.557735427846083, 62.815432605484865], [54.657069712311909, 58.852359481592003], [54.425672609429782, 60.656875181887543], [59.467910273833496, 61.246435197959869],
[53.924572880883488, 64.45713851067498], [55.23813358169582, 62.719016457544093], [55.839925177499225, 58.948775629532548], [61.566879599624116, 60.790128631727512],
[54.046083021004591, 60.382098985693375], [60.38707627184337, 64.442272136745061], [59.073515571031265, 62.78743925890857], [64.307482321184608, 58.880352828168078],
[58.580527899059263, 60.758543132262687], [57.452840958494306, 64.765505556914746], [63.105834948279863, 60.705332405862833], [64.419395649092422, 58.935972089982478],
[57.229903337726483, 60.472290777817484], [55.068968755413863, 66.207436162142642], [60.599986309400691, 60.664636149120639], [59.958689597373933, 64.724809300172552],
[61.272250298186037, 62.384602396234413], [55.842536287795468, 60.754716813399689], [55.37327622693752, 62.706581721293162], [63.58425838093919, 64.60747945679077],
[56.97441752583498, 61.096094251843738], [58.287978226647539, 60.13703706580646], [55.37535553690438, 60.976775925322897], [55.840456977829007, 67.482175741765502],
[59.785192039405473, 63.202782974627048], [53.249010887157141, 63.070874526402008], [51.935450186345037, 60.416539363122524], [57.817824439147756, 60.450092665649841],
[54.532660085694502, 66.340146180008503], [53.477056696116023, 64.116992627172976], [56.105693408017345, 61.586581081461645], [54.792132707204786, 61.2383770579927],
[54.961141918287666, 62.151790521307987], [60.02585305639515, 68.657190337750592]],
'late': None,
'nominal':[[58.315688644802336, 67.941608106525962], [58.699553582372133, 68.216610867075019], [60.013114283184464, 70.870946030354617], [55.522383831337692, 76.227382496521045],
[61.249338253462469, 82.73278231296365], [61.034502057891714, 67.5297317675778], [57.605481866448571, 71.589904918629486], [56.291921165636239, 74.244240081909084],
[59.922883974521909, 79.600676548075512], [54.195929552397018, 83.67318795743563], [59.323986578282543, 69.034479028836927], [59.598161170434622, 73.094652179888612],
[58.284600469622177, 75.748987343168324], [57.930204670535858, 81.105423809334752], [56.480323133327346, 82.16844069617639], [61.330901916723263, 67.260539655001878],
[57.1547706919566, 70.862730136048185], [55.841209991144268, 73.517065299327783], [63.030702302510207, 78.873501765494325], [61.812833478946203, 84.400362740016817],
[60.701948729767963, 68.734704692647142], [59.058996045201383, 72.794877843698828], [57.745435344389051, 75.449213006978539], [64.93492765575499, 80.805649473144967],
[59.90860812570142, 82.468215032366061], [60.656112778776873, 68.968996520593123], [57.545538650434395, 73.029169671644809], [56.231977949622063, 75.683504834924292],
[63.421470260988002, 81.039941301090835], [61.422065520468408, 82.233923204420421], [59.0723881878383, 69.777825095129515], [61.486287718935813, 73.837998246180973],
[62.799848419748145, 76.492333409460684], [55.610356108382206, 81.848769875626999], [49.883401686257542, 81.425094629884256], [59.468916655554352, 67.364298434866157],
[49.457102358747392, 67.381440082119184], [50.770663059559723, 70.035775245398895], [43.581170748193784, 75.39221171156521], [47.514454116243556, 81.897611528007815],
[54.692502136879142, 64.117246184170369], [45.355112786426673, 68.177419335222055], [46.668673487239232, 67.127024437697798], [45.748971840204618, 72.108322158970054],
[51.475926262329509, 78.613721975412659], [47.843894416891828, 63.434627451836832], [50.224282887023733, 65.513403513357559], [48.910722186211629, 68.167738676637043],
[56.100214497577568, 69.407469035206191], [61.827168919702231, 75.912868851648795], [49.794998872208467, 63.680659950289225], [59.806813169015427, 67.740833101340911],
[58.493252468203096, 67.563610671578488], [61.344311744412394, 71.598061321290174], [55.832450549015419, 78.103461137733007], [56.252879268922939, 64.844137581795167],
[60.762362958251757, 65.693923112906475], [62.075923659063861, 68.348258276185959], [56.845540347981768, 69.514314030956371], [60.831802681417201, 76.019713847398975],
[59.513305357913865, 67.313140050960271], [60.891652992573398, 67.146095188716004], [61.199083758137675, 69.800430351995715], [59.528416030051488, 75.15686681816203],
[65.255370452176379, 81.662266634604634], [56.755340584613137, 68.350709489080089], [57.851524394896131, 69.404187282975613], [59.165085095708463, 72.058522446255097],
[63.101323175941246, 77.414958912421639], [61.742212605515391, 83.920358728864244], [60.46566380481292, 67.094767107715484], [65.155845000490075, 71.154940258767169],
[63.842284299677743, 73.809275422046653], [59.538713592537619, 79.165711888213195], [53.811759170412955, 84.10815261729806], [61.019085163593758, 69.111367814980326],
[59.539590743180355, 73.171540966032012], [60.853151443992687, 75.825876129311496], [53.663659132626748, 81.182312595478265], [47.936704710502084, 82.091551910033218],
[61.789043745989915, 71.014923668091456], [54.674145892434325, 75.075096819143369], [55.987706593246656, 77.729431982422852], [48.798214281880718, 83.085868448589395],
[48.121640480828944, 80.187996056922088], [56.678274101447158, 69.59142914724805], [50.252678538604385, 73.651602298299736], [51.566239239416717, 76.305937461579219],
[48.643203555507114, 81.662373927745762], [44.607277629406795, 81.611490577765494], [54.303834394941731, 58.180895973608642], [52.627118245110267, None],
[53.940678945922372, None], [46.751186634556433, None], [47.113542363600516, None], None, None, None, None, None, None, None, None, None, None, None, None, None,
None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None,
None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None],
}
def get_adjust_cmda_odelay(): def get_adjust_cmda_odelay():
return { return {
'cmda_odly_period':-1, 'cmda_odly_period':-1,
......
py393/x393_lma.py
View file @ 1417d17e
...@@ -296,6 +296,7 @@ class X393LMA(object): ...@@ -296,6 +296,7 @@ class X393LMA(object):
def showENLresults(self, def showENLresults(self,
DQvDQS): DQvDQS):
rslt_names=("early","nominal","late") rslt_names=("early","nominal","late")
err_name='maxErrDqs'
numBits=0 numBits=0
for n in DQvDQS: for n in DQvDQS:
try: try:
...@@ -311,15 +312,23 @@ class X393LMA(object): ...@@ -311,15 +312,23 @@ class X393LMA(object):
pass pass
if not numBits: if not numBits:
raise Exception("showENLresults(): No no-None data provided") raise Exception("showENLresults(): No no-None data provided")
numLanes=numBits//8
# print ("numBits=%d"%(numBits)) # print ("numBits=%d"%(numBits))
enl_list=[] enl_list=[]
for k in rslt_names: for k in rslt_names:
if DQvDQS[k]: if DQvDQS[k]:
enl_list.append(k) enl_list.append(k)
print("DQS", end=" ") print("DQS", end=" ")
for enl in enl_list: for enl in enl_list:
for b in range(numBits): for b in range(numBits):
print("%s%d"%(enl[0].upper(),b),end=" ") print("%s%d"%(enl[0].upper(),b),end=" ")
for enl in enl_list:
for lane in range(numLanes):
if numLanes > 1:
print("%s%d_err"%(enl[0].upper(),lane),end=" ")
else:
print("%s_err"%(enl[0].upper()),end=" ")
print() print()
for dly in range(len(DQvDQS[enl_list[0]])): for dly in range(len(DQvDQS[enl_list[0]])):
print ("%d"%(dly),end=" ") print ("%d"%(dly),end=" ")
...@@ -332,6 +341,25 @@ class X393LMA(object): ...@@ -332,6 +341,25 @@ class X393LMA(object):
print("?",end=" ") print("?",end=" ")
else: else:
print("%d"%(DQvDQS[enl][dly][b]),end=" ") print("%d"%(DQvDQS[enl][dly][b]),end=" ")
for enl in enl_list:
# if numLanes>1:
# print ("DQvDQS[err_name]=",DQvDQS[err_name])
# print ("DQvDQS[err_name][enl]=",DQvDQS[err_name][enl])
# print ("DQvDQS[err_name][enl][dly]=",DQvDQS[err_name][enl][dly])
if DQvDQS[err_name][enl][dly] is None:
print ("? "*numLanes,end="")
else:
for lane in range(numLanes):
if DQvDQS[err_name][enl][dly] is None:
print("?",end=" ")
else:
if numLanes > 1:
if DQvDQS[err_name][enl][dly][lane] is None:
print("?",end=" ")
else:
print("%.1f"%(DQvDQS[err_name][enl][dly][lane]),end=" ")
else:
print("%.1f"%(DQvDQS[err_name][enl][dly]),end=" ")
print() print()
...@@ -853,8 +881,9 @@ class X393LMA(object): ...@@ -853,8 +881,9 @@ class X393LMA(object):
lane_rslt=[] lane_rslt=[]
numLanes=2 numLanes=2
parametersKey='parameters' parametersKey='parameters'
errorKey='maxErrDqs'
for lane in range(numLanes): for lane in range(numLanes):
lane_rslt.append(self.lma_fit(lane, # byte lane lane_rslt.append(self.lma_fit_dqi_dqsi(lane, # byte lane
bin_size, bin_size,
clk_period, clk_period,
dly_step_ds, dly_step_ds,
...@@ -865,8 +894,8 @@ class X393LMA(object): ...@@ -865,8 +894,8 @@ class X393LMA(object):
quiet)) quiet))
rslt={} rslt={}
for k in lane_rslt[0].keys(): for k in lane_rslt[0].keys():
if k != parametersKey: if (k != parametersKey) and (k != errorKey):
for r in lane_rslt: for r in lane_rslt: # lane_rslt is list of two dictionaries
try: try:
l=len(r[k]) l=len(r[k])
break break
...@@ -892,7 +921,41 @@ class X393LMA(object): ...@@ -892,7 +921,41 @@ class X393LMA(object):
rslt[parametersKey] = [] rslt[parametersKey] = []
for lane in range(numLanes): for lane in range(numLanes):
rslt[parametersKey].append(lane_rslt[lane][parametersKey]) rslt[parametersKey].append(lane_rslt[lane][parametersKey])
rslt[errorKey]={}
# print ("lane_rslt[0][errorKey]=",lane_rslt[0][errorKey])
for k in lane_rslt[0][errorKey].keys():
for r in lane_rslt: # lane_rslt is list of two dictionaries
try:
l=len(r[errorKey][k])
break
except:
pass
else:
rslt[errorKey][k]=None
continue
rslt[errorKey][k]=[]
for dly in range(l):
w=[]
for lane in range(numLanes):
if (lane_rslt[lane][errorKey][k] is None) or (lane_rslt[lane][errorKey][k][dly] is None):
w.append(None)
else:
w.append(lane_rslt[lane][errorKey][k][dly])
for lane in w:
if not lane is None:
rslt[errorKey][k].append(w)
break
else:
rslt[errorKey][k].append(None)
# print ("lane_rslt[0][errorKey]=",lane_rslt[0][errorKey])
# print ("lane_rslt[1][errorKey]=",lane_rslt[1][errorKey])
# print ("combined: rslt['maxErrDqs']=",rslt['maxErrDqs'])
# print ("rslt=",rslt)
return rslt # byte lanes combined return rslt # byte lanes combined
# rslt['parameters']=parameters
# rslt['maxErrDqs']=DQvDQS_ERR # {enl}[dly]
...@@ -1057,10 +1120,14 @@ class X393LMA(object): ...@@ -1057,10 +1120,14 @@ class X393LMA(object):
self.showYOrVector(ywp,True,fx) self.showYOrVector(ywp,True,fx)
# calculate DQ[i] vs. DQS for -1, 0 and +1 period # calculate DQ[i] vs. DQS for -1, 0 and +1 period
DQvDQS=self.getBestDQforDQS(parameters, DQvDQS_withErr=self.getBestDQforDQS(parameters,
primary_set, primary_set,
quiet) quiet)
DQvDQS= DQvDQS_withErr['dqForDqs']
DQvDQS_ERR=DQvDQS_withErr['maxErrDqs']
if quiet < 4: if quiet < 4:
# print ("DQvDQS_ERR=",DQvDQS_ERR)
enl_list=[] enl_list=[]
for i in range(3): for i in range(3):
if not DQvDQS[i] is None: if not DQvDQS[i] is None:
...@@ -1069,6 +1136,8 @@ class X393LMA(object): ...@@ -1069,6 +1136,8 @@ class X393LMA(object):
for enl in enl_list: for enl in enl_list:
for b in range(8): for b in range(8):
print("%s%d"%(('E','N','L')[enl],b),end=" ") print("%s%d"%(('E','N','L')[enl],b),end=" ")
for enl in enl_list:
print("%s-Err"%(('E','N','L')[enl]),end=" ")
print() print()
for dly in range(DLY_STEPS): for dly in range(DLY_STEPS):
print ("%d"%(dly),end=" ") print ("%d"%(dly),end=" ")
...@@ -1081,12 +1150,26 @@ class X393LMA(object): ...@@ -1081,12 +1150,26 @@ class X393LMA(object):
print("?",end=" ") print("?",end=" ")
else: else:
print("%d"%(DQvDQS[enl][dly][b]),end=" ") print("%d"%(DQvDQS[enl][dly][b]),end=" ")
for enl in enl_list:
if DQvDQS_ERR[enl][dly] is None:
print ("? ",end="")
else:
print ("%f"%(DQvDQS_ERR[enl][dly]), end=" ")
print() print()
rslt={} rslt={}
rslt_names=("early","nominal","late") rslt_names=("early","nominal","late")
for i, d in enumerate(DQvDQS): for i, d in enumerate(DQvDQS):
rslt[rslt_names[i]] = d rslt[rslt_names[i]] = d
rslt['parameters']=parameters rslt['parameters']=parameters
rslt['maxErrDqs']={} # {enl}[dly]
for i, d in enumerate(DQvDQS_ERR):
rslt['maxErrDqs'][rslt_names[i]] = d
if quiet < 4:
self.showDQDQSValues(parameters)
# print ("DQvDQS_ERR=",DQvDQS_ERR)
# print ("rslt['maxErrDqs']=",rslt['maxErrDqs'])
return rslt return rslt
# return DQvDQS # return DQvDQS
# Returns 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list, # Returns 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list,
...@@ -1107,75 +1190,80 @@ class X393LMA(object): ...@@ -1107,75 +1190,80 @@ class X393LMA(object):
tDQ= parameters['tDQ'] # list tDQ= parameters['tDQ'] # list
tCDQS32=list(parameters['tCDQS'][0:8])+[0]+list(parameters['tCDQS'][8:23])+[0]+list(parameters['tCDQS'][23:30]) tCDQS32=list(parameters['tCDQS'][0:8])+[0]+list(parameters['tCDQS'][8:23])+[0]+list(parameters['tCDQS'][23:30])
# tDQSHL =parameters['tDQSHL']#single value
# tDQHL= parameters['tDQHL'] # list
tFDQs=[] tDQSHL =parameters['tDQSHL']#single value
tDQHL= parameters['tDQHL'] # list
tFDQs=[] #corrections in steps?
for b in range(8): for b in range(8):
tFDQi=list(parameters['tFDQ'][4*b:4*(b+1)]) tFDQi=list(parameters['tFDQ'][4*b:4*(b+1)])
tFDQi.append(-tFDQi[0]-tFDQi[1]-tFDQi[2]-tFDQi[3]) tFDQi.append(-tFDQi[0]-tFDQi[1]-tFDQi[2]-tFDQi[3])
for i in range(5):
tFDQi[i]/=tSDQ[b]
tFDQs.append(tFDQi) tFDQs.append(tFDQi)
#calculate worst bit error caused by duty cycles (asymmetry) of DQS and DQ lines
#bit delay error just adds to the 0.25*(abs(tDQSHL)+abs(tDQHL))
asym_err=[]
for i in range(8):
asym_err.append(0.25*(abs(tDQSHL)+abs(tDQHL[i])))
print("asym_err=",asym_err)
dqForDqs=[] dqForDqs=[]
maxErrDqs=[]
for enl in (0,1,2): for enl in (0,1,2):
vDQ=[] vDQ=[]
vErr=[]
someData=False someData=False
for dly in range(DLY_STEPS): for dly in range(DLY_STEPS):
tdqs=dly * tSDQS - tDQS - tFDQS5[dly % FINE_STEPS] # t - time from DQS pad to internal DQS clock with zero setup/hold times to DQ FFs tdqs=dly * tSDQS - tDQS - tFDQS5[dly % FINE_STEPS] # t - time from DQS pad to internal DQS clock with zero setup/hold times to DQ FFs
tdqs-=tCDQS32[dly // FINE_STEPS] tdqs-=tCDQS32[dly // FINE_STEPS]
tdq3=tdqs +(-0.75+enl)*period # (early, nominal, late) tdqs3=tdqs +(-0.75+enl)*period # (early, nominal, late) in ps, centered in the middle
bDQ=[] bDQ=[]
errDQ=None
# dbg_worstBit=None
# dbg_errs=[None]*8
for b in range(8): # use all 4 variants for b in range(8): # use all 4 variants
tdq=(tdq3+tDQ[b])/tSDQ[b] tdq=(tdqs3+tDQ[b])/tSDQ[b]
itdq=int(round(tdq)) # in delay steps itdq=int((tdqs3+tDQ[b])/tSDQ[b]) # in delay steps, approximate (not including tFDQ
bestDQ=None bestDQ=None
if (itdq >= 0) and (itdq < DLY_STEPS): if (itdq >= 0) and (itdq < DLY_STEPS):
bestDiff=None bestDiff=None
for idq in range (max(itdq-FINE_STEPS,0),min(itdq+FINE_STEPS,DLY_STEPS-1)+1): for idq in range (max(itdq-FINE_STEPS,0),min(itdq+FINE_STEPS,DLY_STEPS-1)+1):
diff=idq-tFDQs[b][idq % FINE_STEPS] tdq=idq * tSDQ[b] - tDQ[b] - tFDQs[b][idq % FINE_STEPS]
if (bestDQ is None) or (abs(diff) < bestDiff): diff=tdq - tdqs3 # idq-tFDQs[b][idq % FINE_STEPS]
if (bestDQ is None) or (abs(diff) < abs(bestDiff)):
bestDQ=idq bestDQ=idq
bestDiff=abs(diff) bestDiff=diff
if bestDQ is None: if bestDQ is None:
bDQ=None bDQ=None
break break
bDQ.append(bestDQ) bDQ.append(bestDQ) #tuple(delay,signed error in ps)
"""
fullBitErr=bestDiff # +asym_err[b] #TODO: Restore the full error!
if (errDQ is None) or (abs(fullBitErr) > abs (errDQ)):
errDQ= fullBitErr
"""
fullBitErr=abs(bestDiff) +asym_err[b] #TODO: Restore the full error!
# dbg_errs[b]=abs(bestDiff)
if (errDQ is None) or (fullBitErr > errDQ):
errDQ= fullBitErr
# dbg_worstBit=b
someData=True someData=True
vDQ.append(bDQ) vDQ.append(bDQ)
vErr.append(errDQ)
## if dbg_worstBit is None:
## vErr.append(None)
## else:
# vErr.append(asym_err[dbg_worstBit])
# vErr.append(10*dbg_worstBit)
# vErr.append(dbg_errs[2])
## vErr.append(dbg_errs[5])
# print ("enl=%d, dly=%d, err=%s"%(enl,dly,str(errDQ)))
if someData: if someData:
dqForDqs.append(vDQ) dqForDqs.append(vDQ)
maxErrDqs.append(vErr)
else: else:
dqForDqs.append(None) dqForDqs.append(None)
return dqForDqs maxErrDqs.append(None)
""" return {'dqForDqs':dqForDqs,'maxErrDqs':maxErrDqs}
for dly in range(DLY_STEPS):
tdqs=dly * tSDQS - tDQS - tFDQS5[dly % FINE_STEPS] # t - time from DQS pad to internal DQS clock with zero setup/hold times to DQ FFs
tdq3=(tdqs-0.75*period, tdqs + 0.25*period,tdqs + 1.25*period) # (early, nominal, late)
bDQ=[]
allBits=[True,True,True]
for b in range(8): # use all 4 variants
vDQ=[]
for enl in (0,1,2):
tdq=(tdq3[enl]+tDQ[b])/tSDQ[b]
itdq=int(round(tdq)) # in delay steps
bestDQ=None
if (itdq >= 0) and (itdq < DLY_STEPS):
bestDiff=None
for idq in range (max(itdq-FINE_STEPS,0),min(itdq+FINE_STEPS,DLY_STEPS-1)+1):
diff=idq-tFDQs[b][idq % FINE_STEPS]
if (bestDQ is None) or (abs(diff) < bestDiff):
bestDQ=idq
bestDiff=abs(diff)
if bestDQ is None:
allBits[enl] = False
vDQ.append(bestDQ)
bDQ.append(vDQ)
dqForDqs.append(bDQ)
"""
""" """
ir = ir0 - s/4 + d/4 # ir - convert to ps from steps ir = ir0 - s/4 + d/4 # ir - convert to ps from steps
...@@ -1187,6 +1275,34 @@ class X393LMA(object): ...@@ -1187,6 +1275,34 @@ class X393LMA(object):
s=if-ir+of-or s=if-ir+of-or
d=ir-if+of-or d=ir-if+of-or
""" """
def showDQDQSValues(self,
parameters):
tFDQS5=list(parameters['tFDQS'])
tFDQS5.append(-tFDQS5[0]-tFDQS5[1]-tFDQS5[2]-tFDQS5[3])
tSDQS=parameters['tSDQS']
tSDQ= parameters['tSDQ'] # list
tCDQS32=list(parameters['tCDQS'][0:8])+[0]+list(parameters['tCDQS'][8:23])+[0]+list(parameters['tCDQS'][23:30])
tFDQs=[] #corrections in steps?
for b in range(8):
tFDQi=list(parameters['tFDQ'][4*b:4*(b+1)])
tFDQi.append(-tFDQi[0]-tFDQi[1]-tFDQi[2]-tFDQi[3])
tFDQs.append(tFDQi)
print("\nRelative delay vs delay value")
print ("dly DSQS", end=" ")
for b in range(8):
print ("DQ%d"%(b),end=" ")
print ()
for dly in range(DLY_STEPS): # no constant delay - just scale and corrections
print ("%d"%(dly),end=" ")
tdqs=dly * tSDQS - tFDQS5[dly % FINE_STEPS] # t - time from DQS pad to internal DQS clock with zero setup/hold times to DQ FFs
tdqs-=tCDQS32[dly // FINE_STEPS]
print("%.3f"%(tdqs),end=" ")
for b in range(8):
tdq=dly * tSDQ[b] - tFDQs[b][dly % FINE_STEPS]
print("%.3f"%(tdq),end=" ")
print()
def createFxAndJacobian(self, def createFxAndJacobian(self,
parameters, parameters,
y_data, # keep in self.variable? y_data, # keep in self.variable?
......
py393/x393_mcntrl_adjust.py
View file @ 1417d17e
...@@ -2346,12 +2346,12 @@ class X393McntrlAdjust(object): ...@@ -2346,12 +2346,12 @@ class X393McntrlAdjust(object):
to reduce debugging time for nest stages to reduce debugging time for nest stages
""" """
self.adjustment_state["dqi_dqsi"]= get_test_dq_dqs_data.get_dqi_dqsi() self.adjustment_state["dqi_dqsi"]= get_test_dq_dqs_data.get_dqi_dqsi()
self.adjustment_state["dqi_dqsi_parameters"]=get_test_dq_dqs_data.get_dqi_dqsi_parameters() self.adjustment_state["maxErrDqs"]= get_test_dq_dqs_data.get_maxErrDqs()
self.adjustment_state["dqi_dqsi_parameters"]= get_test_dq_dqs_data.get_dqi_dqsi_parameters()
self.adjustment_state.update(get_test_dq_dqs_data.get_adjust_cmda_odelay()) self.adjustment_state.update(get_test_dq_dqs_data.get_adjust_cmda_odelay())
self.adjustment_state.update(get_test_dq_dqs_data.get_wlev_data()) self.adjustment_state.update(get_test_dq_dqs_data.get_wlev_data())
self.adjustment_state.update(get_test_dq_dqs_data.get_dqsi_phase()) self.adjustment_state.update(get_test_dq_dqs_data.get_dqsi_phase())
def proc_dqi_dqsi(self, def proc_dqi_dqsi(self,
lane="all", lane="all",
bin_size=5, bin_size=5,
...@@ -2424,7 +2424,18 @@ class X393McntrlAdjust(object): ...@@ -2424,7 +2424,18 @@ class X393McntrlAdjust(object):
for k,v in rslt.items(): for k,v in rslt.items():
print ("'%s':%s,"%(k,str(v))) print ("'%s':%s,"%(k,str(v)))
print ("}") print ("}")
self.adjustment_state["dqi_dqsi_parameters"]=rslt.pop('parameters') self.adjustment_state["dqi_dqsi_parameters"]=rslt.pop('parameters')
try:
self.adjustment_state["maxErrDqs"]=rslt.pop('maxErrDqs')
if quiet<5:
print("maxErrDqs={")
for k,v in self.adjustment_state["maxErrDqs"].items():
print ("'%s':%s,"%(k,str(v)))
print ("}")
except:
print ("maxErrDqs does not exist")
self.adjustment_state["dqi_dqsi"]=rslt self.adjustment_state["dqi_dqsi"]=rslt
return rslt return rslt
...@@ -2485,3 +2496,87 @@ class X393McntrlAdjust(object): ...@@ -2485,3 +2496,87 @@ class X393McntrlAdjust(object):
quiet=1) quiet=1)
self.adjustment_state.update(dqsi_phase) self.adjustment_state.update(dqsi_phase)
return dqsi_phase return dqsi_phase
def show_all_vs_phase(self, load_hardcoded=False):
if load_hardcoded:
self.load_hardcoded_data()
rslt_names=("early","nominal","late")
DQvDQS=self.adjustment_state["dqi_dqsi"]
cmda_bspe=self.adjustment_state['cmda_bspe']
dqsi_phase=self.adjustment_state['dqsi_phase']
wlev_dqs_bspe=self.adjustment_state['wlev_dqs_bspe']
numBits=0
for n in DQvDQS:
try:
for d in DQvDQS[n]:
try:
numBits=len(d)
break
except:
pass
break
except:
pass
if not numBits:
raise Exception("showENLresults(): No no-None data provided")
numLanes=numBits//8
enl_list=[]
for k in rslt_names:
if DQvDQS[k]:
enl_list.append(k)
timing=self.x393_mcntrl_timing.get_dly_steps()
numPhaseSteps= int(timing['SDCLK_PERIOD']/timing['PHASE_STEP']+0.5)
print("Phase CMDA",end=" ")
for lane in range(numLanes):
print("DQS%di"%(lane),end=" ")
for k in enl_list:
for b in range(numBits):
print("%s-DQ%di"%(k.upper()[0], b),end=" ")
for lane in range(numLanes):
print("DQS%d0"%(lane),end=" ")
#TODO: add DQ%do
print()
for phase in range(numPhaseSteps):
print("%d"%(phase),end=" ")
#CMDA_ODEALY
if not cmda_bspe[phase]['ldly'] is None:
print("%d"%(cmda_bspe[phase]['ldly']),end=" ")
else:
print ("?",end=" ")
#DQS_IDEALY
# print ('\n\ndqsi_phase=',dqsi_phase)
for lane in range(numLanes):
if not dqsi_phase[lane][phase] is None:
print("%d"%(dqsi_phase[lane][phase]),end=" ")
else:
print ("?",end=" ")
#DQ_IDEALY, with half/clock variants
for k in enl_list:
for b in range(numBits):
lane=b//8
dqs_dly=dqsi_phase[lane][phase]
valid = not dqs_dly is None
valid = valid and not DQvDQS[k] is None
valid = valid and not DQvDQS[k][dqs_dly] is None
valid = valid and not DQvDQS[k][dqs_dly][b] is None
if valid:
print("%d"%(DQvDQS[k][dqs_dly][b]),end=" ")
else:
print ("?",end=" ")
#DQS_ODEALY
for lane in range(numLanes):
if (not wlev_dqs_bspe[lane][phase] is None) and (not wlev_dqs_bspe[lane][phase]['ldly'] is None):
print("%d"%(wlev_dqs_bspe[lane][phase]['ldly']),end=" ")
else:
print ("?",end=" ")
print()
\ No newline at end of file
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