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Commit 12ed7ed1 authored by Andrey Filippov's avatar Andrey Filippov
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working on dct-iv

parent 79b43da3
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dct_tests_01.sav
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dsp/dct_iv.ods
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dsp/dct_iv8_1d.v
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......@@ -71,7 +71,9 @@ module dct_iv8_1d#(
output [OUT_WIDTH -1:0] dout,
output reg pre2_start_out, // 2 clock cycle before Y0 output, full dout sequence
// start_out-x-Y0-x-Y7-x-Y4-x-Y3-x-Y1-x-Y6-x-Y2-x-Y5
output reg en_out // valid at the same time slot as pre2_start_out (goes active with pre2_start_out)
output en_out, // valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 1 ahead of data
output reg [2:0] y_index // for simulation - valid with dout - index of the data output
);
// X6-X7-X5-X2-X1-X3-X0-X4-*-X5-X1-X2-*-X4-X7-*
// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*
......@@ -132,6 +134,9 @@ module dct_iv8_1d#(
reg run_in; // receiving input data
reg restart; // restarting next block if en was active at phase=14;
reg run_out; // running output data
reg en_out_r;
assign en_out = en_out_r;
assign dsp_ain_2 = dsp_p_1 [STAGE1_RSHIFT +: A_WIDTH];
......@@ -147,6 +152,23 @@ module dct_iv8_1d#(
wire din_zero = ~(|d_in);
assign dsp_cin_1 = {{P_WIDTH-WIDTH-COSINE_SHIFT{d_in[WIDTH-1]}},d_in,~d_in[WIDTH-1]^din_zero,{COSINE_SHIFT-1{d_in[WIDTH-1]}}};
always @ (posedge clk) begin
if (en_out_r) begin
case (phase_cnt[3:1])
3'h0: y_index <= 7;
3'h1: y_index <= 4;
3'h2: y_index <= 3;
3'h3: y_index <= 1;
3'h4: y_index <= 6;
3'h5: y_index <= 2;
3'h6: y_index <= 5;
3'h7: y_index <= 0;
endcase
end else begin
y_index <= 'bx;
end
end
//register files
assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra];
......@@ -173,7 +195,7 @@ module dct_iv8_1d#(
pre2_start_out <= run_out && (phase_cnt == 14);
en_out <= run_out && !phase_cnt[0];
en_out_r <= run_out && !phase_cnt[0];
// Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand
case (phase_cnt)
......
dsp/dct_iv_8x8.v 0 → 100644
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dsp/dct_tests_01.tf
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......@@ -40,7 +40,7 @@
`timescale 1ns/1ps
// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
// will reduce needed resources
//`define DCT_INPUT_UNITY
`define DCT_INPUT_UNITY
module dct_tests_01 ();
// parameter fstname="dct_tests_01.fst";
`ifdef IVERILOG
......@@ -65,7 +65,12 @@ module dct_tests_01 ();
parameter WIDTH = 24; // input data width
// parameter OUT_WIDTH = 16; // output data width
parameter OUT_WIDTH = 24; // output data width
parameter TRANSPOSE_WIDTH = 25; // width of the transpose memory (intermediate results)
parameter OUT_RSHIFT = 3; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter OUT_RSHIFT2 = 0; // overall right shift for the second (vertical) pass
parameter DCT_GAP = 16; // between runs
reg RST = 1'b1;
reg CLK = 1'b0;
......@@ -83,11 +88,13 @@ module dct_tests_01 ();
wire x_we = !phase_in[3] && run_in;
reg [WIDTH-1:0] x_in;
reg [WIDTH-1:0] x_in_2d;
reg [WIDTH-1:0] x_out;
reg [WIDTH-1:0] x_ram[0:7];
wire [WIDTH-1:0] x_out_w = x_ram[x_ra];
reg start = 0;
reg start2 = 0; // second start for 2d
wire [OUT_WIDTH-1:0] y_dct; // S uppressThisWarning VEditor - simulation only
wire pre2_start_out; // S uppressThisWarning VEditor - simulation only
......@@ -103,7 +110,22 @@ module dct_tests_01 ();
wire signed [OUT_WIDTH-1:0] y_out = y_ram[y_ra]; // SuppressThisWarning VEditor - simulation only
reg signed [WIDTH-1:0] data_in[0:63];
reg signed [OUT_WIDTH-1:0] data_out[0:63];
integer i,j;
reg signed [WIDTH-1:0] d_in;
wire pre_last_in_2d;
wire pre_first_out_2d;
wire pre_busy_2d;
wire dv_2d;
wire signed [OUT_WIDTH-1:0] d_out_2d;
wire pre_last_in_2dr;
wire pre_first_out_2dr;
wire pre_busy_2dr;
wire dv_2dr;
wire signed [OUT_WIDTH-1:0] d_out_2dr;
integer i,j, i1, j1;
initial begin
for (i=0; i<64; i=i+1) begin
`ifdef DCT_INPUT_UNITY
......@@ -147,23 +169,6 @@ module dct_tests_01 ();
if (&i[2:0]) repeat (8) @(posedge CLK);
end
#1 x_in = 0;
/*
// running 'one' - just make a period == 17
repeat (7) begin
@(posedge CLK);
#1 x_in = {2'b1,{WIDTH-2{1'b0}}}; // >>x_wa;
@(posedge CLK);
#1 x_in = 0;
repeat (15) @(posedge CLK); // 16+1= 17, non-zero will go through all of the 8 x[i]
end
begin
@(posedge CLK);
#1 x_in = {2'b1,{WIDTH-2{1'b0}}};
@(posedge CLK);
#1 x_in = 0;
en_x = 0;
end
*/
repeat (64) @(posedge CLK);
$display("");
......@@ -173,9 +178,45 @@ module dct_tests_01 ();
data_out[i+4],data_out[i+5],data_out[i+6],data_out[i+7]);
end
// repeat (64) @(posedge CLK);
// $finish;
end
initial begin
wait (!RST);
while (!start) begin
@(posedge CLK);
#1;
end
for (i1 = 0; i1 < 64; i1 = i1+1) begin
@(posedge CLK);
#1;
x_in_2d = data_in[i1];
if (i1 == 63) start2 = 1;
end
for (i1 = 0; i1 < 64; i1 = i1+1) begin
@(posedge CLK);
#1;
start2 = 0;
x_in_2d = data_in[i1];
end
repeat (DCT_GAP) @(posedge CLK);
#1;
start2 = 1;
for (i1 = 0; i1 < 64; i1 = i1+1) begin
@(posedge CLK);
#1;
start2 = 0;
x_in_2d = data_in[63-i1];
end
repeat (300) @(posedge CLK);
$finish;
end
initial j = 0;
always @ (posedge CLK) begin
if (y_dv) begin
......@@ -285,7 +326,53 @@ module dct_tests_01 ();
.start (start), // input
.dout (y_dct), // output[15:0]
.pre2_start_out (pre2_start_out), // output reg
.en_out (en_out) // output reg
.en_out (en_out), // output reg
.y_index () // output[2:0] reg
);
dct_iv_8x8 #(
.INPUT_WIDTH (WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.OUT_RSHIFT1 (OUT_RSHIFT),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.DSP_B_WIDTH (18),
.DSP_A_WIDTH (25),
.DSP_P_WIDTH (48)
) dct_iv_8x8_i (
.clk (CLK), // input
.rst (RST), // input
.start (start || start2), // input
.xin (x_in_2d), // input[24:0] signed
.pre_last_in (pre_last_in_2d), // output reg
.pre_first_out (pre_first_out_2d), // output
.dv (dv_2d), // output
.d_out (d_out_2d), // output[24:0] signed
.pre_busy (pre_busy_2d) // output reg
);
dct_iv_8x8 #(
.INPUT_WIDTH (WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.OUT_RSHIFT1 (OUT_RSHIFT),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.DSP_B_WIDTH (18),
.DSP_A_WIDTH (25),
.DSP_P_WIDTH (48)
) dct_iv_8x8r_i (
.clk (CLK), // input
.rst (RST), // input
.start (pre_first_out_2d), // input
.xin (d_out_2d), // input[24:0] signed
.pre_last_in (pre_last_in_2dr), // output reg
.pre_first_out (pre_first_out_2dr), // output
.dv (dv_2dr), // output
.d_out (d_out_2dr), // output[24:0] signed
.pre_busy (pre_busy_2dr) // output reg
);
endmodule
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