working on dct-iv (12ed7ed1) · Commits · Elphel / x393

dct_tests_01.sav

+352 −15

Original line number	Original line	Diff line number	Diff line
	[*]		[*]
	[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI		[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
	[*] Tue Dec 6 17:55:24 2016		[*] Tue Dec 13 06:32:08 2016
	[*]		[*]
	[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-20161206105514691.fst"		[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-20161212230744155.fst"
	[dumpfile_mtime] "Tue Dec 6 17:55:14 2016"		[dumpfile_mtime] "Tue Dec 13 06:07:44 2016"
	[dumpfile_size] 10348		[dumpfile_size] 100634
	[savefile] "/home/eyesis/git/x393-neon/dct_tests_01.sav"		[savefile] "/home/eyesis/git/x393-neon/dct_tests_01.sav"
	[timestart] 0		[timestart] 0
	[size] 1814 1171		[size] 1814 1171
	[pos] 1937 0		[pos] 1920 0
	*-18.387537 1752000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1		*-19.687614 1195000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
	[treeopen] dct_tests_01.		[treeopen] dct_tests_01.
	[treeopen] dct_tests_01.dct_iv8_1d_i.		[treeopen] dct_tests_01.dct_iv8_1d_i.
	[treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.		[treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.
			[treeopen] dct_tests_01.dct_iv_8x8_i.
	[sst_width] 204		[sst_width] 204
	[signals_width] 305		[signals_width] 325
	[sst_expanded] 1		[sst_expanded] 1
	[sst_vpaned_height] 344		[sst_vpaned_height] 344
	@800200		@c00200
	-top		-top
	@25		@24
	dct_tests_01.i		dct_tests_01.i
	dct_tests_01.j		dct_tests_01.j
	@28		@28
	@@ -87,10 +88,50 @@ dct_tests_01.y_we
	dct_tests_01.phase_y[3:0]		dct_tests_01.phase_y[3:0]
	dct_tests_01.y_dct[23:0]		dct_tests_01.y_dct[23:0]
	dct_tests_01.y_out[23:0]		dct_tests_01.y_out[23:0]
	@1000200		dct_tests_01.dct_iv8_1d_i.y_index[2:0]
			@1401200
	-top		-top
	@800200		@800200
			-2d-1d
			@28
			dct_tests_01.start
			@22
			dct_tests_01.x_out[23:0]
			@8420
			dct_tests_01.x_out[23:0]
			dct_tests_01.dct_iv8_1d_i.d_in[23:0]
			dct_tests_01.dct_iv8_1d_i.dout[23:0]
			@28
			dct_tests_01.dct_iv8_1d_i.en_out
			@22
			dct_tests_01.dct_iv8_1d_i.y_index[2:0]
			@8420
			dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.d_in[23:0]
			dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.dout[24:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.en_out
			@22
			dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.y_index[2:0]
			@8420
			dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.d_in[23:0]
			@8421
			dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.dout[24:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.en_out
			@22
			dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.y_index[2:0]
			@200
			-
			@1000200
			-2d-1d
			@c00200
	-dct_iv8_1d		-dct_iv8_1d
			@22
			[color] 2
			dct_tests_01.dct_iv8_1d_i.phase_cnt[3:0]
			@28
			dct_tests_01.dct_iv8_1d_i.en_out
			dct_tests_01.dct_iv8_1d_i.run_out
	@c08022		@c08022
	dct_tests_01.phase_out[3:0]		dct_tests_01.phase_out[3:0]
	@28		@28
	@@ -105,8 +146,6 @@ dct_tests_01.dct_iv8_1d_i.start
	dct_tests_01.dct_iv8_1d_i.restart		dct_tests_01.dct_iv8_1d_i.restart
	dct_tests_01.dct_iv8_1d_i.clk		dct_tests_01.dct_iv8_1d_i.clk
	@8022		@8022
	[color] 2
	dct_tests_01.dct_iv8_1d_i.phase_cnt[3:0]
	dct_tests_01.dct_iv8_1d_i.d_in[23:0]		dct_tests_01.dct_iv8_1d_i.d_in[23:0]
	dct_tests_01.dct_iv8_1d_i.dsp_ain_1[24:0]		dct_tests_01.dct_iv8_1d_i.dsp_ain_1[24:0]
	@28		@28
	@@ -124,8 +163,8 @@ dct_tests_01.dct_iv8_1d_i.dsp_ced_1
	@22		@22
	dct_tests_01.dct_iv8_1d_i.dsp_cin_1[47:0]		dct_tests_01.dct_iv8_1d_i.dsp_cin_1[47:0]
	@28		@28
	dct_tests_01.dct_iv8_1d_i.dsp_cec_1
	dct_tests_01.dct_iv8_1d_i.dsp_neg_m_1		dct_tests_01.dct_iv8_1d_i.dsp_neg_m_1
			dct_tests_01.dct_iv8_1d_i.dsp_cec_1
	dct_tests_01.dct_iv8_1d_i.dsp_post_add_1		dct_tests_01.dct_iv8_1d_i.dsp_post_add_1
	dct_tests_01.dct_iv8_1d_i.dsp_accum_1		dct_tests_01.dct_iv8_1d_i.dsp_accum_1
	@22		@22
	@@ -238,7 +277,305 @@ dct_tests_01.dct_iv8_1d_i.pre2_start_out
	dct_tests_01.dct_iv8_1d_i.rst		dct_tests_01.dct_iv8_1d_i.rst
	dct_tests_01.dct_iv8_1d_i.run_in		dct_tests_01.dct_iv8_1d_i.run_in
	dct_tests_01.dct_iv8_1d_i.run_out		dct_tests_01.dct_iv8_1d_i.run_out
	@1000200		@1401200
	-dct_iv8_1d		-dct_iv8_1d
			@800200
			-st22d_test
			@28
			dct_tests_01.CLK
			dct_tests_01.RST
			[color] 2
			dct_tests_01.start
			[color] 2
			dct_tests_01.start2
			@c00022
			dct_tests_01.x_in_2d[23:0]
			@28
			(0)dct_tests_01.x_in_2d[23:0]
			(1)dct_tests_01.x_in_2d[23:0]
			(2)dct_tests_01.x_in_2d[23:0]
			(3)dct_tests_01.x_in_2d[23:0]
			(4)dct_tests_01.x_in_2d[23:0]
			(5)dct_tests_01.x_in_2d[23:0]
			(6)dct_tests_01.x_in_2d[23:0]
			(7)dct_tests_01.x_in_2d[23:0]
			(8)dct_tests_01.x_in_2d[23:0]
			(9)dct_tests_01.x_in_2d[23:0]
			(10)dct_tests_01.x_in_2d[23:0]
			(11)dct_tests_01.x_in_2d[23:0]
			(12)dct_tests_01.x_in_2d[23:0]
			(13)dct_tests_01.x_in_2d[23:0]
			(14)dct_tests_01.x_in_2d[23:0]
			(15)dct_tests_01.x_in_2d[23:0]
			(16)dct_tests_01.x_in_2d[23:0]
			(17)dct_tests_01.x_in_2d[23:0]
			(18)dct_tests_01.x_in_2d[23:0]
			(19)dct_tests_01.x_in_2d[23:0]
			(20)dct_tests_01.x_in_2d[23:0]
			(21)dct_tests_01.x_in_2d[23:0]
			(22)dct_tests_01.x_in_2d[23:0]
			(23)dct_tests_01.x_in_2d[23:0]
			@1401200
			-group_end
			@c08420
			dct_tests_01.x_in_2d[23:0]
			@28
			(0)dct_tests_01.x_in_2d[23:0]
			(1)dct_tests_01.x_in_2d[23:0]
			(2)dct_tests_01.x_in_2d[23:0]
			(3)dct_tests_01.x_in_2d[23:0]
			(4)dct_tests_01.x_in_2d[23:0]
			(5)dct_tests_01.x_in_2d[23:0]
			(6)dct_tests_01.x_in_2d[23:0]
			(7)dct_tests_01.x_in_2d[23:0]
			(8)dct_tests_01.x_in_2d[23:0]
			(9)dct_tests_01.x_in_2d[23:0]
			(10)dct_tests_01.x_in_2d[23:0]
			(11)dct_tests_01.x_in_2d[23:0]
			(12)dct_tests_01.x_in_2d[23:0]
			(13)dct_tests_01.x_in_2d[23:0]
			(14)dct_tests_01.x_in_2d[23:0]
			(15)dct_tests_01.x_in_2d[23:0]
			(16)dct_tests_01.x_in_2d[23:0]
			(17)dct_tests_01.x_in_2d[23:0]
			(18)dct_tests_01.x_in_2d[23:0]
			(19)dct_tests_01.x_in_2d[23:0]
			(20)dct_tests_01.x_in_2d[23:0]
			(21)dct_tests_01.x_in_2d[23:0]
			(22)dct_tests_01.x_in_2d[23:0]
			(23)dct_tests_01.x_in_2d[23:0]
			@1401200
			-group_end
			@28
			dct_tests_01.pre_busy_2d
			dct_tests_01.pre_last_in_2d
			dct_tests_01.pre_first_out_2d
			dct_tests_01.dv_2d
			@22
			dct_tests_01.d_out_2d[23:0]
			@28
			dct_tests_01.dv_2dr
			@22
			dct_tests_01.d_out_2dr[23:0]
			@8420
			dct_tests_01.d_out_2dr[23:0]
			@200
			-
			@800200
			-dct_iv_8x8
			@28
			dct_tests_01.dct_iv_8x8_i.clk
			dct_tests_01.dct_iv_8x8_i.start
			dct_tests_01.dct_iv_8x8_i.pre_last_in
			dct_tests_01.dct_iv_8x8_i.pre_busy
			dct_tests_01.dct_iv_8x8_i.x_run
			@c00022
			dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
			@28
			(0)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
			(1)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
			(2)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
			(3)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
			(4)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
			(5)dct_tests_01.dct_iv_8x8_i.x_wa[5:0]
			@1401200
			-group_end
			@28
			dct_tests_01.dct_iv_8x8_i.dcth_phin_start
			@22
			dct_tests_01.dct_iv_8x8_i.dcth_phin_run
			@c00022
			dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
			@28
			(0)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
			(1)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
			(2)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
			(3)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
			(4)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
			(5)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
			(6)dct_tests_01.dct_iv_8x8_i.dcth_phin[6:0]
			@1401200
			-group_end
			@22
			dct_tests_01.dct_iv_8x8_i.x_ra0[2:0]
			dct_tests_01.dct_iv_8x8_i.x_ra1[2:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dcth_en0
			dct_tests_01.dct_iv_8x8_i.dcth_start_0_r
			@22
			dct_tests_01.dct_iv_8x8_i.dcth_xin0[23:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dcth_en_out0
			@22
			dct_tests_01.dct_iv_8x8_i.dcth_dout0[24:0]
			dct_tests_01.dct_iv_8x8_i.dcth_yindex0[2:0]
			@200
			-
			@28
			dct_tests_01.dct_iv_8x8_i.dcth_en1
			dct_tests_01.dct_iv_8x8_i.dcth_start_1_r
			@22
			dct_tests_01.dct_iv_8x8_i.dcth_xin1[23:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dcth_en_out1
			@22
			dct_tests_01.dct_iv_8x8_i.dcth_dout1[24:0]
			dct_tests_01.dct_iv_8x8_i.dcth_yindex1[2:0]
			@200
			-
			@22
			dct_tests_01.dct_iv_8x8_i.transpose_start
			@28
			dct_tests_01.dct_iv_8x8_i.transpose_in_run
			@22
			dct_tests_01.dct_iv_8x8_i.transpose_w_page[1:0]
			[color] 3
			dct_tests_01.dct_iv_8x8_i.transpose_cntr[6:0]
			@28
			dct_tests_01.dct_iv_8x8_i.transpose_wa_decr
			@22
			dct_tests_01.dct_iv_8x8_i.transpose_wa_low[2:0]
			dct_tests_01.dct_iv_8x8_i.transpose_wa_high[4:0]
			dct_tests_01.dct_iv_8x8_i.transpose_wa[7:0]
			@28
			dct_tests_01.dct_iv_8x8_i.transpose_we
			@22
			[color] 2
			dct_tests_01.dct_iv_8x8_i.transpose_debug_di[7:0]
			@28
			dct_tests_01.dct_iv_8x8_i.transpose_out_start
			@800022
			dct_tests_01.dct_iv_8x8_i.transpose_out_run[2:0]
			@28
			(0)dct_tests_01.dct_iv_8x8_i.transpose_out_run[2:0]
			(1)dct_tests_01.dct_iv_8x8_i.transpose_out_run[2:0]
			(2)dct_tests_01.dct_iv_8x8_i.transpose_out_run[2:0]
			@1001200
			-group_end
			@c00028
			dct_tests_01.dct_iv_8x8_i.transpose_r_page[1:0]
			@28
			(0)dct_tests_01.dct_iv_8x8_i.transpose_r_page[1:0]
			(1)dct_tests_01.dct_iv_8x8_i.transpose_r_page[1:0]
			@1401200
			-group_end
			@c00022
			dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
			@28
			(0)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
			(1)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
			(2)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
			(3)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
			(4)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
			(5)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
			(6)dct_tests_01.dct_iv_8x8_i.transpose_rcntr[6:0]
			@1401200
			-group_end
			@22
			dct_tests_01.dct_iv_8x8_i.transpose_ra[7:0]
			dct_tests_01.dct_iv_8x8_i.transpose_reg[24:0]
			@8420
			dct_tests_01.dct_iv_8x8_i.transpose_out[24:0]
			@22
			dct_tests_01.dct_iv_8x8_i.transpose_out[24:0]
			dct_tests_01.dct_iv_8x8_i.transpose_debug_reg[7:0]
			dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
			@8022
			dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
			@22
			dct_tests_01.dct_iv_8x8_i.t_wa[3:0]
			@28
			dct_tests_01.dct_iv_8x8_i.t_we0
			dct_tests_01.dct_iv_8x8_i.t_we1
			dct_tests_01.dct_iv_8x8_i.dctv_start_0_r
			dct_tests_01.dct_iv_8x8_i.dctv_start_1_r
			dct_tests_01.dct_iv_8x8_i.dctv_en0
			dct_tests_01.dct_iv_8x8_i.dctv_en1
			dct_tests_01.dct_iv_8x8_i.dctv_phin_start
			dct_tests_01.dct_iv_8x8_i.dctv_phin_run
			@c00022
			[color] 2
			dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
			@28
			(0)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
			(1)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
			(2)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
			(3)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
			(4)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
			(5)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
			(6)dct_tests_01.dct_iv_8x8_i.dctv_phin[6:0]
			@1401200
			-group_end
			@8022
			dct_tests_01.dct_iv_8x8_i.t_ra0[2:0]
			dct_tests_01.dct_iv_8x8_i.t_ra1[2:0]
			@22
			dct_tests_01.dct_iv_8x8_i.dctv_xin0[24:0]
			@8420
			dct_tests_01.dct_iv_8x8_i.dctv_xin0[24:0]
			@22
			dct_tests_01.dct_iv_8x8_i.dctv_xin1[24:0]
			dct_tests_01.dct_iv_8x8_i.transpose_debug_out[7:0]
			dct_tests_01.dct_iv_8x8_i.dctv_debug_xin0[7:0]
			@8022
			dct_tests_01.dct_iv_8x8_i.dctv_debug_xin0[7:0]
			@22
			dct_tests_01.dct_iv_8x8_i.dctv_debug_xin1[7:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dctv_start_0_r
			dct_tests_01.dct_iv_8x8_i.dctv_start_1_r
			dct_tests_01.dct_iv_8x8_i.dctv_en0
			dct_tests_01.dct_iv_8x8_i.dctv_en1
			dct_tests_01.dct_iv_8x8_i.dctv_en_out0
			dct_tests_01.dct_iv_8x8_i.dctv_en_out1
			@c00022
			dct_tests_01.dct_iv_8x8_i.dctv_yindex0[2:0]
			@28
			(0)dct_tests_01.dct_iv_8x8_i.dctv_yindex0[2:0]
			(1)dct_tests_01.dct_iv_8x8_i.dctv_yindex0[2:0]
			(2)dct_tests_01.dct_iv_8x8_i.dctv_yindex0[2:0]
			@1401200
			-group_end
			@22
			dct_tests_01.dct_iv_8x8_i.dctv_yindex1[2:0]
			dct_tests_01.dct_iv_8x8_i.dctv_dout0[24:0]
			dct_tests_01.dct_iv_8x8_i.dctv_dout1[24:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dctv_out_start
			dct_tests_01.dct_iv_8x8_i.dctv_out_run
			@22
			dct_tests_01.dct_iv_8x8_i.dctv_out_cntr[6:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dctv_out_we_1
			dct_tests_01.dct_iv_8x8_i.dctv_out_sel
			@22
			dct_tests_01.dct_iv_8x8_i.dctv_out_wa_1[3:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dctv_out_start_1
			dct_tests_01.dct_iv_8x8_i.dctv_out_run_1
			@22
			dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1[6:0]
			dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1_w[3:0]
			dct_tests_01.dct_iv_8x8_i.dctv_out_reg_1[23:0]
			dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_1[2:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dctv_out_we_2
			@22
			dct_tests_01.dct_iv_8x8_i.dctv_out_wa_2[1:0]
			@28
			dct_tests_01.dct_iv_8x8_i.dctv_out_run_2
			@22
			dct_tests_01.dct_iv_8x8_i.dctv_out_ra_2[6:0]
			dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]
			dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_2[2:0]
			@1000200
			-dct_iv_8x8
			@800200
			-dct_iv_8x8r
			@200
			-
			@1000200
			-dct_iv_8x8r
			-st22d_test
	[pattern_trace] 1		[pattern_trace] 1
	[pattern_trace] 0		[pattern_trace] 0

dsp/dct_iv.ods

+20.3 KiB (96.1 KiB)

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dsp/dct_iv8_1d.v

+24 −2

Original line number	Original line	Diff line number	Diff line
	@@ -71,7 +71,9 @@ module dct_iv8_1d#(
	output [OUT_WIDTH -1:0] dout,		output [OUT_WIDTH -1:0] dout,
	output reg pre2_start_out, // 2 clock cycle before Y0 output, full dout sequence		output reg pre2_start_out, // 2 clock cycle before Y0 output, full dout sequence
	// start_out-x-Y0-x-Y7-x-Y4-x-Y3-x-Y1-x-Y6-x-Y2-x-Y5		// start_out-x-Y0-x-Y7-x-Y4-x-Y3-x-Y1-x-Y6-x-Y2-x-Y5
	output reg en_out // valid at the same time slot as pre2_start_out (goes active with pre2_start_out)		output en_out, // valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 1 ahead of data
			output reg [2:0] y_index // for simulation - valid with dout - index of the data output

	);		);
	// X6-X7-X5-X2-X1-X3-X0-X4--X5-X1-X2--X4-X7-*		// X6-X7-X5-X2-X1-X3-X0-X4--X5-X1-X2--X4-X7-*
	// X2-X7-X3-X4-X5-X6-X0-X1--X3-X5-X4--X1-X7-*		// X2-X7-X3-X4-X5-X6-X0-X1--X3-X5-X4--X1-X7-*
	@@ -132,6 +134,9 @@ module dct_iv8_1d#(
	reg run_in; // receiving input data		reg run_in; // receiving input data
	reg restart; // restarting next block if en was active at phase=14;		reg restart; // restarting next block if en was active at phase=14;
	reg run_out; // running output data		reg run_out; // running output data
			reg en_out_r;

			assign en_out = en_out_r;

	assign dsp_ain_2 = dsp_p_1 [STAGE1_RSHIFT +: A_WIDTH];		assign dsp_ain_2 = dsp_p_1 [STAGE1_RSHIFT +: A_WIDTH];

	@@ -147,6 +152,23 @@ module dct_iv8_1d#(
	wire din_zero = ~(\|d_in);		wire din_zero = ~(\|d_in);
	assign dsp_cin_1 = {{P_WIDTH-WIDTH-COSINE_SHIFT{d_in[WIDTH-1]}},d_in,~d_in[WIDTH-1]^din_zero,{COSINE_SHIFT-1{d_in[WIDTH-1]}}};		assign dsp_cin_1 = {{P_WIDTH-WIDTH-COSINE_SHIFT{d_in[WIDTH-1]}},d_in,~d_in[WIDTH-1]^din_zero,{COSINE_SHIFT-1{d_in[WIDTH-1]}}};

			always @ (posedge clk) begin
			if (en_out_r) begin
			case (phase_cnt[3:1])
			3'h0: y_index <= 7;
			3'h1: y_index <= 4;
			3'h2: y_index <= 3;
			3'h3: y_index <= 1;
			3'h4: y_index <= 6;
			3'h5: y_index <= 2;
			3'h6: y_index <= 5;
			3'h7: y_index <= 0;
			endcase
			end else begin
			y_index <= 'bx;
			end
			end


	//register files		//register files
	assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra];		assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra];
	@@ -173,7 +195,7 @@ module dct_iv8_1d#(

	pre2_start_out <= run_out && (phase_cnt == 14);		pre2_start_out <= run_out && (phase_cnt == 14);

	en_out <= run_out && !phase_cnt[0];		en_out_r <= run_out && !phase_cnt[0];

	// Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand		// Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand
	case (phase_cnt)		case (phase_cnt)

dsp/dct_iv_8x8.v

0 → 100644

+609 −0

File added.

Preview size limit exceeded, changes collapsed.

dsp/dct_tests_01.tf

+114 −27

Original line number	Original line	Diff line number	Diff line
	@@ -40,7 +40,7 @@
	`timescale 1ns/1ps		`timescale 1ns/1ps
	// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder		// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
	// will reduce needed resources		// will reduce needed resources
	//`define DCT_INPUT_UNITY		`define DCT_INPUT_UNITY
	module dct_tests_01 ();		module dct_tests_01 ();
	// parameter fstname="dct_tests_01.fst";		// parameter fstname="dct_tests_01.fst";
	`ifdef IVERILOG		`ifdef IVERILOG
	@@ -65,7 +65,12 @@ module dct_tests_01 ();
	parameter WIDTH = 24; // input data width		parameter WIDTH = 24; // input data width
	// parameter OUT_WIDTH = 16; // output data width		// parameter OUT_WIDTH = 16; // output data width
	parameter OUT_WIDTH = 24; // output data width		parameter OUT_WIDTH = 24; // output data width
			parameter TRANSPOSE_WIDTH = 25; // width of the transpose memory (intermediate results)
	parameter OUT_RSHIFT = 3; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)		parameter OUT_RSHIFT = 3; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
			parameter OUT_RSHIFT2 = 0; // overall right shift for the second (vertical) pass

			parameter DCT_GAP = 16; // between runs


	reg RST = 1'b1;		reg RST = 1'b1;
	reg CLK = 1'b0;		reg CLK = 1'b0;
	@@ -83,11 +88,13 @@ module dct_tests_01 ();

	wire x_we = !phase_in[3] && run_in;		wire x_we = !phase_in[3] && run_in;
	reg [WIDTH-1:0] x_in;		reg [WIDTH-1:0] x_in;
			reg [WIDTH-1:0] x_in_2d;
	reg [WIDTH-1:0] x_out;		reg [WIDTH-1:0] x_out;
	reg [WIDTH-1:0] x_ram[0:7];		reg [WIDTH-1:0] x_ram[0:7];
	wire [WIDTH-1:0] x_out_w = x_ram[x_ra];		wire [WIDTH-1:0] x_out_w = x_ram[x_ra];

	reg start = 0;		reg start = 0;
			reg start2 = 0; // second start for 2d

	wire [OUT_WIDTH-1:0] y_dct; // S uppressThisWarning VEditor - simulation only		wire [OUT_WIDTH-1:0] y_dct; // S uppressThisWarning VEditor - simulation only
	wire pre2_start_out; // S uppressThisWarning VEditor - simulation only		wire pre2_start_out; // S uppressThisWarning VEditor - simulation only
	@@ -103,7 +110,22 @@ module dct_tests_01 ();
	wire signed [OUT_WIDTH-1:0] y_out = y_ram[y_ra]; // SuppressThisWarning VEditor - simulation only		wire signed [OUT_WIDTH-1:0] y_out = y_ram[y_ra]; // SuppressThisWarning VEditor - simulation only
	reg signed [WIDTH-1:0] data_in[0:63];		reg signed [WIDTH-1:0] data_in[0:63];
	reg signed [OUT_WIDTH-1:0] data_out[0:63];		reg signed [OUT_WIDTH-1:0] data_out[0:63];
	integer i,j;
			reg signed [WIDTH-1:0] d_in;
			wire pre_last_in_2d;
			wire pre_first_out_2d;
			wire pre_busy_2d;
			wire dv_2d;
			wire signed [OUT_WIDTH-1:0] d_out_2d;

			wire pre_last_in_2dr;
			wire pre_first_out_2dr;
			wire pre_busy_2dr;
			wire dv_2dr;
			wire signed [OUT_WIDTH-1:0] d_out_2dr;


			integer i,j, i1, j1;
	initial begin		initial begin
	for (i=0; i<64; i=i+1) begin		for (i=0; i<64; i=i+1) begin
	`ifdef DCT_INPUT_UNITY		`ifdef DCT_INPUT_UNITY
	@@ -147,23 +169,6 @@ module dct_tests_01 ();
	if (&i[2:0]) repeat (8) @(posedge CLK);		if (&i[2:0]) repeat (8) @(posedge CLK);
	end		end
	#1 x_in = 0;		#1 x_in = 0;
	/*
	// running 'one' - just make a period == 17
	repeat (7) begin
	@(posedge CLK);
	#1 x_in = {2'b1,{WIDTH-2{1'b0}}}; // >>x_wa;
	@(posedge CLK);
	#1 x_in = 0;
	repeat (15) @(posedge CLK); // 16+1= 17, non-zero will go through all of the 8 x[i]
	end
	begin
	@(posedge CLK);
	#1 x_in = {2'b1,{WIDTH-2{1'b0}}};
	@(posedge CLK);
	#1 x_in = 0;
	en_x = 0;
	end
	*/
	repeat (64) @(posedge CLK);		repeat (64) @(posedge CLK);

	$display("");		$display("");
	@@ -173,9 +178,45 @@ module dct_tests_01 ();
	data_out[i+4],data_out[i+5],data_out[i+6],data_out[i+7]);		data_out[i+4],data_out[i+5],data_out[i+6],data_out[i+7]);
	end		end

			// repeat (64) @(posedge CLK);
			// $finish;
			end

			initial begin
			wait (!RST);
			while (!start) begin
			@(posedge CLK);
			#1;
			end
			for (i1 = 0; i1 < 64; i1 = i1+1) begin
			@(posedge CLK);
			#1;
			x_in_2d = data_in[i1];
			if (i1 == 63) start2 = 1;
			end
			for (i1 = 0; i1 < 64; i1 = i1+1) begin
			@(posedge CLK);
			#1;
			start2 = 0;
			x_in_2d = data_in[i1];
			end

			repeat (DCT_GAP) @(posedge CLK);
			#1;
			start2 = 1;
			for (i1 = 0; i1 < 64; i1 = i1+1) begin
			@(posedge CLK);
			#1;
			start2 = 0;
			x_in_2d = data_in[63-i1];
			end

			repeat (300) @(posedge CLK);
	$finish;		$finish;

	end		end


	initial j = 0;		initial j = 0;
	always @ (posedge CLK) begin		always @ (posedge CLK) begin
	if (y_dv) begin		if (y_dv) begin
	@@ -285,7 +326,53 @@ module dct_tests_01 ();
	.start (start), // input		.start (start), // input
	.dout (y_dct), // output[15:0]		.dout (y_dct), // output[15:0]
	.pre2_start_out (pre2_start_out), // output reg		.pre2_start_out (pre2_start_out), // output reg
	.en_out (en_out) // output reg		.en_out (en_out), // output reg
			.y_index () // output[2:0] reg
			);



			dct_iv_8x8 #(
			.INPUT_WIDTH (WIDTH),
			.OUT_WIDTH (OUT_WIDTH),
			.OUT_RSHIFT1 (OUT_RSHIFT),
			.OUT_RSHIFT2 (OUT_RSHIFT2),
			.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
			.DSP_B_WIDTH (18),
			.DSP_A_WIDTH (25),
			.DSP_P_WIDTH (48)
			) dct_iv_8x8_i (
			.clk (CLK), // input
			.rst (RST), // input
			.start (start \|\| start2), // input
			.xin (x_in_2d), // input[24:0] signed
			.pre_last_in (pre_last_in_2d), // output reg
			.pre_first_out (pre_first_out_2d), // output
			.dv (dv_2d), // output
			.d_out (d_out_2d), // output[24:0] signed
			.pre_busy (pre_busy_2d) // output reg
	);		);

			dct_iv_8x8 #(
			.INPUT_WIDTH (WIDTH),
			.OUT_WIDTH (OUT_WIDTH),
			.OUT_RSHIFT1 (OUT_RSHIFT),
			.OUT_RSHIFT2 (OUT_RSHIFT2),
			.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
			.DSP_B_WIDTH (18),
			.DSP_A_WIDTH (25),
			.DSP_P_WIDTH (48)
			) dct_iv_8x8r_i (
			.clk (CLK), // input
			.rst (RST), // input
			.start (pre_first_out_2d), // input
			.xin (d_out_2d), // input[24:0] signed
			.pre_last_in (pre_last_in_2dr), // output reg
			.pre_first_out (pre_first_out_2dr), // output
			.dv (dv_2dr), // output
			.d_out (d_out_2dr), // output[24:0] signed
			.pre_busy (pre_busy_2dr) // output reg
			);


	endmodule		endmodule

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