converting gamma tables to multi-sensor for each sesnor port, adding... (0fec497c) · Commits · Elphel / x393

sensor/sens_gamma.v

+162 −57

Original line number	Original line	Diff line number	Diff line
	@@ -21,12 +21,17 @@
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module sens_gamma #(		module sens_gamma #(
			parameter SENS_GAMMA_NUM_CHN = 3, // number of subchannels for his sensor ports (1..4)
			parameter SENS_GAMMA_BUFFER = 0, // 1 - use "shadow" table for clean switching, 0 - single table per channel
	parameter SENS_GAMMA_ADDR = 'h338,		parameter SENS_GAMMA_ADDR = 'h338,
	parameter SENS_GAMMA_ADDR_MASK = 'h3fc,		parameter SENS_GAMMA_ADDR_MASK = 'h3fc,
	parameter SENS_GAMMA_CTRL = 'h0,		parameter SENS_GAMMA_CTRL = 'h0,
			parameter SENS_GAMMA_ADDR_DATA = 'h1, // bit 20 ==1 - table address, bit 20==0 - table data (18 bits)
			parameter SENS_GAMMA_HEIGHT01 = 'h2, // bits [15:0] - height minus 1 of image 0, [31:16] - height-1 of image1
			parameter SENS_GAMMA_HEIGHT2 = 'h3, // bits [15:0] - height minus 1 of image 2 ( no need for image 3)
	// parameter SENS_GAMMA_STATUS = 'h1,		// parameter SENS_GAMMA_STATUS = 'h1,
	parameter SENS_GAMMA_TADDR = 'h2,		// parameter SENS_GAMMA_TADDR = 'h2,
	parameter SENS_GAMMA_TDATA = 'h3, // 1.. 2^16, 0 - use HACT		// parameter SENS_GAMMA_TDATA = 'h3, // 1.. 2^16, 0 - use HACT????
	// parameter SENS_GAMMA_STATUS_REG = 'h32		// parameter SENS_GAMMA_STATUS_REG = 'h32
	parameter SENS_GAMMA_MODE_WIDTH = 5, // does not include trig		parameter SENS_GAMMA_MODE_WIDTH = 5, // does not include trig
	parameter SENS_GAMMA_MODE_BAYER = 0,		parameter SENS_GAMMA_MODE_BAYER = 0,
	@@ -62,11 +67,6 @@ module sens_gamma #(
	input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port		input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
	input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3		input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
	input cmd_stb // strobe (with first byte) for the command a/d		input cmd_stb // strobe (with first byte) for the command a/d
	/*
	output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
	output status_rq, // input request to send status downstream
	input status_start // Acknowledge of the first status packet byte (address)
	*/
	);		);
	wire [1:0] cmd_a;		wire [1:0] cmd_a;
	wire [31:0] cmd_data;		wire [31:0] cmd_data;
	@@ -75,14 +75,34 @@ module sens_gamma #(
	wire set_ctrl_w;		wire set_ctrl_w;
	wire set_taddr_w;		wire set_taddr_w;
	wire set_tdata_w;		wire set_tdata_w;
	reg [10:0] taddr;		wire set_height01_w;
			wire set_height2_w;
			reg set_tdata_r;
			reg [3:0] set_tdata_ram;
			reg [17:0] tdata;
			// wire set_taddr_data_w;
			reg [12:0] taddr; // to high bits - select channnel (in buffered mode), in nion-buffered - 1 bit less, only 10 bits each table
	reg [SENS_GAMMA_MODE_WIDTH-1:0] mode=0;		reg [SENS_GAMMA_MODE_WIDTH-1:0] mode=0;
	reg [SENS_GAMMA_MODE_WIDTH-1:0] mode_mclk=0;		reg [SENS_GAMMA_MODE_WIDTH-1:0] mode_mclk=0;

			reg [15:0] height0_m1; // set @ posedge mclk, used at pclk, but should be OK
			reg [15:0] height1_m1;
			reg [15:0] height2_m1;

	wire [1:0] bayer;		wire [1:0] bayer;
	wire table_page; //part of the mode register		wire table_page; //part of the mode register
	wire en_input;		wire en_input;
	wire repet_mode;		wire repet_mode;

			reg [1:0] sensor_subchn; // select sensor from the multiplexed ones
			reg sof_r;
			reg inc_line;
			reg [15:0] line_cntr; // count image lines to switch to next subchannels
			wire [3:0] table_re;
			reg [3:0] table_regen;
			wire [1:0] ram_chn;
			reg [1:0] ram_chn_d;
			reg [1:0] ram_chn_d2;

	reg bayer_nset; // set color to bayer (start of frame up to first hact) when zero		reg bayer_nset; // set color to bayer (start of frame up to first hact) when zero
	wire sync_bayer; // at the beginning of the line - sync color to bayer		wire sync_bayer; // at the beginning of the line - sync color to bayer
	@@ -117,28 +137,41 @@ module sens_gamma #(
	reg frame_run;		reg frame_run;
	wire trig_soft;		wire trig_soft;
	wire trig;		wire trig;
			wire [10:0] table_raddr;
			wire [17:0] table_rdata0;
			wire [17:0] table_rdata1;
			wire [17:0] table_rdata2;
			wire [17:0] table_rdata3;
			wire [17:0] table_rdata;

	assign pxd_out = cdata;		assign pxd_out = cdata;
	assign hact_out = hact_d[3];		assign hact_out = hact_d[3];

	assign set_ctrl_w = cmd_we && (cmd_a == SENS_GAMMA_CTRL );		assign set_ctrl_w = cmd_we && (cmd_a == SENS_GAMMA_CTRL );
	// assign set_status_w = cmd_we && (cmd_a == SENS_GAMMA_STATUS );		// assign set_status_w = cmd_we && (cmd_a == SENS_GAMMA_STATUS );
	assign set_taddr_w = cmd_we && (cmd_a == SENS_GAMMA_TADDR );		// assign set_taddr_w = cmd_we && (cmd_a == SENS_GAMMA_TADDR );
	assign set_tdata_w = cmd_we && (cmd_a == SENS_GAMMA_TDATA );		// assign set_tdata_w = cmd_we && (cmd_a == SENS_GAMMA_TDATA );
			assign set_taddr_w = cmd_we && (cmd_a == SENS_GAMMA_ADDR_DATA ) && cmd_data[20];
	/*		assign set_tdata_w = cmd_we && (cmd_a == SENS_GAMMA_ADDR_DATA ) && !cmd_data[20];
	assign bayer = mode[1:0];
	assign table_page = mode[2]; // TODO: re-assign?		assign set_height01_w = cmd_we && (cmd_a == SENS_GAMMA_HEIGHT01 );
	assign en_input = mode[3];		assign set_height2_w = cmd_we && (cmd_a == SENS_GAMMA_HEIGHT2 );
	assign repet_mode = mode[4]; // TODO: re-assign?
	parameter SENS_GAMMA_MODE_WIDTH = 5, // does not include trig		assign ram_chn= SENS_GAMMA_BUFFER ? sensor_subchn: {1'b0, sensor_subchn[1]};
	parameter SENS_GAMMA_MODE_BAYER = 0,		assign table_re= {4{hact_in}} & { ram_chn[1] & ram_chn[0],
	parameter SENS_GAMMA_MODE_PAGE = 2,		ram_chn[1] & ~ram_chn[0],
	parameter SENS_GAMMA_MODE_EN = 3,		~ram_chn[1] & ram_chn[0],
	parameter SENS_GAMMA_MODE_REPET = 4,		~ram_chn[1] & ~ram_chn[0]};
	parameter SENS_GAMMA_MODE_TRIG = 5		assign table_raddr= SENS_GAMMA_BUFFER ?
			{table_page,color[1:0],pxd_in[15:8]}:
			{ram_chn[0],color[1:0],pxd_in[15:8]};

			// TODO: register data
			assign table_rdata= ram_chn_d2[1]?
			(ram_chn_d2[0]?table_rdata3:table_rdata2):
			(ram_chn_d2[0]?table_rdata1:table_rdata0);
			assign {table_diff_w[7:0],table_base_w[9:0]} = table_rdata;

	*/
	assign bayer = mode[SENS_GAMMA_MODE_BAYER +: 2];		assign bayer = mode[SENS_GAMMA_MODE_BAYER +: 2];
	assign table_page = mode[SENS_GAMMA_MODE_PAGE]; // TODO: re-assign?		assign table_page = mode[SENS_GAMMA_MODE_PAGE]; // TODO: re-assign?
	assign en_input = mode[SENS_GAMMA_MODE_EN];		assign en_input = mode[SENS_GAMMA_MODE_EN];
	@@ -151,20 +184,40 @@ module sens_gamma #(
	assign sof_masked= sof_in && (pend_trig \|\| repet_mode) && en_input;		assign sof_masked= sof_in && (pend_trig \|\| repet_mode) && en_input;
	assign trig = trig_in \|\| trig_soft;		assign trig = trig_in \|\| trig_soft;
	always @ (posedge rst or posedge mclk) begin		always @ (posedge rst or posedge mclk) begin
			if (rst) tdata <= 0;
			else if (set_taddr_w) tdata <= cmd_data[17:0];

			if (rst) set_tdata_r <= 0;
			else set_tdata_r <= set_tdata_w;

	if (rst) taddr <= 0;		if (rst) taddr <= 0;
	else if (set_taddr_w) taddr <= cmd_data[10:0];		else if (set_taddr_w) taddr <= cmd_data[12:0];
	else if (set_tdata_w) taddr <= taddr + 1;		else if (set_tdata_r) taddr <= taddr + 1;

	if (rst) mode_mclk <= 0;		if (rst) mode_mclk <= 0;
	else if (set_ctrl_w) mode_mclk <= cmd_data[SENS_GAMMA_MODE_WIDTH-1:0];		else if (set_ctrl_w) mode_mclk <= cmd_data[SENS_GAMMA_MODE_WIDTH-1:0];

			if (rst) set_tdata_ram <=0;
			else set_tdata_ram <= {4{set_tdata_w}} &
			{ taddr[12] & taddr[11],
			taddr[12] & ~taddr[11],
			~taddr[12] & taddr[11],
			~taddr[12] & ~taddr[11]};
			if (rst) height0_m1 <= 0;
			else if (set_height01_w) height0_m1 <= cmd_data[15:0];

			if (rst) height1_m1 <= 0;
			else if (set_height01_w) height1_m1 <= cmd_data[31:16];

			if (rst) height2_m1 <= 0;
			else if (set_height2_w) height2_m1 <= cmd_data[15:0];


	end		end
	// reg vblank; // from sof to first hact
	// reg pend_trig; // pending trigger (if trig came outside of vblank
	//SENS_GAMMA_MODE_TRIG
	always @ (posedge rst or posedge pclk) begin		always @ (posedge rst or posedge pclk) begin
	if (rst) begin		if (rst) begin
	mode <= 0;		mode <= 0;
	// hact_m <= 0;
	// en_d <= 0;
	hact_d[3:0] <= 0;		hact_d[3:0] <= 0;
	bayer_nset <= 0;		bayer_nset <= 0;
	bayer0_latched <= 0;		bayer0_latched <= 0;
	@@ -176,8 +229,6 @@ module sens_gamma #(

	end else begin		end else begin
	mode <= mode_mclk;		mode <= mode_mclk;
	// hact_m <= hact_in && en;
	// en_d <= en;
	hact_d[3:0] <= {hact_d[2:0],hact_in};		hact_d[3:0] <= {hact_d[2:0],hact_in};
	bayer_nset <= frame_run && (bayer_nset \|\| hact_in);		bayer_nset <= frame_run && (bayer_nset \|\| hact_in);
	bayer0_latched <= bayer_nset? bayer0_latched:bayer[0];		bayer0_latched <= bayer_nset? bayer0_latched:bayer[0];
	@@ -200,6 +251,21 @@ module sens_gamma #(
	{{4{table_diff_w[6]}},table_diff_w[6:0]};		{{4{table_diff_w[6]}},table_diff_w[6:0]};
	table_mult_r[17:7] <= table_mult[17:7];		table_mult_r[17:7] <= table_mult[17:7];
	table_base_r[ 9:0] <= table_base[ 9:0];		table_base_r[ 9:0] <= table_base[ 9:0];

			table_regen <= table_re;
			ram_chn_d <= ram_chn;
			ram_chn_d2 <= ram_chn_d;

			inc_line <= hact_d[0] && !hact_in && (sensor_subchn < SENS_GAMMA_NUM_CHN);

			sof_r <= sof_in;

			if (sof_r) sensor_subchn <= 0;
			else if (inc_line && (line_cntr == 0)) sensor_subchn <= sensor_subchn+1;

			if (sof_r) line_cntr <= height0_m1;
			else if (inc_line && (line_cntr == 0)) line_cntr <= (sensor_subchn ==0)? height1_m1: height2_m1;

	end		end


	@@ -218,21 +284,7 @@ module sens_gamma #(
	.data (cmd_data), // output[31:0]		.data (cmd_data), // output[31:0]
	.we (cmd_we) // output		.we (cmd_we) // output
	);		);
	/*
	status_generate #(
	.STATUS_REG_ADDR(SENS_GAMMA_STATUS_REG),
	.PAYLOAD_BITS(15) // STATUS_PAYLOAD_BITS)
	) status_generate_sens_io_i (
	.rst (rst), // input
	.clk (mclk), // input
	.we (set_status_w), // input
	.wd (cmd_data[7:0]), // input[7:0]
	.status (status), // input[25:0]
	.ad (status_ad), // output[7:0]
	.rq (status_rq), // output
	.start (status_start) // input
	);
	*/
	dly_16 #(		dly_16 #(
	.WIDTH(8)		.WIDTH(8)
	) dly_16_pxd_i (		) dly_16_pxd_i (
	@@ -260,25 +312,78 @@ module sens_gamma #(
	.out_pulse (trig_soft),		.out_pulse (trig_soft),
	.busy ());		.busy ());

			// channel0 (or 0,1 - always present)
			ramp_var_w_var_r #(
			.REGISTERS (1), // try to delay i2c_byte_start by one more cycle
			.LOG2WIDTH_WR (4),
			.LOG2WIDTH_RD (4),
			.DUMMY (0)
			) gamma_table0_i (
			.rclk (pclk), // input
			.raddr (table_raddr), // input[11:0]
			.ren (table_re[0]), // input TODO: add "en"?
			.regen (table_regen[0]), // input
			.data_out (table_rdata0), // output[7:0]
			.wclk (mclk), // input
			.waddr (taddr[10:0]), // input[9:0]
			.we (set_tdata_ram[0]), // input
			.web (8'hff), // input[7:0]
			.data_in (tdata) // input[31:0]
			);
			// Optionally generated/ replaced by dummy
			ramp_var_w_var_r #(
			.REGISTERS (1), // try to delay i2c_byte_start by one more cycle
			.LOG2WIDTH_WR (4),
			.LOG2WIDTH_RD (4),
			.DUMMY (!((SENS_GAMMA_NUM_CHN > 1) && ((SENS_GAMMA_NUM_CHN > 2) \|\| SENS_GAMMA_BUFFER)))
			) gamma_table1_i (
			.rclk (pclk), // input
			.raddr (table_raddr), // input[11:0]
			.ren (table_re[1]), // input TODO: add "en"?
			.regen (table_regen[1]), // input
			.data_out (table_rdata1), // output[7:0]
			.wclk (mclk), // input
			.waddr (taddr[10:0]), // input[9:0]
			.we (set_tdata_ram[1]), // input
			.web (8'hff), // input[7:0]
			.data_in (tdata) // input[31:0]
			);

	//sof_masked
	ramp_var_w_var_r #(		ramp_var_w_var_r #(
	.REGISTERS (1), // try to delay i2c_byte_start by one more cycle		.REGISTERS (1), // try to delay i2c_byte_start by one more cycle
	.LOG2WIDTH_WR (4),		.LOG2WIDTH_WR (4),
	.LOG2WIDTH_RD (4)		.LOG2WIDTH_RD (4),
	) i_gamma_table (		.DUMMY (!(SENS_GAMMA_BUFFER && (SENS_GAMMA_NUM_CHN > 2)))
			) gamma_table2_i (
	.rclk (pclk), // input		.rclk (pclk), // input
	.raddr ({table_page,color[1:0],pxd_in[15:8]}), // input[11:0]		.raddr (table_raddr), // input[11:0]
	.ren (hact_in), // input TODO: add "en"?		.ren (table_re[2]), // input TODO: add "en"?
	.regen (hact_d[0]), // input		.regen (table_regen[2]), // input
	.data_out ({table_diff_w[7:0],table_base_w[9:0]}), // output[7:0]		.data_out (table_rdata2), // output[7:0]
	.wclk (mclk), // input		.wclk (mclk), // input
	.waddr (taddr), // input[9:0]		.waddr (taddr[10:0]), // input[9:0]
	.we (set_tdata_w), // input		.we (set_tdata_ram[2]), // input
	.web (8'hff), // input[7:0]		.web (8'hff), // input[7:0]
	.data_in (cmd_data[17:0]) // input[31:0]		.data_in (tdata) // input[31:0]
	);		);

			ramp_var_w_var_r #(
			.REGISTERS (1), // try to delay i2c_byte_start by one more cycle
			.LOG2WIDTH_WR (4),
			.LOG2WIDTH_RD (4),
			.DUMMY (!(SENS_GAMMA_BUFFER && (SENS_GAMMA_NUM_CHN > 3)))
			) gamma_table3_i (
			.rclk (pclk), // input
			.raddr (table_raddr), // input[11:0]
			.ren (table_re[3]), // input TODO: add "en"?
			.regen (table_regen[3]), // input
			.data_out (table_rdata3), // output[7:0]
			.wclk (mclk), // input
			.waddr (taddr[10:0]), // input[9:0]
			.we (set_tdata_ram[3]), // input
			.web (8'hff), // input[7:0]
			.data_in (tdata) // input[31:0]
			);

	endmodule		endmodule

sensor/sens_parallel12.v

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -27,7 +27,7 @@ module sens_parallel12 #(
	parameter SENSIO_STATUS = 'h1,		parameter SENSIO_STATUS = 'h1,
	parameter SENSIO_JTAG = 'h2,		parameter SENSIO_JTAG = 'h2,
	parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT		parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
	parameter SENSIO_DELAYS = 'h4,		parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
	parameter SENSIO_STATUS_REG = 'h31,		parameter SENSIO_STATUS_REG = 'h31,

	parameter SENS_JTAG_PGMEN = 8,		parameter SENS_JTAG_PGMEN = 8,

sensor/sensor_channel.v

+36 −10

Original line number	Original line	Diff line number	Diff line
	@@ -21,10 +21,23 @@
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module sensor_channel#(		module sensor_channel#(
	parameter SENSI2C_ABS_ADDR = 'h300,		parameter SENSOR_BASE_ADDR = 'h300, // sensor registers base address
	parameter SENSI2C_REL_ADDR = 'h310,		parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels
			parameter SENSOR_CTRL_RADDR = 0, //'h300
			parameter SENSI2C_CTRL_RADDR = 2, // 302..'h303
			parameter SENS_GAMMA_RADDR = 4,
			parameter SENSIO_RADDR = 8, //'h308 .. 'h30c
			parameter SENSI2C_ABS_RADDR = 'h10, // 'h310..'h31f
			parameter SENSI2C_REL_RADDR = 'h20, // 'h320..'h32f
			parameter HISTOGRAM_RADDR0 = 'h30, //
			parameter HISTOGRAM_RADDR1 = 'h32, //
			parameter HISTOGRAM_RADDR2 = 'h34, //
			parameter HISTOGRAM_RADDR3 = -1, // < 0 - not implemented

			// parameter SENSI2C_ABS_ADDR = 'h302, // 'h300,
			// parameter SENSI2C_REL_ADDR = 'h320, // 'h310,
	parameter SENSI2C_ADDR_MASK = 'h3f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR		parameter SENSI2C_ADDR_MASK = 'h3f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
	parameter SENSI2C_CTRL_ADDR = 'h320,		// parameter SENSI2C_CTRL_ADDR = 'h302. // 'h320,
	parameter SENSI2C_CTRL_MASK = 'h3fe,		parameter SENSI2C_CTRL_MASK = 'h3fe,
	parameter SENSI2C_CTRL = 'h0,		parameter SENSI2C_CTRL = 'h0,
	parameter SENSI2C_STATUS = 'h1,		parameter SENSI2C_STATUS = 'h1,
	@@ -34,13 +47,13 @@ module sensor_channel#(
	parameter SENSI2C_IOSTANDARD = "DEFAULT",		parameter SENSI2C_IOSTANDARD = "DEFAULT",
	parameter SENSI2C_SLEW = "SLOW",		parameter SENSI2C_SLEW = "SLOW",

	parameter SENSIO_ADDR = 'h330,		// parameter SENSIO_ADDR = 'h308, // 'h330,
	parameter SENSIO_ADDR_MASK = 'h3f8,		parameter SENSIO_ADDR_MASK = 'h3f8,
	parameter SENSIO_CTRL = 'h0,		parameter SENSIO_CTRL = 'h0,
	parameter SENSIO_STATUS = 'h1,		parameter SENSIO_STATUS = 'h1,
	parameter SENSIO_JTAG = 'h2,		parameter SENSIO_JTAG = 'h2,
	parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT		parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
	parameter SENSIO_DELAYS = 'h4,		parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
	parameter SENSIO_STATUS_REG = 'h31,		parameter SENSIO_STATUS_REG = 'h31,

	parameter SENS_JTAG_PGMEN = 8,		parameter SENS_JTAG_PGMEN = 8,
	@@ -61,7 +74,7 @@ module sensor_channel#(
	parameter SENSOR_FIFO_2DEPTH = 4,		parameter SENSOR_FIFO_2DEPTH = 4,
	parameter SENSOR_FIFO_DELAY = 7,		parameter SENSOR_FIFO_DELAY = 7,

	parameter SENS_GAMMA_ADDR = 'h338,		// parameter SENS_GAMMA_ADDR = 'h304, //..'h307, // 'h338,
	parameter SENS_GAMMA_ADDR_MASK = 'h3fc,		parameter SENS_GAMMA_ADDR_MASK = 'h3fc,
	parameter SENS_GAMMA_CTRL = 'h0,		parameter SENS_GAMMA_CTRL = 'h0,
	// parameter SENS_GAMMA_STATUS = 'h1,		// parameter SENS_GAMMA_STATUS = 'h1,
	@@ -79,10 +92,10 @@ module sensor_channel#(
	parameter HISTOGRAM_ADDR_MASK = 'h3fe,		parameter HISTOGRAM_ADDR_MASK = 'h3fe,
	parameter HISTOGRAM_LEFT_TOP = 'h0,		parameter HISTOGRAM_LEFT_TOP = 'h0,
	parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT		parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
	parameter HISTOGRAM_ADDR0 = 'h340, // TODO: optimize!		// parameter HISTOGRAM_ADDR0 = 'h340, // TODO: optimize!
	parameter HISTOGRAM_ADDR1 = 'h342, // TODO: optimize!		// parameter HISTOGRAM_ADDR1 = 'h342, // TODO: optimize!
	parameter HISTOGRAM_ADDR2 = 'h344, // TODO: optimize!		// parameter HISTOGRAM_ADDR2 = 'h344, // TODO: optimize!
	parameter HISTOGRAM_ADDR3 = -1, // < 0 - not implemented		// parameter HISTOGRAM_ADDR3 = -1, // < 0 - not implemented


	parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?		parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
	@@ -141,6 +154,19 @@ module sensor_channel#(


	);		);
			// parameter SENSOR_BASE_ADDR = 'h300; // sensor registers base address
			localparam SENSOR_CTRL_ADDR = SENSOR_BASE_ADDR + SENSOR_CTRL_RADDR; //'h300
			localparam SENSI2C_CTRL_ADDR = SENSOR_BASE_ADDR + SENSI2C_CTRL_RADDR; // 302..'h303
			localparam SENS_GAMMA_ADDR = SENSOR_BASE_ADDR + SENS_GAMMA_RADDR;
			localparam SENSIO_ADDR = SENSOR_BASE_ADDR + SENSIO_RADDR; //'h308 .. 'h30c
			localparam SENSI2C_ABS_ADDR = SENSOR_BASE_ADDR + SENSI2C_ABS_RADDR; // 'h310..'h31f
			localparam SENSI2C_REL_ADDR = SENSOR_BASE_ADDR + SENSI2C_REL_RADDR; // 'h320..'h32f
			localparam HISTOGRAM_ADDR0 = (SENSOR_NUM_HISTOGRAM > 0)?HISTOGRAM_RADDR0:-1; //
			localparam HISTOGRAM_ADDR1 = (SENSOR_NUM_HISTOGRAM > 1)?HISTOGRAM_RADDR1:-1; //
			localparam HISTOGRAM_ADDR2 = (SENSOR_NUM_HISTOGRAM > 2)?HISTOGRAM_RADDR2:-1; //
			localparam HISTOGRAM_ADDR3 = (SENSOR_NUM_HISTOGRAM > 3)?HISTOGRAM_RADDR3:-1; //


	reg [7:0] cmd_ad; // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3		reg [7:0] cmd_ad; // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
	reg cmd_stb; // strobe (with first byte) for the command a/d		reg cmd_stb; // strobe (with first byte) for the command a/d

wrap/ram_var_w_var_r.v

+19 −2

Original line number	Original line	Diff line number	Diff line
	@@ -74,7 +74,8 @@ module ram_var_w_var_r
	#(		#(
	parameter integer REGISTERS = 0, // 1 - registered output		parameter integer REGISTERS = 0, // 1 - registered output
	parameter integer LOG2WIDTH_WR = 6, // WIDTH= 1 << LOG2WIDTH		parameter integer LOG2WIDTH_WR = 6, // WIDTH= 1 << LOG2WIDTH
	parameter integer LOG2WIDTH_RD = 6 // WIDTH= 1 << LOG2WIDTH		parameter integer LOG2WIDTH_RD = 6, // WIDTH= 1 << LOG2WIDTH
			parameter DUMMY = 0
	)		)
	(		(
	input rclk, // clock for read port		input rclk, // clock for read port
	@@ -91,7 +92,13 @@ module ram_var_w_var_r
	input [(1 << LOG2WIDTH_WR)-1:0] data_in // data out		input [(1 << LOG2WIDTH_WR)-1:0] data_in // data out
	);		);
	generate		generate
	if ((LOG2WIDTH_WR == 6) && (LOG2WIDTH_RD == 6))		if (DUMMY)
			ram_dummy #(
			.LOG2WIDTH_RD(LOG2WIDTH_RD)
			) ramp_dummy_i (
			.data_out(data_out)
			);
			else if ((LOG2WIDTH_WR == 6) && (LOG2WIDTH_RD == 6))
	ram_64w_64r #(		ram_64w_64r #(
	.REGISTERS (REGISTERS)		.REGISTERS (REGISTERS)
	) ram_i (		) ram_i (
	@@ -530,3 +537,13 @@ module ram_64w_lt64r

	endmodule		endmodule

			module ram_dummy
			#(
			parameter integer LOG2WIDTH_RD = 5 // WIDTH= 1 << LOG2WIDTH
			)
			(
			output [(1 << LOG2WIDTH_RD)-1:0] data_out // data out
			);
			assign data_out=0;
			endmodule

wrap/ramp_var_w_var_r.v

+19 −3

Original line number	Original line	Diff line number	Diff line
	@@ -75,7 +75,8 @@ module ramp_var_w_var_r
	#(		#(
	parameter integer REGISTERS = 0, // 1 - registered output		parameter integer REGISTERS = 0, // 1 - registered output
	parameter integer LOG2WIDTH_WR = 6, // WIDTH= 9 << (LOG2WIDTH - 3)		parameter integer LOG2WIDTH_WR = 6, // WIDTH= 9 << (LOG2WIDTH - 3)
	parameter integer LOG2WIDTH_RD = 6 // WIDTH= 9 << (LOG2WIDTH - 3)		parameter integer LOG2WIDTH_RD = 6, // WIDTH= 9 << (LOG2WIDTH - 3)
			parameter DUMMY = 0
	)		)
	(		(
	input rclk, // clock for read port		input rclk, // clock for read port
	@@ -92,7 +93,13 @@ module ramp_var_w_var_r
	input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out		input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
	);		);
	generate		generate
	if ((LOG2WIDTH_WR == 6) && (LOG2WIDTH_RD == 6))		if (DUMMY)
			ramp_dummy #(
			.LOG2WIDTH_RD(LOG2WIDTH_RD)
			) ramp_dummy_i (
			.data_out(data_out)
			);
			else if ((LOG2WIDTH_WR == 6) && (LOG2WIDTH_RD == 6))
	ramp_64w_64r #(		ramp_64w_64r #(
	.REGISTERS (REGISTERS)		.REGISTERS (REGISTERS)
	) ram_i (		) ram_i (
	@@ -546,3 +553,12 @@ module ramp_64w_lt64r

	endmodule		endmodule

			module ramp_dummy
			#(
			parameter integer LOG2WIDTH_RD = 5 // WIDTH= 1 << LOG2WIDTH
			)
			(
			output [(9 << (LOG2WIDTH_RD-3))-1:0] data_out // data out
			);
			assign data_out=0;
			endmodule

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