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Commit 0ec5957a authored by Andrey Filippov's avatar Andrey Filippov
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Reordered fold ROM table so first/second variant match colors, repeating 

R/B color twice (instead of 0), so the output values will have the same
value range.
parent 412a3a33
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Showing with 154 additions and 127 deletions
dsp/create_bayer_fold_rom.py
View file @ 0ec5957a
......@@ -218,6 +218,27 @@ def create_fold(n = 8): # n - DCT and window size
if not blank:
addresses.append (fold_index[i][var4])
signs.append ([((0,1)[fold_signs[0][i][var4] < 0]),((0,1)[fold_signs[1][i][var4] < 0])])
byrs = []
for var2 in range(2):
row = (addresses[var2] >> 4) & 0xf
col = (addresses[var2] >> 0) & 0xf
byr = ((row & 1) << 1) + (col & 1)
byrs.append(byr)
#make sure first variant always has lower byr index
if byrs[1] < byrs[0]:
addresses = [addresses[1],addresses[0]]
signs = [signs[1],signs[0]]
for var2 in range(2):
row = (addresses[var2] >> 4) & 0xf
col = (addresses[var2] >> 0) & 0xf
byr = ((row & 1) << 1) + (col & 1)
print ("%1d "%(byr,),end="")
print (" ",end="")
if ((i + 1) % 8) == 0:
print()
for size_bits, size_val in enumerate ([16,18,20,22]):
for var2 in range(2):
row = (addresses[var2] >> 4) & 0xf
......@@ -228,6 +249,7 @@ def create_fold(n = 8): # n - DCT and window size
((full_addr & 0xff) << 8) +
(signs[var2][0] << 16) +
(signs[var2][1] << 17))
print()
# wire [7:0] wnd_a_w = fold_rom_out[7:0];
# wire [PIX_ADDR_WIDTH-1:0] pix_a_w = {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};
......
dsp/mclt16x16_bayer.v
View file @ 0ec5957a
......@@ -97,7 +97,6 @@ module mclt16x16_bayer#(
reg inv_checker_r3;
reg inv_checker_r4;
// wire signed [WND_WIDTH-1:0] window; //!< msb==0, always positive
wire [1:0] signs; //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
wire [14:0] phases; //!< other signals
......@@ -140,7 +139,6 @@ module mclt16x16_bayer#(
reg dtt_r_regen;
reg dtt_start;
// wire [1:0] dtt_mode = {dtt_r_cntr[7], dtt_r_cntr[6]}; // TODO: or reverse?
wire dtt_mode = dtt_r_cntr[6]; // TODO: or reverse?
wire [8:0] dtt_r_ra = {1'b0,dtt_r_page,dtt_r_cntr};
wire signed [35:0] dtt_r_data_w; // high bits are not used
......@@ -179,25 +177,21 @@ module mclt16x16_bayer#(
y_shft_r4 <= y_shft_r3;
inv_checker_r4 <= inv_checker_r3;
end
if (phases[8]) begin
pix_d_r <= pix_d;
window_r <= window_w;
end
if (phases[9]) pix_wnd_r <= pix_d_r * window_r; // 1 MSB is extra
// pix_wnd_r2 - positive with 2 extra zeros, max value 0x3fff60
if (phases[10]) begin
pix_wnd_r2 <= {{2{pix_wnd_r2_w[DTT_IN_WIDTH-3]}},pix_wnd_r2_w};
// mpix_use_r <= mpix_use_d;
// var_first_r <= var_first_d;
pix_sgn_r <= pix_sgn_d;
end
var_last <= var_first & phases[11];
if (phases[11]) begin
// data_cc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + (mpix_use_r ? (mpix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;
// data_sc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + (mpix_use_r ? (mpix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;
data_cc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + (pix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2) ;
data_sc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + (pix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2) ;
data_sc_r2 <= data_sc_r;
......@@ -233,7 +227,6 @@ module mclt16x16_bayer#(
if (!dtt_r_re) dtt_r_cntr <= 0;
else dtt_r_cntr <= dtt_r_cntr + 1;
/// dtt_start <= dtt_r_cntr[5:0] == 0;
dtt_start <= (dtt_r_cntr[5:0] == 0) && dtt_r_re;
end
......@@ -243,17 +236,17 @@ module mclt16x16_bayer#(
.SHIFT_WIDTH (SHIFT_WIDTH),
.PIX_ADDR_WIDTH (PIX_ADDR_WIDTH),
.COORD_WIDTH (COORD_WIDTH),
.PIXEL_WIDTH (PIXEL_WIDTH),
.WND_WIDTH (WND_WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.DTT_IN_WIDTH (DTT_IN_WIDTH),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.OUT_RSHIFT (OUT_RSHIFT),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
.DEAD_CYCLES (DEAD_CYCLES)
// .PIXEL_WIDTH (PIXEL_WIDTH),
.WND_WIDTH (WND_WIDTH)
// .OUT_WIDTH (OUT_WIDTH),
// .DTT_IN_WIDTH (DTT_IN_WIDTH),
// .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
// .OUT_RSHIFT (OUT_RSHIFT),
// .OUT_RSHIFT2 (OUT_RSHIFT2),
// .DSP_B_WIDTH (DSP_B_WIDTH),
// .DSP_A_WIDTH (DSP_A_WIDTH),
// .DSP_P_WIDTH (DSP_P_WIDTH),
// .DEAD_CYCLES (DEAD_CYCLES)
) mclt_bayer_fold_i (
.clk (clk), // input
.rst (rst), // input
......@@ -324,12 +317,10 @@ module mclt16x16_bayer#(
wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};
reg [7:0] dtt_dly_cntr;
// reg [8:0] dtt_rd_cntr; // counter for dtt readout to rotator
reg [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator
// TODO: fix rd addresses
// wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency
reg [8:0] dtt_rd_ra0;
reg [8:0] dtt_rd_ra1;
......@@ -340,7 +331,6 @@ module mclt16x16_bayer#(
wire signed [OUT_WIDTH-1:0] dtt_rd_data0 = dtt_rd_data0_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
wire signed [OUT_WIDTH-1:0] dtt_rd_data1 = dtt_rd_data1_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
// wire dtt_first_quad_out = ~dtt_out_ram_cntr[3] & ~dtt_out_ram_cntr[2];
wire dtt_first_quad_out = ~dtt_out_ram_cntr[2];
always @(posedge clk) begin
......@@ -358,10 +348,6 @@ module mclt16x16_bayer#(
dtt_start_out <= dtt_dly_cntr == 1;
// if (rst) dtt_rd_regen_dv[0] <= 0;
// else if (dtt_start_out) dtt_rd_regen_dv[0] <= 1;
// else if (&dtt_rd_cntr[7:0]) dtt_rd_regen_dv[0] <= 0;
if (rst) dtt_rd_regen_dv[0] <= 0;
else if (dtt_start_out) dtt_rd_regen_dv[0] <= 1;
else if (&dtt_rd_cntr_pre[6:0]) dtt_rd_regen_dv[0] <= 0;
......@@ -369,11 +355,9 @@ module mclt16x16_bayer#(
if (rst) dtt_rd_regen_dv[3:1] <= 0;
else dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];
// if (dtt_start_out) dtt_rd_cntr_pre <= {dtt_out_ram_wah[4], 8'b0}; //copy page number
if (dtt_start_out) dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number
else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
//// wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency
dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5],
......
dsp/mclt_bayer_fold.v
View file @ 0ec5957a
......@@ -42,19 +42,19 @@ module mclt_bayer_fold#(
parameter SHIFT_WIDTH = 7, // bits in shift (7 bits - fractional)
parameter PIX_ADDR_WIDTH = 9, // number of pixel address width
// parameter EXT_PIX_LATENCY = 2, // external pixel buffer a->d latency
parameter ADDR_DLY = 4'h2, // extra delay of pixel address to match window delay
// parameter ADDR_DLY = 4'h2, // extra delay of pixel address to match window delay
parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM
parameter PIXEL_WIDTH = 16, // input pixel width (unsigned)
parameter WND_WIDTH = 18, // input pixel width (unsigned)
parameter OUT_WIDTH = 25, // bits in dtt output
parameter DTT_IN_WIDTH = 25, // bits in DTT input
parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)
parameter OUT_RSHIFT = 2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter OUT_RSHIFT2 = 0, // overall right shift for the second (vertical) pass
parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
parameter DSP_A_WIDTH = 25,
parameter DSP_P_WIDTH = 48,
parameter DEAD_CYCLES = 14 // start next block immedaitely, or with longer pause
// parameter PIXEL_WIDTH = 16, // input pixel width (unsigned)
parameter WND_WIDTH = 18 // input pixel width (unsigned)
// parameter OUT_WIDTH = 25, // bits in dtt output
// parameter DTT_IN_WIDTH = 25, // bits in DTT input
// parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)
// parameter OUT_RSHIFT = 2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
// parameter OUT_RSHIFT2 = 0, // overall right shift for the second (vertical) pass
// parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
// parameter DSP_A_WIDTH = 25,
// parameter DSP_P_WIDTH = 48,
// parameter DEAD_CYCLES = 14 // start next block immedaitely, or with longer pause
)(
input clk, //!< system clock, posedge
input rst, //!< sync reset
......@@ -77,12 +77,15 @@ module mclt_bayer_fold#(
);
reg [6:0] in_cntr; // input phase counter
reg [14:0] run_r; // run phase
reg [1:0] tile_size_r; // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
reg inv_checker_r;// 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
reg [7:0] top_left_r0; // index of the 16x16 top left corner
reg [7:0] top_left_r; // index of the 16x16 top left corner
reg [1:0] valid_rows_r0;// 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels
reg [1:0] valid_rows_r ;// correct latency for window rom
// reg [1:0] valid_rows_r ;// correct latency for window rom
/// wire [ 9:0] fold_addr= {tile_size_r,inv_checker_r, in_cntr[0],in_cntr[6:1]};
wire [ 9:0] fold_addr= {tile_size_r,inv_checker_r, (valid_rows_r0==3)?in_cntr[0]:valid_rows_r0[0],in_cntr[6:1]};
reg [SHIFT_WIDTH-1:0] x_shft_r0; // tile pixel X fractional shift (valid @ start)
reg [SHIFT_WIDTH-1:0] y_shft_r0; // tile pixel Y fractional shift (valid @ start)
reg [SHIFT_WIDTH-1:0] x_shft_r; // matching delay
......@@ -94,7 +97,7 @@ module mclt_bayer_fold#(
wire [PIX_ADDR_WIDTH-1:0] pix_a_w = {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};
reg [PIX_ADDR_WIDTH-1:0] pix_a_r;
wire [ 1:0] sgn_w = fold_rom_out[16 +: 2];
reg blank_r; // blank window (latency 1 from fold_rom_out)
// reg blank_r; // blank window (latency 1 from fold_rom_out)
// wire blank_d; // delayed to matchwindow rom regrst
wire pre_page = in_cntr == 2; // valid 1 cycle before fold_rom_out
......@@ -139,15 +142,15 @@ module mclt_bayer_fold#(
if (run_r[2]) pix_a_r <= pix_a_w + {1'b0, top_left_r};
if (in_cntr == 2) valid_rows_r <= valid_rows_r0;
/// if (in_cntr == 2) valid_rows_r <= valid_rows_r0;
blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]);
/// blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]);
if (run_r[10]) begin
var_first <= var_first_d;
end
pre_last_in <= in_cntr[7:0] == 8'hfd;
pre_last_in <= in_cntr[6:0] == 7'h7d;
......@@ -164,7 +167,7 @@ module mclt_bayer_fold#(
) i_mclt_fold_rom (
.clk_a (clk), // input
.addr_a ({tile_size_r,inv_checker_r, in_cntr[0],in_cntr[6:1]}), // input[9:0]
.addr_a (fold_addr), // input[9:0]
.en_a (run_r[0]), // input
.regen_a (run_r[1]), // input
.we_a (1'b0), // input
......@@ -219,7 +222,7 @@ module mclt_bayer_fold#(
.y_in (wnd_a_w[7:4]), // input[3:0]
.x_shft (x_shft_r), // input[7:0]
.y_shft (y_shft_r), // input[7:0]
.zero_in (blank_r), // input 2 cycles after inputs!
.zero_in (1'b0), // blank_r), // input 2 cycles after inputs!
.wnd_out (window) // output[17:0] valid with in_busy[8]
);
......
includes/mclt_bayer_fold_rom.vh
View file @ 0ec5957a
This diff is collapsed.
mclt_test_02.sav
View file @ 0ec5957a
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sat Dec 23 00:35:32 2017
[*] Sat Dec 23 06:37:18 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_02-20171222173437847.fst"
[dumpfile_mtime] "Sat Dec 23 00:34:42 2017"
[dumpfile_size] 1338753
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_02-20171222233655371.fst"
[dumpfile_mtime] "Sat Dec 23 06:37:00 2017"
[dumpfile_size] 1389826
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_02.sav"
[timestart] 0
[timestart] 275700
[size] 1920 1171
[pos] -1920 0
*-21.350550 1140000 355000 2885000 325000 7455000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-15.350550 306400 355000 2885000 325000 7455000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_02.
[treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i.
[treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i.
......@@ -1264,7 +1264,26 @@ mclt_test_02.mclt16x16_i.dtt_start_out
@28
mclt_test_02.mclt_bayer_fold_i.clk
mclt_test_02.mclt_bayer_fold_i.start
mclt_test_02.mclt_bayer_fold_i.pre_last_in
mclt_test_02.mclt_bayer_fold_i.pre_last_in_w
mclt_test_02.mclt_bayer_fold_i.pre_busy
@800200
-fold
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.start
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows[1:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows_r0[1:0]
@23
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows_r[1:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pre_last_in
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.wnd_a_w[7:0]
@1000200
-fold
-top
@22
mclt_test_02.mclt_bayer_fold_i.pix_d[15:0]
......@@ -1480,7 +1499,6 @@ mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.negm_1
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.negm_2
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.cntr_h[7:0]
@23
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.cntr_v[7:0]
@200
-
......
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