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Commit 09228f9d authored by Andrey Filippov's avatar Andrey Filippov
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minor cleanup

parent 730c34f7
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Showing with 17 additions and 85 deletions
dsp/dtt_iv8_1d.v
View file @ 09228f9d
......@@ -156,7 +156,6 @@ module dtt_iv8_1d#(
if (A_WIDTH > WIDTH) assign dsp_ain_1 = {{A_WIDTH-WIDTH{d_in[WIDTH-1]}},d_in};
else assign dsp_ain_1 = d_in; // SuppressThisWarning VEditor (not implemented)
endgenerate
// assign dsp_cin_1 = {{P_WIDTH-WIDTH{d_in[WIDTH-1]}},d_in};
// symmetrically lshift by COSINE_SHIFT (match multiplication by 1.0), add 0.5LSB for positive, subtract 0.5LSB for negative
wire din_zero = ~(|d_in);
......@@ -166,14 +165,6 @@ module dtt_iv8_1d#(
en_out_r2 <= en_out_r;
if (en_out_r2) begin
case (phase_cnt[3:1])
// 3'h0: y_index <= dst_out_r ? 7 : 0;
// 3'h1: y_index <= dst_out_r ? 0 : 7;
// 3'h2: y_index <= dst_out_r ? 3 : 4;
// 3'h3: y_index <= dst_out_r ? 4 : 3;
// 3'h4: y_index <= dst_out_r ? 6 : 1;
// 3'h5: y_index <= dst_out_r ? 1 : 6;
// 3'h6: y_index <= dst_out_r ? 5 : 2;
// 3'h7: y_index <= dst_out_r ? 2 : 5;
3'h0: y_index <= 0;
3'h1: y_index <= 7;
3'h2: y_index <= 4;
......@@ -207,7 +198,6 @@ module dtt_iv8_1d#(
if (start) dst_pre <= dst_in;
/// if (phase_cnt == 12) dst_2 <= dst_pre;
if (phase_cnt == 13) dst_2 <= dst_pre;
if (phase_cnt == 14) dst_out_r <= dst_2;
......@@ -295,7 +285,6 @@ module dtt_iv8_1d#(
dsp_selb_2 <= p00 | p03 | p05 | p06 | p08 | p11 | p13 | p14 ;
// dsp_neg_m_2 <= p03 | p06 | p12 | p15 ;
dsp_neg_m_2_dct <= p02 | p05 | p11 | p14 ;
// dsp_neg_m_2_dst <= p00 | p01 | p02 | p05 | p06 | p07 | p08 | p09 | p11 | p12 | p13 | p14 ;
dsp_neg_m_2_dst <= p03 | p04 | p10 | p15 ;
dsp_accum_2 <= p00 | p02 | p04 | p06 | p08 | p10 | p12 | p14 ;
end
......
dsp/dtt_iv_8x8_ad.v
View file @ 09228f9d
......@@ -193,20 +193,12 @@ module dtt_iv_8x8_ad#(
reg mode_h_ra1; // one cycle before x_ra1
wire [2:0] x_ra0inv = {3{mode_h_ra0}};
wire [2:0] x_ra1inv = {3{mode_h_ra1}};
// reg mode_v_ra;
reg mode_v_ra0; // one cycle before x_ra0
reg mode_v_ra1; // one cycle before x_ra1
wire [2:0] t_ra0inv = {3{mode_v_ra0}};
wire [2:0] t_ra1inv = {3{mode_v_ra1}};
reg [1:0] mode_h_late; // mode_h registered @ pre_last_in
reg [1:0] mode_v; // mode_h_late registered @ transpose_out_start ([0]used for vert pass)
// mode_out mode_v registered @ pre_first_out_w
wire [1:0] pre2_dsth; // 2 cycles before horizontal output data is valid, 0 dct, 1 - dst
wire [1:0] pre2_dstv; // 2 cycles before vertical output data is valid, 0 dct, 1 - dst
reg pre_dsth; // 1 cycles before horizontal output data is valid, 0 dct, 1 - dst
reg pre_dstv; // 1 cycles before vertical output data is valid, 0 dct, 1 - dst
reg dstv; // when vertical output data is valid, 0 dct, 1 - dst
wire start_out_w = out_cntr[6:0] == 'h0d;
......@@ -262,9 +254,6 @@ module dtt_iv_8x8_ad#(
dcth_start_0_r <= dcth_start_0_w;
dcth_start_1_r <= dcth_start_1_w;
pre_dsth <= dcth_en_out0 ? pre2_dsth[0] : pre2_dsth[1];
if (rst) transpose_in_run <= 0;
else if (transpose_start) transpose_in_run <= 1;
else if (transpose_cntr [6:0] == 7'h46) transpose_in_run <= 0; // check actual?
......@@ -276,23 +265,6 @@ module dtt_iv_8x8_ad#(
else if (transpose_in_run && (&transpose_cntr[5:0])) transpose_w_page <= transpose_w_page + 1;
case (transpose_cntr[3:0])
// 4'h0: transpose_wa_low <= 0 ^ {3{pre_dsth}};
// 4'h1: transpose_wa_low <= 1 ^ {3{pre_dsth}};
// 4'h2: transpose_wa_low <= 7 ^ {3{pre_dsth}};
// 4'h3: transpose_wa_low <= 6 ^ {3{pre_dsth}};
// 4'h4: transpose_wa_low <= 4 ^ {3{pre_dsth}};
// 4'h5: transpose_wa_low <= 2 ^ {3{pre_dsth}};
// 4'h6: transpose_wa_low <= 3 ^ {3{pre_dsth}};
// 4'h7: transpose_wa_low <= 5 ^ {3{pre_dsth}};
// 4'h8: transpose_wa_low <= 1 ^ {3{pre_dsth}};
// 4'h9: transpose_wa_low <= 0 ^ {3{pre_dsth}};
// 4'ha: transpose_wa_low <= 6 ^ {3{pre_dsth}};
// 4'hb: transpose_wa_low <= 7 ^ {3{pre_dsth}};
// 4'hc: transpose_wa_low <= 2 ^ {3{pre_dsth}};
// 4'hd: transpose_wa_low <= 4 ^ {3{pre_dsth}};
// 4'he: transpose_wa_low <= 5 ^ {3{pre_dsth}};
// 4'hf: transpose_wa_low <= 3 ^ {3{pre_dsth}};
4'h0: transpose_wa_low <= 0;
4'h1: transpose_wa_low <= 1;
4'h2: transpose_wa_low <= 7;
......@@ -318,7 +290,6 @@ module dtt_iv_8x8_ad#(
// Write transpose memory)
if (transpose_we[1]) transpose_ram[transpose_wa] <= transpose_di;
if (transpose_we[1]) transpose_debug_ram[transpose_wa] <= transpose_debug_di;
// if (transpose_we[1]) $display("%d %d @%t",transpose_cntr, transpose_wa, $time) ;
if (rst) transpose_out_run[0] <= 0;
else if (transpose_out_start) transpose_out_run[0] <= 1;
......@@ -358,10 +329,6 @@ module dtt_iv_8x8_ad#(
else if (dctv_start_1_w) dctv_en1 <= 1;
else if (dctv_phin[6]) dctv_en1 <= 0; // maybe get rid of this signal and send start for each 8?
pre_dstv <= dctv_en_out0 ? pre2_dstv[0] : pre2_dstv[1];
// if (t_we0 || t_we1) $display("%d %d",transpose_rcntr-2, transpose_out) ;
//write vertical dct input reorder memory
if (t_we0) t_ram0[{t_wa[4],t_wa[2:0]}] <= transpose_out;
if (t_we1) t_ram1[{t_wa[4],t_wa[2:0]}] <= transpose_out;
......@@ -382,9 +349,6 @@ module dtt_iv_8x8_ad#(
dctv_out_we <= {dctv_out_we[0], dctv_en_out0 | dctv_en_out1};
// alternative option
// Reordering data from a pair of vertical DCTs - 2 steps, 1 is not enough
if (rst) out_run <= 0;
else if (out_start) out_run <= 1;
......@@ -398,26 +362,7 @@ module dtt_iv_8x8_ad#(
if (dctv_out_we[1]) out_wd <= out_sel? dctv_dout1: dctv_dout0;
dstv <= pre_dstv;
case (out_cntr[3:0])
// 4'h0: out_wa[3:0] <= 4'h0 ^ {1'b0,{3{dstv}}};
// 4'h1: out_wa[3:0] <= 4'h9 ^ {1'b0,{3{dstv}}};
// 4'h2: out_wa[3:0] <= 4'h7 ^ {1'b0,{3{dstv}}};
// 4'h3: out_wa[3:0] <= 4'he ^ {1'b0,{3{dstv}}};
// 4'h4: out_wa[3:0] <= 4'h4 ^ {1'b0,{3{dstv}}};
// 4'h5: out_wa[3:0] <= 4'ha ^ {1'b0,{3{dstv}}};
// 4'h6: out_wa[3:0] <= 4'h3 ^ {1'b0,{3{dstv}}};
// 4'h7: out_wa[3:0] <= 4'hd ^ {1'b0,{3{dstv}}};
// 4'h8: out_wa[3:0] <= 4'h1 ^ {1'b0,{3{dstv}}};
// 4'h9: out_wa[3:0] <= 4'h8 ^ {1'b0,{3{dstv}}};
// 4'ha: out_wa[3:0] <= 4'h6 ^ {1'b0,{3{dstv}}};
// 4'hb: out_wa[3:0] <= 4'hf ^ {1'b0,{3{dstv}}};
// 4'hc: out_wa[3:0] <= 4'h2 ^ {1'b0,{3{dstv}}};
// 4'hd: out_wa[3:0] <= 4'hc ^ {1'b0,{3{dstv}}};
// 4'he: out_wa[3:0] <= 4'h5 ^ {1'b0,{3{dstv}}};
// 4'hf: out_wa[3:0] <= 4'hb ^ {1'b0,{3{dstv}}};
4'h0: out_wa[3:0] <= 4'h0;
4'h1: out_wa[3:0] <= 4'h9;
4'h2: out_wa[3:0] <= 4'h7;
......@@ -434,7 +379,6 @@ module dtt_iv_8x8_ad#(
4'hd: out_wa[3:0] <= 4'hc;
4'he: out_wa[3:0] <= 4'h5;
4'hf: out_wa[3:0] <= 4'hb;
endcase
sub16 <= ~out_cntr[3] & ~out_cntr[0] & out_run;
inc16 <= out_cntr[3:0] == 'he;
......@@ -555,9 +499,9 @@ module dtt_iv_8x8_ad#(
.d_in (dcth_xin0), // input[23:0]
.start (dcth_start_0_r), // input
.dout (dcth_dout0), // output[23:0]
.pre2_start_out (), // pre2_start_outh[0]), // output reg
.pre2_start_out (), // output reg
.en_out (dcth_en_out0), // output reg
.dst_out (pre2_dsth[0]), // output valid with en_out
.dst_out (), // output valid with en_out
.y_index (dcth_yindex0) // output[2:0] reg
);
......@@ -589,13 +533,12 @@ module dtt_iv_8x8_ad#(
.d_in (dcth_xin1), // input[23:0]
.start (dcth_start_1_r), // input
.dout (dcth_dout1), // output[23:0]
.pre2_start_out (), // pre2_start_outh[1]), // output reg
.pre2_start_out (), // output reg
.en_out (dcth_en_out1), // output reg
.dst_out (pre2_dsth[1]), // output valid with en_out
.dst_out (), // output valid with en_out
.y_index (dcth_yindex1) // output[2:0] reg
);
//dcth_phin_run && (dcth_phin [6:0] ==9)
dtt_iv8_1d #(
.WIDTH (TRANSPOSE_WIDTH),
......@@ -624,9 +567,9 @@ module dtt_iv_8x8_ad#(
.d_in (dctv_xin0), // input[23:0]
.start (dctv_start_0_r), // input
.dout (dctv_dout0), // output[23:0]
.pre2_start_out (), // pre2_start_outv[0]), // output reg
.pre2_start_out (), // output reg
.en_out (dctv_en_out0), // output reg
.dst_out (pre2_dstv[0]), // output valid with en_out
.dst_out (), // output valid with en_out
.y_index () // dctv_yindex0) // output[2:0] reg
);
......@@ -658,10 +601,10 @@ module dtt_iv_8x8_ad#(
.d_in (dctv_xin1), // input[23:0]
.start (dctv_start_1_r), // input
.dout (dctv_dout1), // output[23:0]
.pre2_start_out (), // pre2_start_outv[1]), // output reg
.pre2_start_out (), // output reg
.en_out (dctv_en_out1), // output reg
.dst_out (pre2_dstv[1]), // output valid with en_out
.y_index () //dctv_yindex1) // output[2:0] reg
.dst_out (), // output valid with en_out
.y_index () // output[2:0] reg
);
dly_var #(
......
mclt_test_01.sav
View file @ 09228f9d
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Tue Dec 19 07:49:51 2017
[*] Tue Dec 19 16:58:00 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171219002107123.fst"
[dumpfile_mtime] "Tue Dec 19 07:21:09 2017"
[dumpfile_size] 1109829
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171219005000376.fst"
[dumpfile_mtime] "Tue Dec 19 07:50:02 2017"
[dumpfile_size] 1108642
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav"
[timestart] 3926100
[timestart] 4720000
[size] 1814 1171
[pos] 1923 0
*-16.313055 4330300 2715000 3535000 3355000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-19.408367 7791000 2715000 3535000 3355000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_01.
[treeopen] mclt_test_01.mclt16x16_i.
[treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.
......
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