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x393
Commit 05a118d9 authored by Andrey Filippov's avatar Andrey Filippov
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working with cocotb simulation

parent ca6e4334
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Showing with 1434 additions and 166 deletions
.settings/com.elphel.vdt.cocotb.prefs
View file @ 05a118d9
......@@ -7,8 +7,9 @@ cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_@_GrepFindErr=error|ERROR
cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING
cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)
cocotb_@_SaveLogsPreprocessor=true
cocotb_@_SaveLogsSimulator=true
com.elphel.store.context.cocotb=cocotb_@_CocotbExtraFiles<-@\#\#@->cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_CocotbDutTopFile<-@\#\#@->cocotb_@_CocotbTESTCASE<-@\#\#@->cocotb_@_GrepFindErrWarn<-@\#\#@->cocotb_@_COCOTB_DEBUG<-@\#\#@->cocotb_@_SaveLogsPreprocessor<-@\#\#@->cocotb_@_SaveLogsSimulator<-@\#\#@->cocotb_@_GrepFindErr<-@\#\#@->
com.elphel.store.context.cocotb=cocotb_@_CocotbExtraFiles<-@\#\#@->cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_CocotbDutTopFile<-@\#\#@->cocotb_@_CocotbTESTCASE<-@\#\#@->cocotb_@_GrepFindErrWarn<-@\#\#@->cocotb_@_SaveLogsPreprocessor<-@\#\#@->cocotb_@_SaveLogsSimulator<-@\#\#@->cocotb_@_GrepFindErr<-@\#\#@->cocotb_@_PatternInfo<-@\#\#@->cocotb_@_COCOTB_DEBUG<-@\#\#@->
com.elphel.store.version.cocotb=0.8
eclipse.preferences.version=1
axi/cmprs_afi_mux.v
View file @ 05a118d9
......@@ -170,6 +170,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
//`endif
reg en; // enable mux
reg en_d; // or use it to reset all channels?
wire en_nrst = en && ! hrst; // when hclk is not yet available
reg [3:0] en_chn; // per-channel enable
wire [31:0] cmd_data;
......@@ -272,7 +273,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
wire [1:0] want_wleft32 = (|items_left[7:2])? 2'b11 : items_left[1:0]; // want to set wleft[3:2] if not roll-over (actually "3" means 2)
wire rollover_limited_w = max_wlen[1:0] < want_wleft32;
wire afi_wvalid_w;
assign cmd_we_status_w = cmd_we && ((cmd_a & 'hc) == CMPRS_AFIMUX_STATUS_CNTRL);
assign cmd_we_mode_w = cmd_we && (cmd_a == CMPRS_AFIMUX_MODE);
......@@ -280,7 +282,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
assign cmd_we_sa_len_w = cmd_we && ((cmd_a & 'h8) == CMPRS_AFIMUX_SA_LEN);
assign cmd_we_en_w = cmd_we && (cmd_a == CMPRS_AFIMUX_EN);
assign cmd_we_rst_w = cmd_we && (cmd_a == CMPRS_AFIMUX_RST);
assign afi_wvalid = afi_wvalid_w && !hrst;
// use last_chunk_w to apply a special id to waddr and wdata and watch for it during readout
......@@ -300,7 +302,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
assign afi_awaddr = {chunk_addr,5'b0};
assign afi_awid = afi_awid_r; // {1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
assign afi_awvalid = awvalid[1];
assign afi_awvalid = awvalid[1] && !hrst;
// assign afi_awlen = {wleft[3:2],2'b11};
assign afi_wdata = wdata;
// assign afi_bready = 1'b1; // always ready
......@@ -371,7 +373,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
always @ (posedge hclk) begin
en_d <= en;
en_d <= en && !hrst;
ready_to_start <= en && // ready to strta a burst
!afi_wacount[5] && !(&afi_wacount[4:1]) && // >=2 free
......@@ -472,7 +474,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
else if (wleft != 0) wleft <= wleft - 1;
if (!en) wvalid <= 0;
// if (!en) wvalid <= 0;
if (!en_nrst) wvalid <= 0;
else if (pre_busy_w) wvalid <= 1;
else if (wlast) wvalid <= 0; // should be after pre_busy_w as both can happen simultaneously
......@@ -489,8 +492,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
awvalid <= {awvalid[0],pre_busy_w}; // no need to wait for afi_awready, will use fifo levels to enable pre_busy_w
if (hrst) awvalid <= 0;
else awvalid <= {awvalid[0],pre_busy_w}; // no need to wait for afi_awready, will use fifo levels to enable pre_busy_w
if (pre_busy_w) begin
cur_chn <= winner2;
......@@ -523,7 +526,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
.rst (!en), // input
.dly (AFI_MUX_BUF_LATENCY), // input[3:0] will delay by AFI_MUX_BUF_LATENCY+1 (normally 3)
.din ({ wvalid, wlast}), // , afi_awid_r}), // afi_awid}), // input[0:0]
.dout ({afi_wvalid, afi_wlast}) //, afi_wid}) // output[0:0]
.dout ({afi_wvalid_w, afi_wlast}) //, afi_wid}) // output[0:0]
);
localparam [3:0] AFI_MUX_BUF_LATENCYM1 = AFI_MUX_BUF_LATENCY - 1;
dly_16 #(
......
cocotb/socket_command.py
View file @ 05a118d9
......@@ -39,6 +39,10 @@ class SocketCommand():
return self.command == "stop"
def getWrite(self):
return self.arguments if self.command == "write" else None
def getWait(self):
return self.arguments if self.command == "wait" else None
def getFlush(self):
return self.command == "flush"
def getRead(self):
return self.arguments if self.command == "read" else None
def setStart(self):
......@@ -48,6 +52,11 @@ class SocketCommand():
def setWrite(self,arguments):
self.command = "write"
self.arguments=arguments
def setWait(self,arguments): # wait irq mask, timeout (ns)
self.command = "wait"
self.arguments=arguments
def setFlush(self): #flush memory file (use when sync_for_*
self.command = "flush"
def setRead(self,arguments):
self.command = "read"
self.arguments=arguments
......@@ -88,7 +97,15 @@ class x393Client():
def write(self, address, data):
self.cmd.setWrite([address,data])
rslt = self.communicate(self.cmd.toJSON())
print("write->",rslt)
# print("write->",rslt)
def waitIrq(self, irqMask,wait_ns):
self.cmd.setWait([irqMask,wait_ns])
rslt = self.communicate(self.cmd.toJSON())
# print("waitIrq->",rslt)
def flush(self):
self.cmd.setFlush()
# print("flush->",self.communicate(self.cmd.toJSON()))
def read(self, address):
self.cmd.setRead(address)
# print("read->args",self.cmd.getArgs())
......
cocotb/x393_cocotb_02.sav
View file @ 05a118d9
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed Jul 6 17:53:54 2016
[*] Sun Jul 10 21:53:13 2016
[*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160706092756207.fst"
[dumpfile_mtime] "Wed Jul 6 16:46:27 2016"
[dumpfile_size] 26909872
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160710153754314.fst"
[dumpfile_mtime] "Sun Jul 10 21:52:27 2016"
[dumpfile_size] 86055110
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav"
[timestart] 0
[size] 1836 1171
[pos] 1920 0
*-24.853212 32750000 32750000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-24.555765 88800000 11730000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.ddr3_i.ddr3_i.
[treeopen] x393_dut.simul_axi_hp1_wr_i.
[treeopen] x393_dut.simul_axi_master_wdata_i.
[sst_width] 357
[signals_width] 238
[treeopen] x393_dut.x393_i.
[treeopen] x393_dut.x393_i.compressor393_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].
[treeopen] x393_dut.x393_i.compressor393_i.genblk3.
[treeopen] x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
[sst_width] 361
[signals_width] 280
[sst_expanded] 1
[sst_vpaned_height] 484
[sst_vpaned_height] 530
@820
x393_dut.TEST_TITLE[639:0]
@c00200
......@@ -112,17 +134,476 @@ x393_dut.simul_sensor12bits_i.D[11:0]
@28
x393_dut.simul_sensor12bits_i.HACT
x393_dut.simul_sensor12bits_i.MRST
@29
x393_dut.simul_sensor12bits_i.ARST
@28
x393_dut.simul_sensor12bits_i.NMRST
x393_dut.simul_sensor12bits_i.stopped
x393_dut.simul_sensor12bits_i.DCLK
@1000200
-SENSOR1
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst_in
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mrst
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst
@c00200
-memory_timing
@200
-
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst_in
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dci_rst
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr_rst
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dly_addr[6:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dly_data[7:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ld_delay
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ld_mmcm
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ps_rdy
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ps_out[7:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.set
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.locked_mmcm
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.locked_pll
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_din[7:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.rst
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.psclk
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_we
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start0
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_dout_r[7:0]
@200
-
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dly_data[7:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.set_idelay
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.set_odelay
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ld_idelay
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ld_odelay
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dq[15:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsl
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsu
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dqs[3:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs[3:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs_r[3:0]
@200
-
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_a[14:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_ba[2:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_cas
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_cke
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_clk
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_nclk
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_nrst
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_odt
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_ras
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_we
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr_rst
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk_pre
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.cmda_cke_i.clk
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.cmda_cke_i.clk_div
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.cmda_cke_i.din[1:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.cmda_cke_i.dq
x393_dut.x393_i.mclk
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mrst
@200
-
@1401200
-memory_timing
@800200
-resets
@28
x393_dut.x393_i.axi_rst_pre
@c00022
x393_dut.x393_i.sync_resets_i.locked[6:0]
@28
(0)x393_dut.x393_i.sync_resets_i.locked[6:0]
(1)x393_dut.x393_i.sync_resets_i.locked[6:0]
(2)x393_dut.x393_i.sync_resets_i.locked[6:0]
(3)x393_dut.x393_i.sync_resets_i.locked[6:0]
(4)x393_dut.x393_i.sync_resets_i.locked[6:0]
(5)x393_dut.x393_i.sync_resets_i.locked[6:0]
(6)x393_dut.x393_i.sync_resets_i.locked[6:0]
@1401200
-group_end
@800022
x393_dut.x393_i.sync_resets_i.clk[6:0]
@28
(0)x393_dut.x393_i.sync_resets_i.clk[6:0]
(1)x393_dut.x393_i.sync_resets_i.clk[6:0]
(2)x393_dut.x393_i.sync_resets_i.clk[6:0]
(3)x393_dut.x393_i.sync_resets_i.clk[6:0]
(4)x393_dut.x393_i.sync_resets_i.clk[6:0]
(5)x393_dut.x393_i.sync_resets_i.clk[6:0]
(6)x393_dut.x393_i.sync_resets_i.clk[6:0]
@1001200
-group_end
@800022
x393_dut.x393_i.sync_resets_i.rst[6:0]
@28
(0)x393_dut.x393_i.sync_resets_i.rst[6:0]
(1)x393_dut.x393_i.sync_resets_i.rst[6:0]
(2)x393_dut.x393_i.sync_resets_i.rst[6:0]
(3)x393_dut.x393_i.sync_resets_i.rst[6:0]
(4)x393_dut.x393_i.sync_resets_i.rst[6:0]
(5)x393_dut.x393_i.sync_resets_i.rst[6:0]
(6)x393_dut.x393_i.sync_resets_i.rst[6:0]
x393_dut.x393_i.sync_resets_i.arst
x393_dut.x393_i.sync_resets_i.mrst
x393_dut.x393_i.sync_resets_i.rst_early_master_w
x393_dut.x393_i.sync_resets_i.rst_early_master
@1001200
-group_end
@200
-
@1000200
-SENSOR1
-resets
@800200
-sensor_channel0
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pclk
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd[11:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.hact
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sof
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_valid
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.wpage[1:0]
@200
-other_channels
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.pxd[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.pxd[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0]
@800200
-memory
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.mclk
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_dout[63:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_rd
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_we
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_a[3:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_data[31:0]
@200
-
@1000200
-memory
-sensor_channel0
@800200
-compressor_channel0
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.mclk
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_din[63:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_we
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_rd[1:0]
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_ra[11:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_pxd[7:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.mb_data_out[7:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.signed_y[8:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.signed_c[8:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.ywe
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cwe
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_nodc[9:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_avr[8:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_pre_first_out
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_out[12:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quant_do[12:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quant_ds
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.focus_do[12:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.focus_ds
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.first_block_quant
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enc_do[15:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enc_dv
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_do[31:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_dv
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_out_fifo_i.wdata[31:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_rst
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_ren
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_rdata[63:0]
@8022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_count[7:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hrst
@200
-
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_en
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_go
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_num_compressed[3:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_dst[15:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_src[15:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_started[15:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_start_dst
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.suspend
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.vsync_late
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hclk
@1000200
-compressor_channel0
@800200
-interrupts
@800022
x393_dut.irq_r[8:0]
@28
(0)x393_dut.irq_r[8:0]
(1)x393_dut.irq_r[8:0]
(2)x393_dut.irq_r[8:0]
(3)x393_dut.irq_r[8:0]
(4)x393_dut.irq_r[8:0]
(5)x393_dut.irq_r[8:0]
(6)x393_dut.irq_r[8:0]
(7)x393_dut.irq_r[8:0]
(8)x393_dut.irq_r[8:0]
@1001200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.is_r
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.im_r
@c00023
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(6)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(7)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(8)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(9)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(10)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
(11)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.status[11:0]
@1401201
-group_end
@200
-
@1000200
-interrupts
@c00200
-afi0_mux
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmd_we
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmd_a[3:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmd_data[31:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awaddr[31:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awburst[1:0]
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awcache[3:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awid[5:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awid_r[5:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awlen[3:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awlock[1:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awprot[2:0]
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awqos[3:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awready
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awsize[1:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awvalid
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_bid[5:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_bready
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_bresp[1:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_bvalid
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wacount[5:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wcount[7:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wdata[63:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wid[5:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wlast
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wready
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wrissuecap1en
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wstrb[7:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wvalid
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.awvalid[1:0]
@200
-
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.pre_busy_w
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.busy[3:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.ready_to_start
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.ptr_resetting
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.need_to_bother
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.counts_corr2[8:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.counts_corr1[17:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.counts_corr0[35:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_count0[7:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.en_chn[3:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.ren_suspend_flush[3:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_ren0
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_flush0
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_count0[7:0]
@8022
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_count1[7:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_count2[7:0]
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_count3[7:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.hclk
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.hrst
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.en
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wvalid
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.wvalid
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.en_d
@1401200
-afi0_mux
@c00200
-saxihp1
@22
x393_dut.saxihp1_bresp_latency[3:0]
x393_dut.saxihp1_wid[5:0]
x393_dut.saxihp1_wr_address[31:0]
@28
x393_dut.saxihp1_wr_cap[2:0]
@22
x393_dut.saxihp1_wr_data[63:0]
x393_dut.saxihp1_wr_qos[3:0]
@28
x393_dut.saxihp1_wr_ready
@22
x393_dut.saxihp1_wr_stb[7:0]
@28
x393_dut.saxihp1_wr_valid
@800200
-x393_afi1
@22
x393_dut.x393_i.afi1_awaddr[31:0]
@28
x393_dut.x393_i.afi1_awburst[1:0]
@22
x393_dut.x393_i.afi1_awcache[3:0]
x393_dut.x393_i.afi1_awid[5:0]
x393_dut.x393_i.afi1_awlen[3:0]
@28
x393_dut.x393_i.afi1_awlock[1:0]
x393_dut.x393_i.afi1_awprot[2:0]
@22
x393_dut.x393_i.afi1_awqos[3:0]
@28
x393_dut.x393_i.afi1_awready
x393_dut.x393_i.afi1_awsize[1:0]
x393_dut.x393_i.afi1_awvalid
@22
x393_dut.x393_i.afi1_bid[5:0]
@28
x393_dut.x393_i.afi1_bready
x393_dut.x393_i.afi1_bresp[1:0]
x393_dut.x393_i.afi1_bvalid
x393_dut.x393_i.afi1_clk
@22
x393_dut.x393_i.afi1_wacount[5:0]
x393_dut.x393_i.afi1_wcount[7:0]
x393_dut.x393_i.afi1_wdata[63:0]
x393_dut.x393_i.afi1_wid[5:0]
@28
x393_dut.x393_i.afi1_wlast
x393_dut.x393_i.afi1_wready
x393_dut.x393_i.afi1_wrissuecap1en
@22
x393_dut.x393_i.afi1_wstrb[7:0]
@28
x393_dut.x393_i.afi1_wvalid
@1000200
-x393_afi1
@1401200
-saxihp1
@800200
-simul_axi_hp1_wr
@22
x393_dut.simul_axi_hp1_wr_i.sim_bresp_latency[3:0]
x393_dut.simul_axi_hp1_wr_i.sim_wid[5:0]
x393_dut.simul_axi_hp1_wr_i.sim_wr_address[31:0]
@28
x393_dut.simul_axi_hp1_wr_i.sim_wr_cap[2:0]
@22
x393_dut.simul_axi_hp1_wr_i.sim_wr_data[63:0]
x393_dut.simul_axi_hp1_wr_i.sim_wr_qos[3:0]
@28
x393_dut.simul_axi_hp1_wr_i.sim_wr_ready
@22
x393_dut.simul_axi_hp1_wr_i.sim_wr_stb[7:0]
@28
x393_dut.simul_axi_hp1_wr_i.sim_wr_valid
@22
x393_dut.simul_axi_hp1_wr_i.wdata_out[63:0]
@800200
-wdata_i
@28
x393_dut.simul_axi_hp1_wr_i.wdata_i.rst
@22
x393_dut.simul_axi_hp1_wr_i.wdata_i.data_in[78:0]
x393_dut.simul_axi_hp1_wr_i.wdata_i.data_out[78:0]
x393_dut.simul_axi_hp1_wr_i.wdata_i.wa[6:0]
@28
x393_dut.simul_axi_hp1_wr_i.wdata_i.we
x393_dut.simul_axi_hp1_wr_i.wdata_i.re
x393_dut.simul_axi_hp1_wr_i.wdata_i.nempty
@8022
x393_dut.simul_axi_hp1_wr_i.wdata_i.wcount[6:0]
x393_dut.simul_axi_hp1_wr_i.wdata_i.rcount[6:0]
x393_dut.simul_axi_hp1_wr_i.wdata_i.wnum_in_fifo[7:0]
x393_dut.simul_axi_hp1_wr_i.wdata_i.rnum_in_fifo[7:0]
@28
x393_dut.simul_axi_hp1_wr_i.wdata_i.half_full
@22
x393_dut.simul_axi_hp1_wr_i.wdata_i.fill[7:0]
@1000200
-wdata_i
-simul_axi_hp1_wr
@200
-
@c00200
-axi_master_wdata
@28
x393_dut.simul_axi_master_wdata_i.clk
......@@ -176,6 +657,7 @@ x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.reset
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.valid
@1000200
-simul_axi_fifo
@1401200
-axi_master_wdata
[pattern_trace] 1
[pattern_trace] 0
cocotb/x393_cocotb_server.py
View file @ 05a118d9
......@@ -28,43 +28,126 @@ import select
from socket_command import SocketCommand
from cocotb.triggers import Timer
from x393interfaces import MAXIGPMaster
from x393interfaces import MAXIGPMaster, PSBus, SAXIRdSim, SAXIWrSim
from cocotb.drivers import BitDriver
from cocotb.triggers import Timer, RisingEdge, ReadOnly
from cocotb.result import ReturnValue, TestFailure, TestError, TestSuccess
import logging
import re
import struct
def hex_list(lst, max_items=0, frmt="0x%08x"):
if (max_items == 0) or (len(lst) <= max_items):
hs="["
for d in lst:
hs+=frmt%(d)+", "
return hs[:-2]+"]"
hs = "%d ["%len(lst)
fi = max_items-1 if max_items > 1 else max_items
for d in lst[:fi]:
hs+=frmt%(d)+", "
hs += "..."
if fi < max_items:
hs += " "+frmt%(d)
return hs+"]"
class X393_cocotb_server(object):
INTR_ADDRESS = 0xfffffff0 #temporary address
INTM_ADDRESS = 0xfffffff4 #temporary address
RESERVED = (INTR_ADDRESS,INTM_ADDRESS)
writeIDMask = (1 <<12) -1
readIDMask = (1 <<12) -1
started=False
def __init__(self, dut, port, host, mempath="memfile", autoflush=True): # , debug=False):
int_mask = 0 # all disabled
def __init__(self, dut, port, host, mempath=None, autoflush=True): # , debug=False):
self.ACLK_FREQ=50000000 # 50 MHz
debug = os.getenv('COCOTB_DEBUG') # None/1
self.cmd= SocketCommand()
self.dut = dut
if mempath is None:
mempath = os.getenv('SIMULATION_PATH')+"/"+"memfile"
self.mempath = mempath
self.memlow = 0
self.memhigh = 0x40000000
self.autoflush = autoflush
self.cmd= SocketCommand()
self.dut = dut
#Open file to use as system memory
try:
self._memfile=open(mempath, 'r+') #keep old file if it exists already
except:
self._memfile=open(mempath, 'w+') #create a new file if it does not exist
self.dut._log.info ("Created a new 'memory' file %s"%(mempath)) #
#Extend to full size
self._memfile.seek(self.memhigh-1)
readOK=False
try:
readOK = len(self._memfile.read(1))>0
self.dut._log.info ("Read from 0x%08x"%(self.memhigh-1)) #
except:
pass
if not readOK:
self._memfile.seek(self.memhigh-1)
self._memfile.write(chr(0))
self._memfile.flush()
self.dut._log.info("Wrote to 0x%08x to extend file to full size"%(self.memhigh-1)) #
#initialize MAXIGP0 interface (main control/status registers, TODO: add MAXIGP1 for SATA)
self.maxigp0 = MAXIGPMaster(entity=dut, name="dutm0", clock=dut.dutm0_aclk, rdlag=0, blag=0)
self.maxigp0 = MAXIGPMaster(entity = dut,
name = "dutm0",
clock = dut.dutm0_aclk,
rdlag = 0,
blag=0)
self.writeID=0
self.readID=0
#initialize Zynq register access, has methods write_reg(a,d) and read_reg(a)
self.ps_sbus = PSBus(entity=dut, name="ps_sbus", clock=dut.ps_sbus_clk)
self.ps_sbus = PSBus (entity = dut,
name = "ps_sbus",
clock = dut.ps_sbus_clk)
#Bus masters (communicated over mempath file
#Membridge to FPGA
self.saxihp0r = SAXIRdSim(entity=dut, name="saxihp0", clock=dut.axi_hclk, mempath = mempath, memhigh=0x40000000, data_bytes=8)
self.saxihp0r = SAXIRdSim (entity = dut,
name = "saxihp0",
clock = dut.axi_hclk,
mempath = self.mempath,
memhigh = self.memhigh,
data_bytes = 8)
#Membridge from FPGA
self.saxihp0w = SAXIWrSim(entity=dut, name="saxihp0", clock=dut.axi_hclk, mempath = mempath, memhigh=0x40000000, data_bytes=8,
autoflush = autoflush, blatency=5)
self.saxihp0w = SAXIWrSim (entity = dut,
name = "saxihp0",
clock = dut.axi_hclk,
mempath = self.mempath,
memhigh = self.memhigh,
data_bytes = 8,
autoflush = self.autoflush,
blatency = 5)
#Compressors from FPGA
self.saxihp1w = SAXIWrSim(entity=dut, name="saxihp1", clock=dut.axi_hclk, mempath = mempath, memhigh=0x40000000, data_bytes=8,
autoflush = autoflush, blatency=5)
self.saxihp1w = SAXIWrSim (entity = dut,
name = "saxihp1",
clock = dut.axi_hclk,
mempath = self.mempath,
memhigh = self.memhigh,
data_bytes = 8,
autoflush = self.autoflush,
blatency = 5)
#histograms from FPGA
self.saxigp0 = SAXIWrSim(entity=dut, name="saxigp0", clock=dut.saxigp0, mempath = mempath, memhigh=0x40000000, data_bytes=4,
autoflush = autoflush, blatency=5)
self.saxigp0 = SAXIWrSim (entity = dut,
name = "saxigp0",
clock = dut.saxi0_aclk,
mempath = self.mempath,
memhigh = self.memhigh,
data_bytes = 4,
autoflush = self.autoflush,
blatency = 5)
level = logging.DEBUG if debug else logging.WARNING
self.dut._log.info('Set debug level '+str(level)+", debug="+str(debug))
self.maxigp0.log.setLevel(level)
self.ps_sbus.log.setLevel(level)
self.saxihp0r.log.setLevel(level)
self.saxihp0w.log.setLevel(level)
self.saxihp1w.log.setLevel(level)
self.saxigp0.log.setLevel(level)
#Initialize socket
self.PORT = port
self.HOST = host # Symbolic name meaning all available interfaces
......@@ -76,10 +159,9 @@ class X393_cocotb_server(object):
self.socket_conn.listen(1) # just a single request (may increase to 5 (backlog)
self.dut._log.info ('Socket now listening to a single request on port %d: send command, receive response, close'%(self.PORT))
except socket.error as msg:
self.dut._log.info ("Maybe you need to run 'killall vvp' to close previously opened socket?" )
self.logErrorTerminate('Bind failed. Error Code : %s Message %s'%( str(msg[0]),msg[1]))
def logErrorTerminate(self, msg):
self.dut._log.error(msg)
......@@ -113,18 +195,16 @@ class X393_cocotb_server(object):
if self.cmd.getStart():
self.dut._log.info('Received START, waiting reset to be over')
yield Timer(10000)
while self.dut.reset_out.value.get_binstr() != "1":
yield Timer(10000)
while self.dut.reset_out.value:
yield Timer(10000)
# Launch all bus masters (no need to join ever, preserving just in case
self.self.saxihp0r_thread = cocotb.fork(saxihp0r.saxi_rd_run)
self.self.saxihp0w_thread = cocotb.fork(saxihp0w.saxi_wr_run)
self.self.saxihp1w_thread = cocotb.fork(saxihp1w.saxi_wr_run)
self.self.saxihp2w_thread = cocotb.fork(saxihp2w.saxi_wr_run)
self.saxihp0r_thread = cocotb.fork(self.saxihp0r.saxi_rd_run())
self.saxihp0w_thread = cocotb.fork(self.saxihp0w.saxi_wr_run())
self.saxihp1w_thread = cocotb.fork(self.saxihp1w.saxi_wr_run())
self.saxigp0_thread = cocotb.fork(self.saxigp0.saxi_wr_run())
self.soc_conn.send(self.cmd.toJSON(0)+"\n")
self.dut._log.debug('Sent 0 to the socket')
started=True
......@@ -143,9 +223,20 @@ class X393_cocotb_server(object):
#For now write - one at a time, TODO: a) consolidate, b) decode address (some will be just a disk file)
elif self.cmd.getWrite():
ad = self.cmd.getWrite()
self.dut._log.info('Received WRITE, 0x%0x: %s'%(ad[0],str(ad[1])))
if ad[0] < 0x40000000:
pass
self.dut._log.debug('Received WRITE, 0x%0x: %s'%(ad[0],hex_list(ad[1])))
if ad[0]in self.RESERVED:
if ad[0] == self.INTM_ADDRESS:
self.int_mask = ad[1][0]
rslt = 0
elif (ad[0] >= self.memlow) and (ad[0] < self.memhigh):
addr = ad[0]
self._memfile.seek(addr)
for data in ad[1]: # currently only single word is supported
sdata=struct.pack("<L",data) # little-endian, u32
self._memfile.write(sdata)
self.dut._log.debug("Written 'system memory': 0x%08x => 0x%08x"%(data,addr))
addr += 4
rslt = 0
elif(ad[0] >= 0x40000000) and (ad[0] < 0x80000000):
rslt = yield self.maxigp0.axi_write(address = ad[0],
value = ad[1],
......@@ -155,42 +246,98 @@ class X393_cocotb_server(object):
burst = 1,
address_latency = 0,
data_latency = 0)
self.dut._log.info('maxigp0.axi_write yielded %s'%(str(rslt)))
self.dut._log.debug('maxigp0.axi_write yielded %s'%(str(rslt)))
self.writeID = (self.writeID+1) & self.writeIDMask
elif ad[0] >= 0xc0000000:
elif (ad[0] >= 0xc0000000) and (ad[0] < 0xfffffffc):
self.ps_sbus.write_reg(ad[0],ad[1][0])
rslt = 0
else:
self.dut._log.info('Write address 0x%08x is outside of maxgp0, not yet supported'%(ad[0]))
rslt = 0
rslt = 0
self.dut._log.info('WRITE 0x%08x <= %s'%(ad[0],hex_list(ad[1], max_items = 4)))
self.soc_conn.send(self.cmd.toJSON(rslt)+"\n")
self.dut._log.debug('Sent rslt to the socket')
elif self.cmd.getRead():
a = self.cmd.getRead()
if a < 0x40000000:
pass
if(a >= 0x40000000) and (a < 0x80000000):
dval = yield self.maxigp0.axi_read(address = a,
ad = self.cmd.getRead()
self.dut._log.debug(str(ad))
if not isinstance(ad,(list,tuple)):
ad=(ad,1)
elif len(ad) < 2:
ad=(ad[0],1)
self.dut._log.debug(str(ad))
if ad[0]in self.RESERVED:
if ad[0] == self.INTR_ADDRESS:
try:
dval=[self.dut.irq_r.value.integer]
except:
bv = self.dut.irq_r.value
bv.binstr = re.sub("[^1]","0",bv.binstr)
dval=[bv.integer]
elif ad[0] == self.INTM_ADDRESS:
dval = [self.int_mask]
else:
dval = [0]
elif (ad[0] >= self.memlow) and (ad[0] < self.memhigh):
addr = ad[0]
self._memfile.seek(addr)
self.dut._log.debug("read length="+str(len(self._memfile.read(4*ad[1]))))
self._memfile.seek(addr)
self.dut._log.debug(str(ad))
dval = list(struct.unpack("<"+"L"*ad[1],self._memfile.read(4*ad[1])))
msg="'Written 'system memory: 0x%08x => "%(addr)
for d in dval:
msg += "0x%08x "%(d)
self.dut._log.debug(msg)
elif(ad[0] >= 0x40000000) and (ad[0] < 0x80000000):
dval = yield self.maxigp0.axi_read(address = ad[0],
id = self.readID,
dlen = 1,
dlen = ad[1],
dsize = 2,
address_latency = 0,
data_latency = 0 )
self.dut._log.info("axi_read returned => " +str(dval))
self.dut._log.debug("axi_read returned 0x%08x => %s"%(ad[0],hex_list(dval, max_items = 4)))
self.readID = (self.readID+1) & self.readIDMask
elif ad[0] >= 0xc0000000:
elif (ad[0]>= 0xc0000000) and (ad[0] < 0xfffffffc):
dval = yield self.ps_sbus.read_reg(ad[0])
else:
self.dut._log.info('Read address 0x%08x is outside of maxgp0, not yet supported'%(a))
self.dut._log.info('Read address 0x%08x is outside of maxgp0, not yet supported'%(ad[0]))
dval = [0]
self.soc_conn.send(self.cmd.toJSON(dval)+"\n")
self.dut._log.debug('Sent dval to the socket')
self.dut._log.info("READ 0x%08x =>%s"%(ad[0],hex_list(dval, max_items = 4)))
elif self.cmd.getFlush():
self.dut._log.info('Received flush')
self.flush_all()
self.soc_conn.send(self.cmd.toJSON(0)+"\n")
self.dut._log.debug('Sent 0 to the socket')
def flush_all(self):
self.self.saxihp0w.flush()
self.self.saxihp1w.flush()
self.self.saxihp2w.flush()
elif self.cmd.getWait():
#self.MAXIGP0_CLK_FREQ
int_dly = self.cmd.getWait()
self.int_mask = int_dly[0]
num_clk= (int_dly[1] * self.ACLK_FREQ) // 1000000000
self.dut._log.info('Received WAIT, interrupt mask = 0x%0x, timeout = %d ns, %d clocks'%(self.int_mask,int_dly[1], num_clk))
n = 0
for _ in range(num_clk):
yield RisingEdge(self.dut.dutm0_aclk)
try:
irq_r=self.dut.irq_r.value.integer
except:
bv = self.dut.irq_r.value
bv.binstr = re.sub("[^1]","0",bv.binstr)
irq_r=bv.integer
if (self.int_mask & irq_r):
break
n += 1
self.soc_conn.send(self.cmd.toJSON(n)+"\n")
self.dut._log.debug('Sent %d to the socket'%(n))
self.dut._log.info(' WAIT over, passed %d ns'%((n * 1000000000)//self.ACLK_FREQ))
else:
self.dut._log.warning('Received unknown command: '+str(self.cmd))
self.soc_conn.send(self.cmd.toJSON(1)+"\n")
self.dut._log.debug('Sent 1 to the socket')
def convert_string(txt):
number=0
......
cocotb/x393_dut.v
View file @ 05a118d9
......@@ -357,19 +357,23 @@ module x393_dut#(
//`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh
// *** Adjusting includes/x393_cur_params_target.vh by the hardware may break simulation, hard-wired parameters below are tested ***
/*
`ifdef USE_HARD_CURPARAMS
localparam DLY_LANE0_ODELAY = 80'hd85c1014141814181218;
localparam DLY_LANE0_IDELAY = 72'h2c7a8380897c807b88;
localparam DLY_LANE1_ODELAY = 80'hd8581812181418181814;
localparam DLY_LANE1_IDELAY = 72'h108078807a887c8280;
localparam DLY_CMDA = 256'hd3d3d3d4dcd1d8cc494949494949494949d4d3ccd3d3dbd4ccd4d2d3d1d2d8cc;
`include "includes/x393_cur_params_target_simulation.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
// localparam DLY_LANE0_ODELAY = 80'hd85c1014141814181218;
// localparam DLY_LANE0_IDELAY = 72'h2c7a8380897c807b88;
// localparam DLY_LANE1_ODELAY = 80'hd8581812181418181814;
// localparam DLY_LANE1_IDELAY = 72'h108078807a887c8280;
// localparam DLY_CMDA = 256'hd3d3d3d4dcd1d8cc494949494949494949d4d3ccd3d3dbd4ccd4d2d3d1d2d8cc;
// localparam DLY_PHASE = 8'h33;
`else
`include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
`endif
`include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used
*/
// ========================== parameters from x353 ===================================
`ifdef SYNC_COMPRESS
......@@ -719,10 +723,10 @@ assign #10 gpio_pins[9] = gpio_pins[8];
// reg [639:0] TEST_TITLE="abcdef"; //S uppressThisWarning VEditor May use again later
// Simulation signals
wire CLK;
reg RST;
reg RST_CLEAN = 1;
// reg RST_CLEAN = 1;
/*
wire [NUM_INTERRUPTS-1:0] IRQ_R = {x393_i.sata_irq, x393_i.cmprs_irq[3:0], x393_i.frseq_irq[3:0]};
wire [NUM_INTERRUPTS-1:0] IRQ_ACKN;
wire [3:0] IRQ_FRSEQ_ACKN = IRQ_ACKN[3:0];
......@@ -742,7 +746,7 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire [3:0] IRQ_CMPRS_S = IRQ_S[7:4];
wire IRQ_SATA_S = IRQ_S[8];// SuppressThisWarning VEditor - not used
*/
assign reset_out = RST || x393_i.arst;
x393 #(
// TODO: Are these parameters needed? They are included in x393 from the save x393_parameters.vh
......@@ -1649,7 +1653,7 @@ simul_axi_hp_wr #(
.VACT (PX4_VACT), // output
.VACT1 () // output
);
/*
sim_soc_interrupts #(
.NUM_INTERRUPTS (NUM_INTERRUPTS)
) sim_soc_interrupts_i (
......@@ -1663,7 +1667,7 @@ simul_axi_hp_wr #(
.inta (IRQ_ACKN), // output[7:0]
.main_go (MAIN_GO) // output
);
*/
// Initilize simulation
`ifndef ROOTPATH
......@@ -1678,7 +1682,7 @@ simul_axi_hp_wr #(
$display(`ROOTPATH);
$display({`ROOTPATH,"/",`DATAPATH});
RST_CLEAN = 1;
// RST_CLEAN = 1;
RST = 1'bx;
$display("%t %s:%d RST=1'bx",$time,`__FILE__,`__LINE__);
#500;
......@@ -1689,14 +1693,16 @@ simul_axi_hp_wr #(
RST =1'b0;
$display("%t %s:%d RST=1'b0",$time,`__FILE__,`__LINE__);
@(posedge CLK) ;
RST_CLEAN = 0;
$display("%t %s:%d RST_CLEAN=1'b0",$time,`__FILE__,`__LINE__);
// RST_CLEAN = 0;
// $display("%t %s:%d RST_CLEAN=1'b0",$time,`__FILE__,`__LINE__);
// IRQ-related
/*
IRQ_EN = 1;
IRQ_M = 0;
IRQ_FRSEQ_DONE = 0;
IRQ_CMPRS_DONE = 0;
IRQ_SATA_DONE = 0;
*/
#5000;
// Need to killall vvp
// $finish;
......
cocotb/x393interfaces.py
View file @ 05a118d9
......@@ -55,7 +55,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. '''
import cocotb
from cocotb.triggers import Timer, RisingEdge, ReadOnly, Lock
from cocotb.triggers import Timer, RisingEdge, FallingEdge, Edge, ReadOnly, Lock
from cocotb.drivers import BusDriver
from cocotb.result import ReturnValue
from cocotb.binary import BinaryValue
......@@ -64,6 +64,7 @@ import re
import binascii
import array
import struct
#import logging
#channels
AR_CHN="AR"
......@@ -72,13 +73,15 @@ R_CHN="R"
W_CHN="W"
B_CHN="B"
def _float_signals(self,signals):
def _float_signals(signals):
if not isinstance (signals,(list,tuple)):
signals = (signals,)
for signal in signals:
v = signal.value
v.binstr = "z" * len(signal)
signal <= v
class MAXIGPReadError(Exception):
# print ("MAXIGPReadError")
......@@ -89,18 +92,19 @@ class PSBus(BusDriver):
Small subset of Zynq registers, used to access SAXI_HP* registers
"""
_signals=[ # i/o from the DUT side
clk, # output
addr, # input [31:0]
wr, # input
rd, # input
din, # input [31:0]
dout] #output [31:0]
"clk", # output
"addr", # input [31:0]
"wr", # input
"rd", # input
"din", # input [31:0]
"dout"] #output [31:0]
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.busy_channel = Lock("%s_busy"%(name))
self.bus.wr.setimmediatevalue(0)
self.bus.rd.setimmediatevalue(0)
_float_signals((self.bus.addr, self.bus.din))
self.name = name
@cocotb.coroutine
def write_reg(self,addr,data):
......@@ -167,20 +171,36 @@ class SAXIWrSim(BusDriver):
@param autoflush flush file after each write
@param blatency number of cycles to delay write response (b) channel
"""
# self.log.setLevel(logging.DEBUG)
BusDriver.__init__(self, entity, name, clock)
self.log.debug ("SAXIWrSim.__init__(): super done")
self._memfile=open(mempath, 'w+')
self.name = name
self.log.debug ("SAXIWrSim: name='%s', mempath='%s', memhigh=0x%08x, data_bytes=%d, autoflush=%s, blatency=%d"%
(name,mempath,memhigh,data_bytes, str(autoflush), blatency))
# self.log.debug ("SAXIWrSim.__init__(): super done")
#Open file to use as system memory
try:
self._memfile=open(mempath, 'r+') #keep old file if it exists already
except:
self._memfile=open(mempath, 'w+') #create a new file if it does not exist
self.log.info ("SAXIWrSim(%s): created a new 'memory' file %s"%(name,mempath)) #
#Extend to full size
self._memfile.seek(memhigh-1)
readOK=False
try:
self._memfile.read(1)
readOK = len(self._memfile.read(1))>0
self.log.debug ("Read from 0x%08x"%(memhigh-1)) #
except:
pass
if not readOK:
self._memfile.seek(memhigh-1)
self._memfile.write(chr(0))
self._memfile.flush()
self.log.info("Wrote to 0x%08x to extend file to full size"%(memhigh-1)) #
self.autoflush=autoflush
self.bus.wr_ready.setimmediatevalue(1) # always ready
self.bresp_latency = blatency
self.bus.bresp_latency.setimmediatevalue(blatency)
if data_bytes > 4:
self._data_bytes = 8
self._address_lsb = 3
......@@ -197,12 +217,14 @@ class SAXIWrSim(BusDriver):
self._data_bytes = 1
self._address_lsb = 0
self._fmt= "<B"
self.log.debug ("SAXIWrSim(%s) init done"%(self.name))
def flush(self):
self._memfile.flush()
@cocotb.coroutine
def saxi_wr_run(self):
self.log.debug ("SAXIWrSim(%s).saxi_wr_run"%(self.name))
while True:
if not self.bus.wr_ready.value:
break #exit
......@@ -278,9 +300,33 @@ class SAXIRdSim(BusDriver):
@param data_bytes data width, in bytes
"""
# self.log.setLevel(logging.DEBUG)
BusDriver.__init__(self, entity, name, clock)
self.log.debug ("SAXIWrSim.__init__(): super done")
self._memfile=open(mempath, 'r+')
self.name = name
self.log.debug ("SAXIRdSim: name='%s', mempath='%s', memhigh=0x%08x, data_bytes=%d"%
(name,mempath,memhigh,data_bytes))
# self._memfile=open(mempath, 'r+')
#Open file to use as system memory
try:
self._memfile=open(mempath, 'r+') #keep old file if it exists already
except:
self._memfile=open(mempath, 'w+') #create a new file if it does not exist
self.log.info ("SAXIRdSim(%s): created a new 'memory' file %s"%(name,mempath)) #
#Extend to full size
self._memfile.seek(memhigh-1)
readOK=False
try:
readOK = len(self._memfile.read(1))>0
self.log.debug ("Read from 0x%08x"%(memhigh-1)) #
except:
pass
if not readOK:
self._memfile.seek(memhigh-1)
self._memfile.write(chr(0))
self._memfile.flush()
self.log.info("Wrote to 0x%08x to extend file to full size"%(memhigh-1)) #
self.bus.rd_valid.setimmediatevalue(0)
if data_bytes > 4:
......@@ -299,9 +345,16 @@ class SAXIRdSim(BusDriver):
self._data_bytes = 1
self._address_lsb = 0
self._fmt= "<B"
self.log.debug("SAXIRdSim(%s) init done"%(self.name))
@cocotb.coroutine
def saxi_test(self):
self.log.info ("SAXIRdSim(%s).saxi_test"%(self.name))
yield Timer(1000)
@cocotb.coroutine
def saxi_rd_run(self):
self.log.info ("SAXIRdSim(%s).saxi_wr_run"%(self.name))
while True:
# if not self.bus.rd_valid.value:
# break #exit
......@@ -404,6 +457,8 @@ class MAXIGPMaster(BusDriver):
_channels = [AR_CHN,AW_CHN,R_CHN,W_CHN,B_CHN]
def __init__(self, entity, name, clock, rdlag=None, blag=None):
BusDriver.__init__(self, entity, name, clock)
# self.log.setLevel(logging.DEBUG)
self.name = name
# set read and write back channels simulation lag between AXI sets valid and host responds with
# ready. If None - drive these signals
self.log.debug ("MAXIGPMaster.__init__(): super done")
......@@ -429,7 +484,7 @@ class MAXIGPMaster(BusDriver):
self.bus.awprot.setimmediatevalue(0)
self.bus.awqos.setimmediatevalue(0)
self.busy_channels = {}
self.log.debug ("MAXIGPMaster.__init__(): pre-lcok done")
self.log.debug ("MAXIGPMaster.__init__(): pre-lock done")
#Locks on each subchannel
for chn in self._channels:
......
py393/cocoargs
View file @ 05a118d9
-d TARGET_MODE=1
-f system_defines.vh
-f includes/x393_parameters.vh includes/x393_cur_params_target.vh includes/x393_localparams.vh includes/x393_simulation_parameters.vh
-f includes/x393_parameters.vh includes/x393_cur_params_target_simulation.vh includes/x393_localparams.vh includes/x393_simulation_parameters.vh
-l includes/x393_cur_params_target_gen.vh
-l includes/x393_cur_params_target_gen.vh
-p PICKLE="includes/x393_mcntrl.pickle"
......
py393/x393_cmprs.py
View file @ 05a118d9
......@@ -267,6 +267,85 @@ class X393Cmprs(object):
focus_mode = focus_mode)
self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CONTROL_REG,
data)
def compressor_interrupt_control (self,
chn,
cntrl = "clr"):
"""
Control compressor interrupts
@param chn - compressor channel number, "a" or "all" - same for all 4 channels
@param cntrl - "clr" - clear, "en" - enable, "dis" - disable
"""
# print("compressor_interrupt_control(",chn,", ",cntrl,")")
try:
if (chn == all) or (chn[0].upper() == "A"): #all is a built-in function
for chn in range(4):
self.compressor_interrupt_control (chn = chn,
cntrl = cntrl)
return
except:
pass
if cntrl.lower() == "clr":
data = 1
elif cntrl.lower() == "dis":
data = 2
elif cntrl.lower() == "en":
data = 3
else:
print ("compressor_interrupts(): invalid control mode: %s, only 'clr', 'en' and 'dis' are accepted"%(str(cntrl)))
return
self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_INTERRUPTS,
data)
def compressor_interrupt_acknowledge (self, enabledOnly=True):
"""
Clear (one of) raised compressor interrupts
@param enabledOnly consider only channels with interrupts enabled
@return number of cleared interrupt, None if none was set
"""
d = 0 if enabledOnly else 2
for chn in range(4):
if ((self.get_status_compressor(chn) | d) & 3) == 3: # both request and mask are set
self.compressor_interrupt_control(chn, "clr")
return chn
return None
def get_status_compressor ( self,
chn="All"):
"""
Read compressor status word
@param chn - compressor port (0..3)
@return status word
"""
try:
if (chn == all) or (chn[0].upper() == "A"): #all is a built-in function
rslt = []
for chn in range(4):
rslt.append(self.get_status_compressor (chn = chn))
return rslt
except:
pass
return self.x393_axi_tasks.read_status(
address=(vrlg.CMPRS_STATUS_REG_BASE + chn * vrlg.CMPRS_STATUS_REG_INC))
def get_highfreq_compressor ( self,
chn="All"):
"""
Read total high frequency amount from the compressor
@param chn - compressor port (0..3)
@return status word
"""
try:
if (chn == all) or (chn[0].upper() == "A"): #all is a built-in function
rslt = []
for chn in range(4):
rslt.append(self.get_highfreq_compressor (chn = chn))
return rslt
except:
pass
return self.x393_axi_tasks.read_status(
address=(vrlg.CMPRS_HIFREQ_REG_BASE + num_sensor * vrlg.CMPRS_STATUS_REG_INC))
def setup_compressor_memory (self,
num_sensor,
frame_sa,
......
py393/x393_cmprs_afi.py
View file @ 05a118d9
......@@ -93,7 +93,7 @@ class X393CmprsAfi(object):
"""
# print ("status reg = 0x%x"%(((vrlg.CMPRS_AFIMUX_REG_ADDR0, vrlg.CMPRS_AFIMUX_REG_ADDR1)[port_afi]+channel) ))
# print ("status reg data = 0x%x"%(self.x393_axi_tasks.read_status((vrlg.CMPRS_AFIMUX_REG_ADDR0, vrlg.CMPRS_AFIMUX_REG_ADDR1)[port_afi]+channel) ))
if (self.DRY_MODE):
if self.DRY_MODE == True:
return None
return 32*(self.x393_axi_tasks.read_status((vrlg.CMPRS_AFIMUX_REG_ADDR0, vrlg.CMPRS_AFIMUX_REG_ADDR1)[port_afi]+channel) & 0x3ffffff)
......
py393/x393_jpeg.py
View file @ 05a118d9
......@@ -44,6 +44,7 @@ import x393_cmprs
import x393_cmprs_afi
import vrlg
import time
import os
STD_QUANT_TBLS = {
"Y_landscape":( 16, 11, 10, 16, 24, 40, 51, 61,
12, 12, 14, 19, 26, 58, 60, 55,
......@@ -763,6 +764,11 @@ class X393Jpeg(object):
self.x393_sens_cmprs.specify_window(verbose = 2)
return numChannels
def _get_project_root(self):
"""
@return absolute path of the directory one above current script one
"""
return os.path.abspath(os.path.join(os.path.dirname(__file__), '../'))
def jpeg_write(self,
file_path = "img.jpeg",
channel = 0,
......@@ -776,7 +782,7 @@ class X393Jpeg(object):
"""
Create JPEG image from the latest acquired in the camera
@param file_path - camera file system path (starts with "/") or relative to web server root
@param channel - compressor channel
@param channel - compressor channel
@param y_quality - 1..100 - quantization quality for Y component
@param c_quality - 1..100 - quantization quality for color components (None - use y_quality)
@param portrait - False - use normal order, True - transpose for portrait mode images
......@@ -784,9 +790,29 @@ class X393Jpeg(object):
@param server_root - files ystem path to the web server root directory
@param verbose - verbose level
"""
useNextReady = False
try:
if (channel == next) or (channel[0].upper() == "N"): #next is a built-in function
useNextReady = True
except:
pass
if useNextReady:
channel = self.x393Cmprs.compressor_interrupt_acknowledge(enabledOnly=True)
if channel is None:
raise Exception ("No channels have new compressed images ready")
else:
schn="-"+str(channel)
if '@' in file_path:
file_path=file_path[:file_path.rindex('@')+1]+schn+file_path[file_path.rindex('@')+1:] #insert after after '@' (keep @ to be replaced by a timestamp)
elif '.' in file_path:
file_path=file_path[:file_path.rindex('.')]+schn+file_path[file_path.rindex('.'):] #insert before '.'
print("Channel %d has JPEG image ready, using path %s"%(channel, file_path))
#change image name
if server_root is None:
if (self.DRY_MODE):
server_root = "../www/"
server_root = self._get_project_root()+"/www/"
if not os.path.exists(server_root):
os.mkdir(server_root)
else:
server_root = "/www/pages/"
allFiles = False
......@@ -867,7 +893,7 @@ class X393Jpeg(object):
color_mode = window["cmode"], #color_mode,
byrshift = byrshift,
verbose = verbose - 1)
if self.DRY_MODE:
if self.DRY_MODE == True:
meta = self.x393_cmprs_afi.afi_mux_get_image_meta(
port_afi = SIMULATION_JPEG_DATA, # 0,
channel = channel,
......@@ -875,6 +901,8 @@ class X393Jpeg(object):
circbuf_len = 0, #x393_sens_cmprs.GLBL_CIRCBUF_ENDS[channel] - x393_sens_cmprs.GLBL_CIRCBUF_STARTS[channel],
verbose = verbose)
else:
if self.DRY_MODE: # only with socket connection
self.x393_mem.flush_simulation()# Same as sync_for_cpu() ?
meta = self.x393_cmprs_afi.afi_mux_get_image_meta(
port_afi = 0,
channel = channel,
......@@ -888,6 +916,9 @@ class X393Jpeg(object):
if verbose > 1 :
for s in meta["segments"]:
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
if "@" in file_path:
fts=("%f"%(meta["timestamp"])).replace(".","_")
file_path=file_path[:file_path.rindex('@')]+fts+file_path[file_path.rindex('@')+1:] #replacing '@'
with open (server_root+file_path, "w+b") as bf:
bf.write(jpeg_data["header"])
for s in meta["segments"]:
......@@ -1064,6 +1095,31 @@ compressor_control all 2
jpeg_write "img.jpeg" 0 85
################## Simulate Serial ####################
measure_all "*DI"
setup_all_sensors True None 0xf
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
wait_irq 0xf0 100000
wait_irq 0x0 100
jpeg_write "img@.jpeg" next
jpeg_write "/home/eyesis/git/x393-neon/www/img.jpeg" next
x393 (localhost:7777) +107.289s--> compressor_control all None None None None None 2
x393 (localhost:7777) +0.647s--> compressor_interrupt_control all clr
x393 (localhost:7777) +0.150s--> compressor_interrupt_control all en
x393 (localhost:7777) +0.589s--> compressor_interrupt_control 0 en
x393 (localhost:7777) +0.153s--> compressor_interrupt_control 1 en
x393 (localhost:7777) +0.147s--> compressor_interrupt_control 2 en
x393 (localhost:7777) +0.150s--> compressor_interrupt_control 3 en
x393 (localhost:7777) +0.162s--> compressor_control all 3
################## Serial ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs
bitstream_set_path /usr/local/verilog/x393_hispi.bit
......
py393/x393_mcntrl_membridge.py
View file @ 05a118d9
......@@ -109,8 +109,8 @@ class X393McntrlMembridge(object):
except:
pass
if dry_mode:
BUFFER_ADDRESS=0x27900000
BUFFER_LEN= 0x6400000
BUFFER_ADDRESS=0x25500000
BUFFER_LEN= 0x19000000
print ("Running in simulated mode, using hard-coded addresses:")
else:
try:
......
py393/x393_mem.py
View file @ 05a118d9
......@@ -133,7 +133,35 @@ class X393Mem(object):
else:
X393_CLIENT.stop()
X393_CLIENT = True # just simulated mode
def flush_simulation(self):
"""
Flush simulation 'system memory" file
"""
global X393_CLIENT
if X393_CLIENT is None:
print ("flush_simulation(): Not running in simulated mode")
return
elif X393_CLIENT is True:
print ("flush_simulation(): Not running as a client to x393 simulation server")
return
else:
X393_CLIENT.flush()
def wait_irq(self,irq_mask= 0, wait_ns = 1000):
"""
Wait silation certain time, interruptible
@param irq_mask - mask to be AND-ed with interrupt vector
@param wait_ns - timeout in nanoseconds
"""
global X393_CLIENT
if X393_CLIENT is None:
print ("wait_irq(): Not running in simulated mode")
return
elif X393_CLIENT is True:
print ("wait_irq(): Not running as a client to x393 simulation server")
return
else:
X393_CLIENT.waitIrq(irq_mask, wait_ns)
def write_mem (self,addr, data,quiet=1):
"""
Write 32-bit word to physical memory
......@@ -149,7 +177,7 @@ class X393Mem(object):
if quiet < 1:
print ("remote: write_mem(0x%x,0x%x)"%(addr,data))
X393_CLIENT.write(addr, [data])
if quiet < 2:
if quiet < 1:
print ("remote: write_mem done" )
return
with open("/dev/mem", "r+b") as f:
......@@ -280,9 +308,26 @@ class X393Mem(object):
@param start_addr physical byte start address
@param length - number of bytes to save
'''
if self.DRY_MODE:
if self.DRY_MODE == True:
print ("Write memory to file is not implemented in non-target mode")
return
elif self.DRY_MODE: # Cocotb over socket
first_page = start_addr // self.PAGE_SIZE
last_page = (start_addr + length - 1) // self.PAGE_SIZE
for page_num in range(first_page, last_page+1):
start_offset = 0
if page_num == first_page:
start_offset = start_addr - self.PAGE_SIZE * page_num
end_offset = self.PAGE_SIZE
if page_num == last_page:
end_offset = start_addr + length - self.PAGE_SIZE * page_num
page_addr = page_num * self.PAGE_SIZE
page_data= X393_CLIENT.read((page_addr, self.PAGE_SIZE//4)) # always read memory page (as in mmap)
mm = struct.pack("<"+("L"*(self.PAGE_SIZE//4)),*page_data)
bf.write(mm[start_offset:end_offset])
# mm = self.wrap_mm(f, page_addr)
# bf.write(mm[start_offset:end_offset])
return
with open("/dev/mem", "r+b") as f:
first_page = start_addr // self.PAGE_SIZE
last_page = (start_addr + length - 1) // self.PAGE_SIZE
......
py393/x393_sens_cmprs.py
View file @ 05a118d9
......@@ -154,11 +154,11 @@ class X393SensCmprs(object):
try:
if ":" in dry_mode:
print ("X393SensCmprs.__init__: setting SENSOR_DEFAULTS")
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["width"]= vrlg.WOI_WIDTH + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["width"]= vrlg.WOI_WIDTH + 2 # 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["height"]= vrlg.WOI_HEIGHT + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["top"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["left"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["width"]= vrlg.WOI_WIDTH + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["width"]= vrlg.WOI_WIDTH + 2 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["top"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["left"]= 0
......@@ -186,6 +186,7 @@ class X393SensCmprs(object):
except:
pass
if dry_mode:
"""
BUFFER_ADDRESS = 0x38100000
BUFFER_LEN = 0x06400000
BUFFER_ADDRESS_H2D = 0x38100000
......@@ -194,7 +195,18 @@ class X393SensCmprs(object):
BUFFER_LEN_D2H = 0x06400000
BUFFER_ADDRESS_BIDIR = 0x38100000
BUFFER_LEN_BIDIR = 0x06400000
print ("Running in simulated mode, using hard-coded addresses:")
"""
BUFFER_ADDRESS = 0x25500000
BUFFER_LEN = 0x19000000
BUFFER_ADDRESS_H2D = 0x25500000
BUFFER_LEN_H2D = 0x19000000
BUFFER_ADDRESS_D2H = 0x25500000
BUFFER_LEN_D2H = 0x19000000
BUFFER_ADDRESS_BIDIR = 0x25500000
BUFFER_LEN_BIDIR = 0x19000000
print ("Running in simulated mode, using hard-coded addresses:")
else:
......@@ -476,7 +488,7 @@ class X393SensCmprs(object):
if (window_top + window_height) % 8:
num8rows += 1
frame_start_address_inc = num8rows * frame_full_width
""" TODO: Calculate tiles and mov e to initial print """
""" TODO: Calculate tiles and move to initial print """
num_macro_cols_m1 = (window_width >> 4) - 1
num_macro_rows_m1 = (window_height >> 4) - 1
......@@ -499,7 +511,10 @@ class X393SensCmprs(object):
print ("frame_start_address_inc = 0x%x"%(frame_start_address_inc))
print ("histogram_start_phys_page = 0x%x"%(histogram_start_phys_page))
print ("histogram start address = 0x%x"%(histogram_start_phys_page * 4096))
print ("width_in_bursts = %d(0x%x)"%(width_in_bursts,width_in_bursts))
print ("num_burst_in_line = %d(0x%x)"%(num_burst_in_line,num_burst_in_line))
print ("num_pages_in_line = %d(0x%x)"%(num_pages_in_line,num_pages_in_line))
print ("num8rows = %d(0x%x)"%(num8rows,num8rows))
print ("last_buf_frame = ", last_buf_frame)
print ("num_macro_cols_m1 = ", num_macro_cols_m1)
print ("num_macro_rows_m1 = ", num_macro_rows_m1)
......@@ -531,7 +546,8 @@ class X393SensCmprs(object):
frame_sa_inc = frame_start_address_inc, # input [31:0] frame_sa_inc; # 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
last_frame_num = last_buf_frame, # input [31:0] last_frame_num; # 16-bit number of the last frame in a buffer
frame_full_width = frame_full_width, # input [31:0] frame_full_width; # 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width = window_width >> 4, # input [31:0] window_width; # 13 bit - in 8*16=128 bit bursts
# window_width = window_width >> 4, # input [31:0] window_width; # 13 bit - in 8*16=128 bit bursts
window_width = num_burst_in_line, # input [31:0] window_width; # 13 bit - in 8*16=128 bit bursts
window_height = window_height, # input [31:0] window_height; # 16 bit
window_left = window_left >> 4, # input [31:0] window_left;
window_top = window_top); # input [31:0] window_top;
......@@ -1173,7 +1189,7 @@ class X393SensCmprs(object):
histogram_top = None,
histogram_width_m1 = None, # 2559, #0,
histogram_height_m1 = None, # 799, #0,
circbuf_chn_size= 0x4000000, # 64 Mib
circbuf_chn_size= 0x4000000, # 64 Mib - all 4 channels?
verbose = 1):
"""
Setup one sensor+compressor channel (for one sub-channel only)
......@@ -1691,6 +1707,13 @@ class X393SensCmprs(object):
num8rows= (window_top + window_height) // 8
if (window_top + window_height) % 8:
num8rows += 1
if verbose >0 :
print ("width_in_bursts = %d(0x%x)"%(width_in_bursts,width_in_bursts))
print ("num_burst_in_line = %d(0x%x)"%(num_burst_in_line,num_burst_in_line))
print ("num_pages_in_line = %d(0x%x)"%(num_pages_in_line,num_pages_in_line))
print ("num8rows = %d(0x%x)"%(num8rows,num8rows))
# frame_start_addr = 0 # for sensor 0
# frame_start_address_inc = num8rows * frame_full_width
# len64 = num_burst_in_line * 2 * window_height
......@@ -2131,18 +2154,21 @@ class X393SensCmprs(object):
return "_bidir"
def sync_for_cpu(self, direction, saddr=None, leng=None):
if self.DRY_MODE:
print ("Simulating sync_for_cpu(),",self.get_mem_buf_args(saddr, leng)," -> ",MEM_PATH + BUFFER_FOR_CPU + self._get_dma_dir_suffix(direction))
self.x393_mem.flush_simulation()
#print ("Simulating sync_for_cpu(),",self.get_mem_buf_args(saddr, leng)," -> ",MEM_PATH + BUFFER_FOR_CPU + self._get_dma_dir_suffix(direction))
return
with open (MEM_PATH + BUFFER_FOR_CPU + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, leng),file=f)
def sync_for_device(self, direction, saddr=None, leng=None):
if self.DRY_MODE:
print ("Simulating sync_for_device(),",self.get_mem_buf_args(saddr, leng)," -> ",MEM_PATH + BUFFER_FOR_DEVICE + self._get_dma_dir_suffix(direction))
self.x393_mem.flush_simulation()
#print ("Simulating sync_for_device(),",self.get_mem_buf_args(saddr, leng)," -> ",MEM_PATH + BUFFER_FOR_DEVICE + self._get_dma_dir_suffix(direction))
return
with open (MEM_PATH + BUFFER_FOR_DEVICE + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, leng),file=f)
"""
flush_simulation
cd /usr/local/verilog/; test_mcntrl.py @hargs
#fpga_shutdown
setupSensorsPower "PAR12"
......@@ -2276,7 +2302,7 @@ jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3
# Above did not work, try disabling memory channel
self.x393_axi_tasks.enable_memcntrl_en_dis(8 + chn, False);
#Will restore defaulrt circbuf parameters
#Will restore default circbuf parameters
self.specify_phys_memory() # setup physical memory
#Overwrite CIRCBUF parameters for selected channel with D2H stream DMA buffer (shared with membridge)
......
py393/x393_sensor.py
View file @ 05a118d9
......@@ -144,7 +144,7 @@ class X393Sensor(object):
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
rslt = []
for num_sensor in range(4):
rslt.append(self.program_status_sensor_io (num_sensor = num_sensor))
rslt.append(self.get_status_sensor_io (num_sensor = num_sensor))
return rslt
except:
pass
......
util_modules/level_cross_clocks.v
View file @ 05a118d9
......@@ -40,7 +40,9 @@
module level_cross_clocks#(
parameter WIDTH = 1,
parameter REGISTER = 2 // number of registers (>=12)
parameter REGISTER = 2, // number of registers (>=12)
parameter FAST0 = 1'b0,
parameter FAST1 = 1'b0
)(
input clk,
input [WIDTH-1:0] d_in,
......@@ -50,20 +52,20 @@ module level_cross_clocks#(
genvar i;
for (i = 0; i < WIDTH ; i = i+1) begin: level_cross_clock_block
if (REGISTER <= 1)
level_cross_clocks_ff_bit level_cross_clocks_single_i ( // just a single ff (if metastability is not a problem)
level_cross_clocks_ff_bit #(.FAST1(FAST1)) level_cross_clocks_single_i ( // just a single ff (if metastability is not a problem)
.clk (clk), // input
.d_in (d_in[i]), // input
.d_out (d_out[i]) // output
);
else if (REGISTER == 2)
level_cross_clocks_sync_bit level_cross_clocks_sync_i ( // classic 2-register synchronizer
level_cross_clocks_sync_bit #(.FAST0(FAST0),.FAST1(FAST1)) level_cross_clocks_sync_i ( // classic 2-register synchronizer
.clk (clk), // input
.d_in (d_in[i]), // input
.d_out (d_out[i]) // output
);
else
level_cross_clocks_single_bit #( // >2 bits (first two only are synchronizer)
.REGISTER(REGISTER)
.REGISTER(REGISTER), .FAST0(FAST0), .FAST1(FAST1)
) level_cross_clocks_single_i (
.clk (clk), // input
.d_in (d_in[i]), // input
......@@ -74,20 +76,24 @@ module level_cross_clocks#(
endmodule
module level_cross_clocks_single_bit#(
parameter REGISTER = 3 // number of registers (>=3)
parameter REGISTER = 3, // number of registers (>=3)
parameter FAST0 = 1'b0,
parameter FAST1 = 1'b0
)(
input clk,
input d_in,
output d_out
);
reg [REGISTER - 3 : 0] regs = 0;
reg [REGISTER - 3 : 0] regs = {REGISTER -2 {FAST1}};
wire d_sync; // after a 2-bit synchronizer
wire [REGISTER - 2 : 0] regs_next = {regs, d_sync};
assign d_out = regs[REGISTER -3];
always @ (posedge clk) begin
regs <= regs_next[REGISTER - 3 : 0]; // | d_in complains about widths mismatch
if (FAST0) regs <= {REGISTER - 3{d_in}} & regs_next[REGISTER - 3 : 0];
else if (FAST1) regs <= {REGISTER - 3{d_in}} | regs_next[REGISTER - 3 : 0];
else regs <= regs_next[REGISTER - 3 : 0]; // | d_in complains about widths mismatch
end
level_cross_clocks_sync_bit level_cross_clocks_sync_bit_i (
level_cross_clocks_sync_bit #(.FAST0(FAST0),.FAST1(FAST1)) level_cross_clocks_sync_bit_i (
.clk (clk), // input
.d_in (d_in), // input
.d_out (d_sync) // output
......@@ -95,7 +101,10 @@ module level_cross_clocks_single_bit#(
endmodule
// Classic 2-bit (exactly) synchronizer
module level_cross_clocks_sync_bit(
module level_cross_clocks_sync_bit #(
parameter FAST0 = 1'b0,
parameter FAST1 = 1'b0
)(
input clk,
input d_in,
output d_out
......@@ -106,17 +115,23 @@ module level_cross_clocks_sync_bit(
reg [1:0] sync_zer;
assign d_out = sync_zer [1];
always @ (posedge clk) begin
sync_zer <= {sync_zer[0],d_in};
if (FAST0) sync_zer <= {sync_zer[0] & d_in, d_in};
else if (FAST1) sync_zer <= {sync_zer[0] | d_in, d_in};
else sync_zer <= {sync_zer[0],d_in};
end
endmodule
module level_cross_clocks_ff_bit( // just a single FF if REGISTER == 1 (if metastability is not a problem)
module level_cross_clocks_ff_bit #( // just a single FF if REGISTER == 1 (if metastability is not a problem)
parameter FAST1 = 1'b0
) (
input clk,
input d_in,
output reg d_out
output d_out
);
reg d_out_r = FAST1;
assign d_out = d_out_r;
always @ (posedge clk) begin
d_out <= d_in;
d_out_r <= d_in;
end
endmodule
......
util_modules/sync_resets.v
View file @ 05a118d9
......@@ -63,7 +63,7 @@ module sync_resets#(
else mrst <= ~(locked[0] && en_locked);
end
always @(posedge clk[0]) begin
rst_early_master <= rst_early_master_w;
rst_early_master <= rst_early_master_w | mrst;
end
level_cross_clocks #(
.WIDTH (1),
......@@ -79,7 +79,9 @@ module sync_resets#(
for (i = 1; i < WIDTH; i = i + 1) begin: rst_block
level_cross_clocks #(
.WIDTH (1),
.REGISTER ((i==5) ? 1: REGISTER) // disable for aclk
.REGISTER ((i==5) ? 1: REGISTER), // disable for aclk
// .REGISTER (REGISTER), // disable for aclk - aclk is now (0)
.FAST1 (1) // Switch to next cycle, to 0 - regeisterd
) level_cross_clocks_rst_i (
.clk (clk[i]), // input
.d_in (mrst || rst_early_master || ~locked[i] ), // input[0:0]
......
wrap/mmcm_phase_cntr.v
View file @ 05a118d9
......@@ -132,24 +132,26 @@ module mmcm_phase_cntr#(
// made a difference, so it doesn't seem Vivado extends bits of operands "+", "-"
wire [PHASE_WIDTH:0] diff= {ps_target[PHASE_WIDTH-1],ps_target}-{ps_dout_r[PHASE_WIDTH-1],ps_dout_r};
assign ps_dout = ps_dout_r;
wire reset_extended = rst || !locked;
always @ (posedge psclk) begin
if (rst) ps_start0 <= 0;
else ps_start0 <= ps_we && ps_ready;
if (reset_extended) ps_start0 <= 0;
else ps_start0 <= ps_we && ps_ready;
if (rst) ps_dout_r <= 0;
if (reset_extended) ps_dout_r <= 0;
else if (psen && psincdec) ps_dout_r <= ps_dout_r +1; //SuppressThisWarning ISExst Result of 9-bit expression is truncated to fit in 8-bit target.
else if (psen && !psincdec) ps_dout_r <= ps_dout_r -1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 8-bit target.
if (rst) ps_target <= 0;
if (reset_extended) ps_target <= 0;
else if (ps_we && ps_ready) ps_target <= ps_din;
if (rst) ps_busy <= 1'b0;
else if (ps_start) ps_busy <= (diff!=0);
if (reset_extended) ps_busy <= 1'b0;
else if (ps_start) ps_busy <= (diff!=0);
end
always @ (posedge psclk) begin
ps_start <= ps_start0 || psdone;
ps_start <= !reset_extended && (ps_start0 || psdone);
psincdec <= !diff[PHASE_WIDTH];
end
......
x393.v
View file @ 05a118d9
......@@ -2476,7 +2476,6 @@ assign axi_grst = axi_rst_pre;
.locked_pclk (locked_pclk), // output
.locked_hclk (locked_hclk) // output
);
sync_resets #(
.WIDTH(7),
.REGISTER(4)
......@@ -2487,6 +2486,19 @@ assign axi_grst = axi_rst_pre;
.rst ({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[6:0]
);
// Changed aclk to master (itg is the source of most orthers)
/*
sync_resets #(
.WIDTH(7),
.REGISTER(4)
) sync_resets_i (
.arst (axi_rst_pre), // input
.locked ({locked_hclk, locked_sync_clk, locked_sync_clk, locked_xclk, locked_pclk, mcntrl_locked, 1'b1 }), // input
.clk ({hclk, logger_clk, camsync_clk, xclk, pclk, mclk, axi_aclk}), // input[6:0]
.rst ({hrst, lrst, crst, xrst, prst, mrst, arst}) // output[6:0]
);
*/
`ifdef DEBUG_RING
debug_master #(
.DEBUG_ADDR (DEBUG_ADDR),
......
x393_testbench03.tf
View file @ 05a118d9
......@@ -113,7 +113,7 @@ module x393_testbench03 #(
parameter TRIGGER_MODE = 0; // 1; // 0 - auto, 1 - triggered
parameter EXT_TRIGGER_MODE = 1 ; // 0 - internal, 1 - external trigger (camsync)
parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - embed received timestamp
parameter NUM_INTERRUPTS = 9;
//parameter NUM_INTERRUPTS = 9;
`include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used
// VDT - incorrect real number calculation
......@@ -1405,7 +1405,8 @@ end
initial begin
// after 1 frame compressed on all channels
// Debugging DCT Chen
//#20000;
//$finish;
`ifdef HISPI
#135000;
`else
......
x393_testbench04.sav
View file @ 05a118d9
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Jun 28 14:16:28 2016
[*] Sat Jul 9 20:52:38 2016
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160627204141983.fst"
[dumpfile_mtime] "Tue Jun 28 03:05:44 2016"
[dumpfile_size] 153062065
[savefile] "/home/andrey/git/x393/x393_testbench04.sav"
[timestart] 26395200
[size] 1736 1145
[pos] 1920 38
*-16.746853 26660000 209370000 209396667 209423333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_testbench03-20160708085728438.fst"
[dumpfile_mtime] "Fri Jul 8 15:12:58 2016"
[dumpfile_size] 152798280
[savefile] "/home/eyesis/git/x393-neon/x393_testbench04.sav"
[timestart] 0
[size] 1920 1171
[pos] 0 24
*-24.427032 91816667 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.read_compressor_frame_irq.
[treeopen] x393_testbench03.read_contol_register_irq.
......@@ -18,8 +18,7 @@
[treeopen] x393_testbench03.x393_i.
[treeopen] x393_testbench03.x393_i.cmd_mux_i.
[treeopen] x393_testbench03.x393_i.cmd_seq_mux_i.status_generate_cmd_seq_mux_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_in_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.
......@@ -30,13 +29,10 @@
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_ma2_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage1_i.dsp_ma2_i.DSP48E1_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_macroblock_buf_iface_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.dct2d8x8_chen_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.
......@@ -47,21 +43,35 @@
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_generate1_i.genblk2.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_generate1_i.genblk2.status_generate_only_i.
[treeopen] x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.cmda_cke_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_membuf_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sensor_i2c_io_i.
[sst_width] 395
[signals_width] 334
[treeopen] x393_testbench03.x393_i.sync_resets_i.
[treeopen] x393_testbench03.x393_i.sync_resets_i.rst_block[5].
[treeopen] x393_testbench03.x393_i.sync_resets_i.rst_block[5].level_cross_clocks_rst_i.
[treeopen] x393_testbench03.x393_i.sync_resets_i.rst_block[5].level_cross_clocks_rst_i.level_cross_clock_block[0].
[sst_width] 321
[signals_width] 348
[sst_expanded] 1
[sst_vpaned_height] 356
[sst_vpaned_height] 642
@820
x393_testbench03.TEST_TITLE[639:0]
@28
......@@ -74,10 +84,154 @@ x393_testbench03.x393_i.ps7_i.MAXIGP0ARQOS[3:0]
@28
x393_testbench03.AR_SET_CMD
x393_testbench03.AR_READY
@29
x393_testbench03.ARSIZE_IN_r[1:0]
@c00200
-memory_timing
@22
x393_testbench03.x393_i.cmd_mux_i.waddr[13:0]
x393_testbench03.x393_i.cmd_mux_i.wdata[31:0]
@28
x393_testbench03.x393_i.cmd_mux_i.wr_en
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst_in
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mrst
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dci_rst
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr_rst
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dly_addr[6:0]
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dly_data[7:0]
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ld_delay
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ld_mmcm
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start0
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ps_rdy
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ps_out[7:0]
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.set
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.locked_mmcm
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.locked_pll
@200
-
@c00022
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
(1)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
(2)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
(3)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
(4)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
(5)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
(6)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
(7)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
@1401200
-group_end
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dly_data[7:0]
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.set_idelay
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.set_odelay
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ld_odelay
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ld_idelay
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dq[15:0]
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsl
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsu
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_a[14:0]
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_ba[2:0]
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_cas
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_cke
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_clk
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_nclk
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_nrst
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_odt
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_ras
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr3_we
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.ddr_rst
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk_pre
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.sdclk
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.cmda_cke_i.clk
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.cmda_cke_i.clk_div
x393_testbench03.x393_i.mclk
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.in_cke_r[1:0]
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.cmda_cke_i.dq
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.ld_delay
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ld_delay
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_ad[7:0]
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_stb
@200
-
@1401200
-memory_timing
@c00200
-resets
@28
x393_testbench03.x393_i.axi_rst_pre
@800022
x393_testbench03.x393_i.sync_resets_i.locked[6:0]
@28
(0)x393_testbench03.x393_i.sync_resets_i.locked[6:0]
(1)x393_testbench03.x393_i.sync_resets_i.locked[6:0]
(2)x393_testbench03.x393_i.sync_resets_i.locked[6:0]
(3)x393_testbench03.x393_i.sync_resets_i.locked[6:0]
(4)x393_testbench03.x393_i.sync_resets_i.locked[6:0]
(5)x393_testbench03.x393_i.sync_resets_i.locked[6:0]
(6)x393_testbench03.x393_i.sync_resets_i.locked[6:0]
@1001200
-group_end
@800022
x393_testbench03.x393_i.sync_resets_i.clk[6:0]
@28
(0)x393_testbench03.x393_i.sync_resets_i.clk[6:0]
(1)x393_testbench03.x393_i.sync_resets_i.clk[6:0]
(2)x393_testbench03.x393_i.sync_resets_i.clk[6:0]
(3)x393_testbench03.x393_i.sync_resets_i.clk[6:0]
(4)x393_testbench03.x393_i.sync_resets_i.clk[6:0]
(5)x393_testbench03.x393_i.sync_resets_i.clk[6:0]
(6)x393_testbench03.x393_i.sync_resets_i.clk[6:0]
@1001200
-group_end
@800022
x393_testbench03.x393_i.sync_resets_i.rst[6:0]
@28
(0)x393_testbench03.x393_i.sync_resets_i.rst[6:0]
(1)x393_testbench03.x393_i.sync_resets_i.rst[6:0]
(2)x393_testbench03.x393_i.sync_resets_i.rst[6:0]
(3)x393_testbench03.x393_i.sync_resets_i.rst[6:0]
(4)x393_testbench03.x393_i.sync_resets_i.rst[6:0]
(5)x393_testbench03.x393_i.sync_resets_i.rst[6:0]
(6)x393_testbench03.x393_i.sync_resets_i.rst[6:0]
x393_testbench03.x393_i.sync_resets_i.mrst
x393_testbench03.x393_i.sync_resets_i.rst_early_master
x393_testbench03.x393_i.sync_resets_i.rst_early_master_w
x393_testbench03.x393_i.sync_resets_i.en_locked
@c00022
x393_testbench03.x393_i.sync_resets_i.rst_w[6:0]
@28
(0)x393_testbench03.x393_i.sync_resets_i.rst_w[6:0]
(1)x393_testbench03.x393_i.sync_resets_i.rst_w[6:0]
(2)x393_testbench03.x393_i.sync_resets_i.rst_w[6:0]
(3)x393_testbench03.x393_i.sync_resets_i.rst_w[6:0]
(4)x393_testbench03.x393_i.sync_resets_i.rst_w[6:0]
(5)x393_testbench03.x393_i.sync_resets_i.rst_w[6:0]
(6)x393_testbench03.x393_i.sync_resets_i.rst_w[6:0]
@1401200
-group_end
@1001200
-group_end
@200
-
@28
x393_testbench03.x393_i.sync_resets_i.rst_block[5].level_cross_clocks_rst_i.d_in
x393_testbench03.x393_i.sync_resets_i.rst_block[5].level_cross_clocks_rst_i.d_out
@1401200
-resets
@800200
-sensor_hispi
-chn1
......@@ -88,6 +242,9 @@ x393_testbench03.PX1_HACT
x393_testbench03.PX1_VACT
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sns_dp[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.pclk
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.pxd[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sof
......@@ -95,6 +252,22 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.eo
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.hact
@1000200
-chn1
@800200
-sensor_memory
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_membuf_i.mclk
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_membuf_i.buf_dout[63:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_membuf_i.buf_rd
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_we
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_a[3:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_data[31:0]
@200
-
@1000200
-sensor_memory
@c00200
-chn2
@22
......@@ -127,6 +300,153 @@ x393_testbench03.PX4_VACT
@1000200
-sensor_hispi
@800200
-compressor_channel0
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.mclk
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_din[63:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_we
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_ra[11:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_pxd[7:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_rd[1:0]
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.signed_y[8:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.signed_c[8:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.ywe
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cwe
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_nodc[9:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_avr[8:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_start
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_pre_first_out
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_out[12:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quant_do[12:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quant_ds
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.focus_do[12:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.focus_ds
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.first_block_quant
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enc_do[15:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enc_dv
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_do[31:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_dv
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_out_fifo_i.wdata[31:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_rst
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_ren
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_rdata[63:0]
@8022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_count[7:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hclk
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hrst
@1000200
-compressor_channel0
@c00200
-afi0_mux
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmd_we
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmd_a[3:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmd_data[31:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awaddr[31:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awburst[1:0]
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awcache[3:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awid[5:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awid_r[5:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awlen[3:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awlock[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awprot[2:0]
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awqos[3:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awready
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awsize[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awvalid
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_bid[5:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_bready
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_bresp[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_bvalid
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wacount[5:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wcount[7:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wdata[63:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wid[5:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wlast
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wready
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wrissuecap1en
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wstrb[7:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wvalid
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.awvalid[1:0]
@200
-
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.pre_busy_w
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.busy[3:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.ready_to_start
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.ptr_resetting
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.need_to_bother
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.counts_corr2[8:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.counts_corr1[17:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.counts_corr0[35:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_count0[7:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.en_chn[3:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.ren_suspend_flush[3:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_ren0
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_flush0
@8022
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_count0[7:0]
@1401200
-afi0_mux
@800200
-simul_axi_hp1_wr
@200
-
@23
x393_testbench03.simul_axi_hp1_wr_i.sim_bresp_latency[3:0]
x393_testbench03.simul_axi_hp1_wr_i.sim_wid[5:0]
x393_testbench03.simul_axi_hp1_wr_i.sim_wr_address[31:0]
@29
x393_testbench03.simul_axi_hp1_wr_i.sim_wr_cap[2:0]
@23
x393_testbench03.simul_axi_hp1_wr_i.sim_wr_data[63:0]
x393_testbench03.simul_axi_hp1_wr_i.sim_wr_qos[3:0]
@29
x393_testbench03.simul_axi_hp1_wr_i.sim_wr_ready
@23
x393_testbench03.simul_axi_hp1_wr_i.sim_wr_stb[7:0]
@29
x393_testbench03.simul_axi_hp1_wr_i.sim_wr_valid
@1000200
-simul_axi_hp1_wr
@800200
-sim_afi1
@22
x393_testbench03.sim_cmprs0_addr[31:0]
......@@ -1089,7 +1409,7 @@ x393_testbench03.read_status_irq.rslt[31:0]
@1401200
-group_end
-other_dbg
@800200
@c00200
-all_sensor_data
@22
x393_testbench03.PX1_D[11:0]
......@@ -1150,7 +1470,7 @@ x393_testbench03.CAPTURED_SENSORS[3:0]
@1001200
-group_end
-group_end
@1000200
@1401200
-all_sensor_data
@c00200
-membridge
......@@ -1529,7 +1849,7 @@ x393_testbench03.x393_i.sens_rpage_set[3:0]
-group_end
@1401200
-top
@c00200
@800200
-mcntrl393
@22
x393_testbench03.x393_i.mcntrl393_i.sens_rpage_set[3:0]
......@@ -1555,7 +1875,6 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
-
@1000200
-mcntrl_linear_wr_sensor
@1401200
-mcntrl393
@c00200
-all_channels
......
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