Commit 02f89609 authored by Andrey Filippov's avatar Andrey Filippov

debugging recover from corrupted image acquisition (i.e. wrong serial port setup)

parent e367007a
...@@ -3,6 +3,6 @@ VivadoBitstream_105_force=true ...@@ -3,6 +3,6 @@ VivadoBitstream_105_force=true
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true VivadoBitstream_124_force=true
VivadoBitstream_124_rawfile=x393_parallel VivadoBitstream_124_rawfile=x393_hispi
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@-> com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
...@@ -32,7 +32,11 @@ ...@@ -32,7 +32,11 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*******************************************************************************/ *******************************************************************************/
parameter FPGA_VERSION = 32'h0393008f; // parallel, all the same parameter FPGA_VERSION = 32'h03930093; // hispi, masking sesnor data to memory buffer, debug still on
// parameter FPGA_VERSION = 32'h03930092; // hispi, even more debugging memory pages sens-> memory
// parameter FPGA_VERSION = 32'h03930091; // hispi, more debugging memory pages sens-> memory
// parameter FPGA_VERSION = 32'h03930090; // hispi, debugging memory pages sens-> memory (not met)
// parameter FPGA_VERSION = 32'h0393008f; // parallel, all the same
// parameter FPGA_VERSION = 32'h0393008e; // hispi, adding i2c fifo fill, all met,83.73% // parameter FPGA_VERSION = 32'h0393008e; // hispi, adding i2c fifo fill, all met,83.73%
// parameter FPGA_VERSION = 32'h0393008d; // parallel, adding i2c fifo fill max err 0.128, 82.61% // parameter FPGA_VERSION = 32'h0393008d; // parallel, adding i2c fifo fill max err 0.128, 82.61%
// parameter FPGA_VERSION = 32'h0393008c; // hispi, all met, 83.55% // parameter FPGA_VERSION = 32'h0393008c; // hispi, all met, 83.55%
......
...@@ -305,6 +305,7 @@ module mcntrl393 #( ...@@ -305,6 +305,7 @@ module mcntrl393 #(
// sensor subsystem interface // sensor subsystem interface
input [3:0] sens_sof, // // single mclk pulse, start of frame (early) input [3:0] sens_sof, // // single mclk pulse, start of frame (early)
output [3:0] sens_frame_run, // output @ mclk - enable data to memory buffer
output [3:0] sens_rpage_set, // (), // input output [3:0] sens_rpage_set, // (), // input
output [3:0] sens_rpage_next, // output to control memory side of the buffer during write to memory output [3:0] sens_rpage_next, // output to control memory side of the buffer during write to memory
output [3:0] sens_buf_rd, // (), // input output [3:0] sens_buf_rd, // (), // input
...@@ -312,6 +313,11 @@ module mcntrl393 #( ...@@ -312,6 +313,11 @@ module mcntrl393 #(
input [3:0] sens_page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer input [3:0] sens_page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer
output [3:0] sens_xfer_skipped, // single mclk pulse on each bit indicating one skipped (not written) block. output [3:0] sens_xfer_skipped, // single mclk pulse on each bit indicating one skipped (not written) block.
output reg [3:0] sens_first_wr_in_frame, // single mclk pulse on first write block in each frame output reg [3:0] sens_first_wr_in_frame, // single mclk pulse on first write block in each frame
`ifdef DEBUG_SENS_MEM_PAGES
input [2 * 4 - 1 : 0] dbg_rpage,
input [2 * 4 - 1 : 0] dbg_wpage,
`endif
// compressor subsystem interface // compressor subsystem interface
// Buffer interfaces, combined for 4 channels // Buffer interfaces, combined for 4 channels
output [3:0] cmprs_xfer_reset_page_rd, // from mcntrl_tiled_rw ( output [3:0] cmprs_xfer_reset_page_rd, // from mcntrl_tiled_rw (
...@@ -1104,6 +1110,7 @@ module mcntrl393 #( ...@@ -1104,6 +1110,7 @@ module mcntrl393 #(
.status_rq (status_sens_rq[i]), // output .status_rq (status_sens_rq[i]), // output
.status_start (status_sens_start[i]), // input .status_start (status_sens_start[i]), // input
.frame_start (sens_sof[i]), // input .frame_start (sens_sof[i]), // input
.frame_run (sens_frame_run[i]), // output
.next_page (sens_page_written[i]) , // Sensor has written next buffer page (full or partial) .next_page (sens_page_written[i]) , // Sensor has written next buffer page (full or partial)
.frame_done (cmprs_frame_done_src[i]), // output .frame_done (cmprs_frame_done_src[i]), // output
.frame_finished (), // output .frame_finished (), // output
...@@ -1126,6 +1133,10 @@ module mcntrl393 #( ...@@ -1126,6 +1133,10 @@ module mcntrl393 #(
.xfer_page_rst_rd (), // output @ negedge mclk .xfer_page_rst_rd (), // output @ negedge mclk
.xfer_skipped (sens_xfer_skipped[i]), // output reg .xfer_skipped (sens_xfer_skipped[i]), // output reg
.cmd_wrmem () // output .cmd_wrmem () // output
`ifdef DEBUG_SENS_MEM_PAGES
,.dbg_rpage (dbg_rpage[2*i +:2]) // input[1:0]
,.dbg_wpage (dbg_wpage[2*i +:2]) // input[1:0]
`endif
); );
mcntrl_tiled_rw #( mcntrl_tiled_rw #(
...@@ -1244,6 +1255,7 @@ module mcntrl393 #( ...@@ -1244,6 +1255,7 @@ module mcntrl393 #(
.status_rq (status_scanline_chn1_rq), // output .status_rq (status_scanline_chn1_rq), // output
.status_start (status_scanline_chn1_start), // input .status_start (status_scanline_chn1_start), // input
.frame_start (frame_start_chn1), // input .frame_start (frame_start_chn1), // input
.frame_run (), // output
.next_page (next_page_chn1), // input .next_page (next_page_chn1), // input
.frame_done (frame_done_chn1), // output .frame_done (frame_done_chn1), // output
.frame_finished (), // output .frame_finished (), // output
...@@ -1266,6 +1278,11 @@ module mcntrl393 #( ...@@ -1266,6 +1278,11 @@ module mcntrl393 #(
.xfer_page_rst_rd (xfer_reset_page1_rd), // output .xfer_page_rst_rd (xfer_reset_page1_rd), // output
.xfer_skipped (), // output reg .xfer_skipped (), // output reg
.cmd_wrmem (cmd_wrmem_chn1) // output .cmd_wrmem (cmd_wrmem_chn1) // output
`ifdef DEBUG_SENS_MEM_PAGES
,.dbg_rpage () // input[1:0]
,.dbg_wpage () // input[1:0]
`endif
); );
mcntrl_linear_rw #( mcntrl_linear_rw #(
...@@ -1308,6 +1325,7 @@ module mcntrl393 #( ...@@ -1308,6 +1325,7 @@ module mcntrl393 #(
.status_rq (status_scanline_chn3_rq), // output .status_rq (status_scanline_chn3_rq), // output
.status_start (status_scanline_chn3_start), // input .status_start (status_scanline_chn3_start), // input
.frame_start (frame_start_chn3), // input .frame_start (frame_start_chn3), // input
.frame_run (), // output
.next_page (next_page_chn3), // input .next_page (next_page_chn3), // input
.frame_done (frame_done_chn3), // output .frame_done (frame_done_chn3), // output
.frame_finished (), // output .frame_finished (), // output
...@@ -1330,6 +1348,10 @@ module mcntrl393 #( ...@@ -1330,6 +1348,10 @@ module mcntrl393 #(
.xfer_page_rst_rd (xfer_reset_page3_rd), // output .xfer_page_rst_rd (xfer_reset_page3_rd), // output
.xfer_skipped (), // output reg .xfer_skipped (), // output reg
.cmd_wrmem () // output .cmd_wrmem () // output
`ifdef DEBUG_SENS_MEM_PAGES
,.dbg_rpage () // input[1:0]
,.dbg_wpage () // input[1:0]
`endif
); );
mcntrl_tiled_rw #( mcntrl_tiled_rw #(
......
...@@ -46,7 +46,7 @@ module mcntrl_buf_wr #( ...@@ -46,7 +46,7 @@ module mcntrl_buf_wr #(
input [1:0] rpage_in, // will register to wclk, input OK with mclk input [1:0] rpage_in, // will register to wclk, input OK with mclk
input rpage_set, // set internal read page to rpage_in input rpage_set, // set internal read page to rpage_in
input page_next, // advance to next page (and reset lower bits to 0) input page_next, // advance to next page (and reset lower bits to 0)
output [1:0] page, // current inernal page output [1:0] page, // current internal page
input rd, // read buffer to memory, increment read address (regester enable will be delayed) input rd, // read buffer to memory, increment read address (regester enable will be delayed)
output [63:0] data_out // data out output [63:0] data_out // data out
......
...@@ -84,6 +84,7 @@ module mcntrl_linear_rw #( ...@@ -84,6 +84,7 @@ module mcntrl_linear_rw #(
input status_start, // acknowledge of address (first byte) from downsteram input status_start, // acknowledge of address (first byte) from downsteram
input frame_start, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page) input frame_start, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
output frame_run, // @mclk - enable pixels from sesnor to memory buffer
input next_page, // page was read/written from/to 4*1kB on-chip buffer input next_page, // page was read/written from/to 4*1kB on-chip buffer
// output page_ready, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory // output page_ready, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
...@@ -109,6 +110,13 @@ module mcntrl_linear_rw #( ...@@ -109,6 +110,13 @@ module mcntrl_linear_rw #(
output xfer_page_rst_rd, // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge output xfer_page_rst_rd, // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge
output reg xfer_skipped, output reg xfer_skipped,
output cmd_wrmem output cmd_wrmem
`ifdef DEBUG_SENS_MEM_PAGES
,input [1 : 0] dbg_rpage
,input [1 : 0] dbg_wpage
`endif
); );
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22 localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22 localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22
...@@ -250,6 +258,8 @@ module mcntrl_linear_rw #( ...@@ -250,6 +258,8 @@ module mcntrl_linear_rw #(
assign single_frame_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_SINGLE]; assign single_frame_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME]; assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
assign frame_run = busy_r;
// Set parameter registers // Set parameter registers
always @(posedge mclk) begin always @(posedge mclk) begin
if (mrst) mode_reg <= 0; if (mrst) mode_reg <= 0;
...@@ -597,17 +607,60 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -597,17 +607,60 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
.data (cmd_data), // output[31:0] .data (cmd_data), // output[31:0]
.we (cmd_we) // output .we (cmd_we) // output
); );
`ifdef DEBUG_SENS_MEM_PAGES
reg [1:0] dbg_cnt_snp;
reg [1:0] dbg_nxt_page;
reg dbg_busy_r2;
reg dbg_pre_want_r1;
reg [1:0] dbg_busy; // busy is toggling
reg [1:0] dbg_prewant; // pre_want_r1 is toggling
// else if (!start_not_partial && next_page) page_cntr <= page_cntr + 1;
always @ (posedge mclk) begin
if (mrst) dbg_cnt_snp <= 0;
else if (start_not_partial) dbg_cnt_snp <= dbg_cnt_snp + 1;
if (mrst) dbg_nxt_page <= 0;
else if (next_page) dbg_nxt_page <= dbg_nxt_page + 1;
if (mrst) dbg_nxt_page <= 0;
else if (next_page) dbg_nxt_page <= dbg_nxt_page + 1;
dbg_busy_r2 <= busy_r;
dbg_pre_want_r1 <=pre_want_r1;
if (mrst) dbg_busy <= 0;
else if (busy_r && !dbg_busy_r2) dbg_busy <= dbg_busy + 1;
if (mrst) dbg_prewant <= 0;
else if (pre_want_r1 && !dbg_pre_want_r1) dbg_prewant <= dbg_prewant + 1;
end
`endif
status_generate #( status_generate #(
.STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_ADDR), .STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_ADDR),
`ifdef DEBUG_SENS_MEM_PAGES
.PAYLOAD_BITS (2 + 2 +2 + 2 + 2 + 2 +2 + 3 + 3 + MCNTRL_SCANLINE_PENDING_CNTR_BITS)
`else
.PAYLOAD_BITS (2) .PAYLOAD_BITS (2)
`endif
) status_generate_i ( ) status_generate_i (
.rst (1'b0), //rst), // input .rst (1'b0), //rst), // input
.clk (mclk), // input .clk (mclk), // input
.srst (mrst), // input .srst (mrst), // input
.we (set_status_w), // input .we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0] .wd (cmd_data[7:0]), // input[7:0]
`ifdef DEBUG_SENS_MEM_PAGES
.status ({frame_en, page_cntr[2:0],
dbg_prewant[1:0], dbg_busy[1:0],
single_frame_r, repeat_frames, dbg_cnt_snp[1:0],
dbg_nxt_page[1:0], pending_xfers[1:0],
dbg_wpage[1:0], dbg_rpage[1:0],
status_data}), // input[25:0]
`else
.status (status_data), // input[25:0] .status (status_data), // input[25:0]
`endif
.ad (status_ad), // output[7:0] .ad (status_ad), // output[7:0]
.rq (status_rq), // output .rq (status_rq), // output
.start (status_start) // input .start (status_start) // input
......
...@@ -257,6 +257,38 @@ class X393AxiControlStatus(object): ...@@ -257,6 +257,38 @@ class X393AxiControlStatus(object):
<addr> - status register address (currently 0..255) <addr> - status register address (currently 0..255)
""" """
return self.x393_mem.axi_read_addr_w(vrlg.STATUS_ADDR + address ) return self.x393_mem.axi_read_addr_w(vrlg.STATUS_ADDR + address )
def rpt_read_status(self, address, num_rep = 10, verbose = 1): # was read_and_wait_status
"""
Read word from the status register multiple times (up to 26 bits payload and 6-bit sequence number)
@param addr - status register address (currently 0..255)
@param num_rep - number of times to read register
@param verbose - verbose level (0 - silent, >0 - print hex results)
"""
rslt = []
for _ in range(num_rep):
rslt.append(self.read_status(address = address))
if (verbose > 0):
for i, v in enumerate(rslt):
# print("%3d: %08x (0x%06x %x 0x%02x"%(i, v, v & 0xffffff, (v >> 24) & 3, (v >> 26) & 0x3f))
print("%3d: %08x (0x%06x) rpage=%x wpage=%x p_xfs=%x npg=%x snp=%x rpt=%x sngl=%x bsy=%x prewant=%x pgcnt=%x fren=%x bsy=%x done=%x"%(
i, v, v & 0xffffff,
(v >> 0) & 3, # rpage
(v >> 2) & 3, # wpage
(v >> 4) & 3, # pening_xfers
(v >> 6) & 3, # dbg_nxt_page (counting next_page signals)
(v >> 8) & 3, # dbg_cnt_snp - count start_not_partial
(v >>10) & 1, # repeat frames
(v >>11) & 1, # single frames
(v >>12) & 3, # dbg_busy - count busy _/~
(v >>14) & 3, # dbg_prewant - count pre_want_r1 _/~
(v >>16) & 7, # page_cntr - up/down counter
(v >>19) & 1, # frame_en
(v >>24) & 1, # bsy
(v >>25) & 1 ))#done
return rslt
# assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
def wait_status_condition(self, def wait_status_condition(self,
status_address, # input [STATUS_DEPTH-1:0] status_address; status_address, # input [STATUS_DEPTH-1:0] status_address;
status_control_address, # input [29:0] status_control_address; status_control_address, # input [29:0] status_control_address;
......
...@@ -1104,12 +1104,66 @@ write_sensor_i2c 0 1 0 0x302e0010 ...@@ -1104,12 +1104,66 @@ write_sensor_i2c 0 1 0 0x302e0010
#Exposure 0x800 lines #Exposure 0x800 lines
write_sensor_i2c 0 1 0 0x30120800 write_sensor_i2c 0 1 0 0x30120800
################## Serial - chn3 ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs
bitstream_set_path /usr/local/verilog/x393_hispi.bit
setupSensorsPower "HISPI"
measure_all "*DI"
setup_all_sensors True None 0xf
#write_sensor_i2c 3 1 0 0x30700101
compressor_control all None None None None None 2
program_gamma all 0 0.57 0.04
write_sensor_i2c 3 1 0 0x030600b4
write_sensor_i2c 3 1 0 0x31c68400
write_sensor_i2c 3 1 0 0x306e9280
#write_sensor_i2c 3 1 0 0x30700002
write_sensor_i2c 3 1 0 0x301a001c
print_sensor_i2c 3 0x31c6 0xff 0x10 0
write_sensor_i2c 3 1 0 0x3028000a
write_sensor_i2c 3 1 0 0x302c000d
write_sensor_i2c 3 1 0 0x302e0010
#exposure
write_sensor_i2c 3 1 0 0x30120200
compressor_control 3 2
jpeg_write "img.jpeg" 3
------- -------
################## Serial - chn2 ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs
bitstream_set_path /usr/local/verilog/x393_hispi.bit
setupSensorsPower "HISPI"
measure_all "*DI"
setup_all_sensors True None 0xf
#write_sensor_i2c 2 1 0 0x30700101
compressor_control all None None None None None 2
program_gamma all 0 0.57 0.04
write_sensor_i2c 2 1 0 0x030600b4
write_sensor_i2c 2 1 0 0x31c68400
write_sensor_i2c 2 1 0 0x306e9280
#write_sensor_i2c 2 1 0 0x30700002
write_sensor_i2c 2 1 0 0x301a001c
print_sensor_i2c 2 0x31c6 0xff 0x10 0
write_sensor_i2c 2 1 0 0x3028000a
write_sensor_i2c 2 1 0 0x302c000d
write_sensor_i2c 2 1 0 0x302e0010
#exposure
write_sensor_i2c 2 1 0 0x30120200
write_sensor_i2c 2 1 0 0x30700101
compressor_control 2 2
jpeg_write "img.jpeg" 2
-------
control_sensor_memory 2 reset
print_sensor_i2c 2 0x31c0 0xff 0x10 0
......
...@@ -1512,7 +1512,7 @@ class X393McntrlAdjust(object): ...@@ -1512,7 +1512,7 @@ class X393McntrlAdjust(object):
try: try:
dqs_patt=self.adjustment_state["dqs_pattern"] dqs_patt=self.adjustment_state["dqs_pattern"]
except: except:
print("Skipping DQS pattern (0x55/0xaa) control as it is not provided and not in gloabal data (dqs_patt=self.adjustment_state['dqs_pattern'])") print("Skipping DQS pattern (0x55/0xaa) control as it is not provided and not in global data (dqs_patt=self.adjustment_state['dqs_pattern'])")
if not dqs_patt is None: # may be just set if not dqs_patt is None: # may be just set
self.x393_mcntrl_timing.axi_set_dqs_dqm_patterns(dqs_patt=dqs_patt, self.x393_mcntrl_timing.axi_set_dqs_dqm_patterns(dqs_patt=dqs_patt,
...@@ -1533,6 +1533,12 @@ class X393McntrlAdjust(object): ...@@ -1533,6 +1533,12 @@ class X393McntrlAdjust(object):
# raise Exception("Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized") # raise Exception("Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized")
#disabling check 04.09.2016 #disabling check 04.09.2016
print ("raise Exception Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized. Phase: %d, cmda_odly_lin=%d"%(phase,cmda_odly_lin)) print ("raise Exception Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized. Phase: %d, cmda_odly_lin=%d"%(phase,cmda_odly_lin))
print ("=== resetting ===")
self.x393_pio_sequences.restart_ddr3()
wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, nbursts, quiet - 1))
if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?)
print ("Second try: raise Exception Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized. Phase: %d, cmda_odly_lin=%d"%(phase,cmda_odly_lin))
self.x393_pio_sequences.restart_ddr3()
dqso_cache[dly] = wlev_rslt dqso_cache[dly] = wlev_rslt
if quiet < 1: if quiet < 1:
print ('measure_dqso(%d) - new measurement'%(dly)) print ('measure_dqso(%d) - new measurement'%(dly))
......
...@@ -949,7 +949,7 @@ class X393Sensor(object): ...@@ -949,7 +949,7 @@ class X393Sensor(object):
def set_sensor_io_dly_hispi (self, def set_sensor_io_dly_hispi (self,
num_sensor, num_sensor,
mmcm_phase = None, mmcm_phase = None, #24 steps in 3ns period
lane0_dly = None, lane0_dly = None,
lane1_dly = None, lane1_dly = None,
lane2_dly = None, lane2_dly = None,
...@@ -1893,6 +1893,68 @@ input mem mtd4 ram1 ...@@ -1893,6 +1893,68 @@ input mem mtd4 ram1
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + vrlg.HIST_SAXI_ADDR_REL + channel, self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + vrlg.HIST_SAXI_ADDR_REL + channel,
channel_page) channel_page)
def control_sensor_memory(self,
num_sensor,
command,
reset_frame = False,
verbose = 1):
"""
Control memory access (write) of a sensor channel
@param num_sensor - memory sensor channel (or all)
@param command - one of (case insensitive):
reset - reset channel, channel pointers immediately,
stop - stop at the end of the frame (if repetitive),
single - acquire single frame ,
repetitive - repetitive mode
@param reset_frame - reset frame number
@param vebose - verbose level
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
print ('num_sensor = ',num_sensor)
self.control_sensor_memory(num_sensor = num_sensor,
command = command,
reset_frame = reset_frame,
verbose = verbose)
return
except:
pass
rpt = False
sngl = False
en = False
rst = False
if command[:3].upper() == 'RES':
rst = True
elif command[:2].upper() == 'ST':
pass
elif command[:2].upper() == 'SI':
sngl = True
en = True
elif command[:3].upper() == 'REP':
rpt = True
en = True
else:
print ("Unrecognized command %s. Valid commands are RESET, STOP, SINGLE, REPETITIVE"%(command))
return
base_addr = vrlg.MCONTR_SENS_BASE + vrlg.MCONTR_SENS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = True,
disable_need = False,
repetitive= rpt,
single = sngl,
reset_frame = reset_frame,
extra_pages = 0,
write_mem = True,
enable = en,
chn_reset = rst)
self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_SCANLINE_MODE, mode)
if verbose > 0 :
print ("write_control_register(0x%08x, 0x%08x)"%(base_addr + vrlg.MCNTRL_SCANLINE_MODE, mode))
def setup_sensor_memory (self, def setup_sensor_memory (self,
num_sensor, num_sensor,
frame_sa, frame_sa,
......
...@@ -39,6 +39,7 @@ module sensor_membuf #( ...@@ -39,6 +39,7 @@ module sensor_membuf #(
input pclk, input pclk,
input prst, // reset @ posedge pclk input prst, // reset @ posedge pclk
input mrst, // reset @ posedge mclk input mrst, // reset @ posedge mclk
input frame_run_mclk, // @mclk - memory channel is ready to accept data from the sensor
input [15:0] px_data, // @posedge pclk pixel (pixel pair) data from the sensor channel input [15:0] px_data, // @posedge pclk pixel (pixel pair) data from the sensor channel
input px_valid, // px_data valid input px_valid, // px_data valid
input last_in_line, // valid with px_valid - last px_data in line input last_in_line, // valid with px_valid - last px_data in line
...@@ -49,30 +50,42 @@ module sensor_membuf #( ...@@ -49,30 +50,42 @@ module sensor_membuf #(
input buf_rd, // read buffer to memory, increment read address (register enable will be delayed) input buf_rd, // read buffer to memory, increment read address (register enable will be delayed)
output [63:0] buf_dout, // data out output [63:0] buf_dout, // data out
output page_written // buffer page (full or partial) is written to the memory buffer output page_written // buffer page (full or partial) is written to the memory buffer
`ifdef DEBUG_SENS_MEM_PAGES
,output [1:0] dbg_rpage
,output [1:0] dbg_wpage
`endif
); );
reg [1:0] wpage; reg [1:0] wpage;
reg [WADDR_WIDTH-1:0] waddr; reg [WADDR_WIDTH-1:0] waddr;
// reg sim_rst = 1; // jsut for simulation - reset from system reset to the first rpage_set // reg sim_rst = 1; // just for simulation - reset from system reset to the first rpage_set
reg [2:0] rst_pntr; reg [2:0] rst_pntr;
reg frame_run_pclk;
wire rst_wpntr; wire rst_wpntr;
wire inc_wpage_w; wire inc_wpage_w;
wire px_use = frame_run_pclk && px_valid; // px valid and enabled by memory controller
assign inc_wpage_w = px_valid && (last_in_line || (&waddr)); `ifdef DEBUG_SENS_MEM_PAGES
assign dbg_wpage = dbg_wpage;
`endif
assign inc_wpage_w = px_use && (last_in_line || (&waddr));
always @ (posedge mclk) begin always @ (posedge mclk) begin
rst_pntr <= {rst_pntr[1] &~rst_pntr[0], rst_pntr[0], rpage_set}; rst_pntr <= {rst_pntr[1] &~rst_pntr[0], rst_pntr[0], rpage_set};
// if (rpage_set) sim_rst <= 0; // if (rpage_set) sim_rst <= 0;
end end
always @ (posedge pclk) begin always @ (posedge pclk) begin
if (prst || rst_wpntr || (px_valid && last_in_line)) waddr <= 0; if (prst || rst_wpntr || (px_use && last_in_line)) waddr <= 0;
else if (px_valid) waddr <= waddr + 1; else if (px_use) waddr <= waddr + 1;
if (prst || rst_wpntr) wpage <= 0; if (prst || rst_wpntr) wpage <= 0;
else if (inc_wpage_w) wpage <= wpage + 1; else if (inc_wpage_w) wpage <= wpage + 1;
frame_run_pclk <= frame_run_mclk;
end end
pulse_cross_clock rst_wpntr_i ( pulse_cross_clock rst_wpntr_i (
...@@ -99,13 +112,17 @@ module sensor_membuf #( ...@@ -99,13 +112,17 @@ module sensor_membuf #(
) chn1wr_buf_i ( ) chn1wr_buf_i (
.ext_clk (pclk), // input .ext_clk (pclk), // input
.ext_waddr ({wpage, waddr}), // input[9:0] .ext_waddr ({wpage, waddr}), // input[9:0]
.ext_we (px_valid), // input .ext_we (px_use), // input
.ext_data_in (px_data), // input[15:0] buf_wdata - from AXI .ext_data_in (px_data), // input[15:0] buf_wdata - from AXI
.rclk (mclk), // input .rclk (mclk), // input
.rpage_in (2'b0), // input[1:0] .rpage_in (2'b0), // input[1:0]
.rpage_set (rpage_set), // input @ posedge mclk .rpage_set (rpage_set), // input @ posedge mclk
.page_next (rpage_next), // input .page_next (rpage_next), // input
`ifdef DEBUG_SENS_MEM_PAGES
.page (dbg_rpage), // output[1:0]
`else
.page (), // output[1:0] .page (), // output[1:0]
`endif
.rd (buf_rd), // input .rd (buf_rd), // input
.data_out (buf_dout) // output[63:0] .data_out (buf_dout) // output[63:0]
); );
......
...@@ -334,8 +334,8 @@ module sensors393 #( ...@@ -334,8 +334,8 @@ module sensors393 #(
`ifdef HISPI `ifdef HISPI
input [15:0] sns_dp, input [15:0] sns_dp,
input [15:0] sns_dn, input [15:0] sns_dn,
inout [15:0] sns_dp74, inout [15:0] sns_dp74, // SuppressThisWarning all - unused yet
inout [15:0] sns_dn74, inout [15:0] sns_dn74, // SuppressThisWarning all - unused yet
input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`else `else
...@@ -355,9 +355,10 @@ module sensors393 #( ...@@ -355,9 +355,10 @@ module sensors393 #(
inout [3:0] sns_pg, inout [3:0] sns_pg,
// Memory interface (4 channels) // Memory interface (4 channels)
input [3:0] frame_run_mclk, // input [3:0] - enable sensor data to memory buffer
input [3:0] rpage_set, // set internal read page to rpage_in (reset pointers) input [3:0] rpage_set, // set internal read page to rpage_in (reset pointers)
input [3:0] rpage_next, // advance to next page (and reset lower bits to 0) input [3:0] rpage_next, // advance to next page (and reset lower bits to 0)
input [3:0] buf_rd, // read buffer to memory, increment read address (regester enable will be delayed) input [3:0] buf_rd, // read buffer to memory, increment read address (register enable will be delayed)
output [255:0] buf_dout, // data out output [255:0] buf_dout, // data out
output [3:0] page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer output [3:0] page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer
...@@ -404,6 +405,11 @@ module sensors393 #( ...@@ -404,6 +405,11 @@ module sensors393 #(
output saxi_bready, // AXI PS Slave GP0 BREADY, input output saxi_bready, // AXI PS Slave GP0 BREADY, input
input [ 5:0] saxi_bid, // AXI PS Slave GP0 BID[5:0], output input [ 5:0] saxi_bid, // AXI PS Slave GP0 BID[5:0], output
input [ 1:0] saxi_bresp // AXI PS Slave GP0 BRESP[1:0], output input [ 1:0] saxi_bresp // AXI PS Slave GP0 BRESP[1:0], output
`ifdef DEBUG_SENS_MEM_PAGES
,output [2 * 4 - 1 : 0] dbg_rpage
,output [2 * 4 - 1 : 0] dbg_wpage
`endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
,output debug_do, // output to the debug ring ,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load
...@@ -437,10 +443,11 @@ module sensors393 #( ...@@ -437,10 +443,11 @@ module sensors393 #(
wire [3:0] hist_dvalid; wire [3:0] hist_dvalid;
wire [127:0] hist_data; wire [127:0] hist_data;
wire [4*NUM_FRAME_BITS-1:0] frame_num = {frame_num3, frame_num2, frame_num1, frame_num0}; wire [4*NUM_FRAME_BITS-1:0] frame_num = {frame_num3, frame_num2, frame_num1, frame_num0};
always @ (posedge mclk) begin always @ (posedge mclk) begin
cmd_ad <= cmd_ad_in; cmd_ad <= cmd_ad_in;
cmd_stb <= cmd_stb_in; cmd_stb <= cmd_stb_in;
...@@ -700,6 +707,7 @@ module sensors393 #( ...@@ -700,6 +707,7 @@ module sensors393 #(
.pclk (pclk), // input .pclk (pclk), // input
.prst (prst), // input .prst (prst), // input
.mrst (mrst), // input .mrst (mrst), // input
.frame_run_mclk(frame_run_mclk[i]), // input @mclk - memory channel is ready to accept data from the sensor
.px_data (px_data[16 * i +: 16]), // input[15:0] .px_data (px_data[16 * i +: 16]), // input[15:0]
.px_valid (px_valid[i]), // input .px_valid (px_valid[i]), // input
.last_in_line (last_in_line[i]), // input .last_in_line (last_in_line[i]), // input
...@@ -708,7 +716,11 @@ module sensors393 #( ...@@ -708,7 +716,11 @@ module sensors393 #(
.rpage_next (rpage_next[i]), // input .rpage_next (rpage_next[i]), // input
.buf_rd (buf_rd[i]), // input .buf_rd (buf_rd[i]), // input
.buf_dout (buf_dout[64*i +: 64]), // output[63:0] .buf_dout (buf_dout[64*i +: 64]), // output[63:0]
.page_written(page_written[i]) // output reg single mclk pulse: buffer page (full or partial) is written to the memory buffer .page_written (page_written[i]) // output reg single mclk pulse: buffer page (full or partial) is written to the memory buffer
`ifdef DEBUG_SENS_MEM_PAGES
,.dbg_rpage (dbg_rpage[2 * i +: 2])
,.dbg_wpage (dbg_wpage[2 * i +: 2])
`endif
); );
end end
endgenerate endgenerate
......
...@@ -48,12 +48,14 @@ ...@@ -48,12 +48,14 @@
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels // if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/ `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define USE_OLD_XDCT393 // `define USE_OLD_XDCT393
// `define USE_PCLK2X // `define USE_PCLK2X
// `define USE_XCLK2X // `define USE_XCLK2X
`define REVERSE_LANES 1 `define REVERSE_LANES 1
`define DEBUG_RING 1 `define DEBUG_RING 1
`define DEBUG_SENS_MEM_PAGES 1
// `define MCLK_VCO_MULT 16 // `define MCLK_VCO_MULT 16
// DDR3 memory speed grade and density // DDR3 memory speed grade and density
`define sg25 1 `define sg25 1
......
...@@ -378,6 +378,12 @@ module x393 #( ...@@ -378,6 +378,12 @@ module x393 #(
wire status_clocks_rq; // Other status request wire status_clocks_rq; // Other status request
wire status_clocks_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq) wire status_clocks_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
`ifdef DEBUG_SENS_MEM_PAGES
wire [7:0] dbg_rpage;
wire [7:0] dbg_wpage;
`endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
wire [7:0] status_debug_ad; // saxi1 - logger data Other status byte-wide address/data wire [7:0] status_debug_ad; // saxi1 - logger data Other status byte-wide address/data
wire status_debug_rq; // Other status request wire status_debug_rq; // Other status request
...@@ -474,8 +480,9 @@ module x393 #( ...@@ -474,8 +480,9 @@ module x393 #(
wire [63:0] gpio_in; wire [63:0] gpio_in;
// signals for sensor393 (in/outs as sseen for the sensor393) // signals for sensor393 (in/outs as seen for the sensor393)
wire [3:0] sens_rpage_set; // (), // input wire [3:0] sens_rpage_set; // (), // input
wire [3:0] sens_frame_run; // @mclk from mcntrl393 - enable data to memory buffer
wire [3:0] sens_rpage_next; // (), // input wire [3:0] sens_rpage_next; // (), // input
wire [3:0] sens_buf_rd; // (), // input wire [3:0] sens_buf_rd; // (), // input
wire [255:0] sens_buf_dout; // (), // output[63:0] wire [255:0] sens_buf_dout; // (), // output[63:0]
...@@ -1312,6 +1319,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1312,6 +1319,7 @@ assign axi_grst = axi_rst_pre;
// sensors interface // sensors interface
.sens_sof (sof_out_mclk), // input[3:0] // Early start of frame pulses (@mclk) .sens_sof (sof_out_mclk), // input[3:0] // Early start of frame pulses (@mclk)
.sens_frame_run (sens_frame_run), // output[3:0] @mclk - enable data to memory buffer
.sens_rpage_set (sens_rpage_set), // output[3:0] .sens_rpage_set (sens_rpage_set), // output[3:0]
.sens_rpage_next (sens_rpage_next), // output[3:0] .sens_rpage_next (sens_rpage_next), // output[3:0]
.sens_buf_rd (sens_buf_rd), // output[3:0] .sens_buf_rd (sens_buf_rd), // output[3:0]
...@@ -1319,6 +1327,10 @@ assign axi_grst = axi_rst_pre; ...@@ -1319,6 +1327,10 @@ assign axi_grst = axi_rst_pre;
.sens_page_written (sens_page_written), // input [3:0] single mclk pulse: buffer page (full or partial) is written to the memory buffer .sens_page_written (sens_page_written), // input [3:0] single mclk pulse: buffer page (full or partial) is written to the memory buffer
.sens_xfer_skipped (sens_xfer_skipped), // output reg .sens_xfer_skipped (sens_xfer_skipped), // output reg
.sens_first_wr_in_frame (sens_first_wr_in_frame), // single mclk pulse on first write block in each frame .sens_first_wr_in_frame (sens_first_wr_in_frame), // single mclk pulse on first write block in each frame
`ifdef DEBUG_SENS_MEM_PAGES
.dbg_rpage (dbg_rpage[7:0]), // input[7:0]
.dbg_wpage (dbg_wpage[7:0]), // input[7:0]
`endif
// compressor interface // compressor interface
.cmprs_xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // output[3:0] .cmprs_xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // output[3:0]
...@@ -1353,7 +1365,6 @@ assign axi_grst = axi_rst_pre; ...@@ -1353,7 +1365,6 @@ assign axi_grst = axi_rst_pre;
.rpage_nxt_chn1 (rpage_nxt_chn1), // output .rpage_nxt_chn1 (rpage_nxt_chn1), // output
.buf_rd_chn1 (buf_rd_chn1), // output .buf_rd_chn1 (buf_rd_chn1), // output
.buf_rdata_chn1 (buf_rdata_chn1[63:0]), // input[63:0] .buf_rdata_chn1 (buf_rdata_chn1[63:0]), // input[63:0]
.frame_start_chn2 (frame_start_chn2), // input .frame_start_chn2 (frame_start_chn2), // input
.next_page_chn2 (next_page_chn2), // input .next_page_chn2 (next_page_chn2), // input
.page_ready_chn2 (page_ready_chn2), // output .page_ready_chn2 (page_ready_chn2), // output
...@@ -1834,6 +1845,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1834,6 +1845,7 @@ assign axi_grst = axi_rst_pre;
.sns_ctl ({sns4_ctl, sns3_ctl, sns2_ctl, sns1_ctl}), // inout .sns_ctl ({sns4_ctl, sns3_ctl, sns2_ctl, sns1_ctl}), // inout
.sns_pg ({sns4_pg, sns3_pg, sns2_pg, sns1_pg}), // inout .sns_pg ({sns4_pg, sns3_pg, sns2_pg, sns1_pg}), // inout
`endif `endif
.frame_run_mclk (sens_frame_run), // input [3:0] - enable sensor data to memory buffer
.rpage_set (sens_rpage_set), // input .rpage_set (sens_rpage_set), // input
.rpage_next (sens_rpage_next), // input .rpage_next (sens_rpage_next), // input
.buf_rd (sens_buf_rd), // input .buf_rd (sens_buf_rd), // input
...@@ -1876,6 +1888,11 @@ assign axi_grst = axi_rst_pre; ...@@ -1876,6 +1888,11 @@ assign axi_grst = axi_rst_pre;
.saxi_bready (saxi0_bready), // output .saxi_bready (saxi0_bready), // output
.saxi_bid (saxi0_bid), // input[5:0] .saxi_bid (saxi0_bid), // input[5:0]
.saxi_bresp (saxi0_bresp) // input[1:0] .saxi_bresp (saxi0_bresp) // input[1:0]
`ifdef DEBUG_SENS_MEM_PAGES
,.dbg_rpage (dbg_rpage[7:0]) // output[7:0]
,.dbg_wpage (dbg_wpage[7:0]) // output[7:0]
`endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output ,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input .debug_sl (debug_sl), // input
......
...@@ -182,8 +182,6 @@ parameter NUM_INTERRUPTS = 9; ...@@ -182,8 +182,6 @@ parameter NUM_INTERRUPTS = 9;
// ========================== end of parameters from x353 =================================== // ========================== end of parameters from x353 ===================================
// Sensor signals - as on sensor pads // Sensor signals - as on sensor pads
wire PX1_MCLK; // input sensor input clock wire PX1_MCLK; // input sensor input clock
wire PX1_MRST; // input wire PX1_MRST; // input
...@@ -191,6 +189,7 @@ parameter NUM_INTERRUPTS = 9; ...@@ -191,6 +189,7 @@ parameter NUM_INTERRUPTS = 9;
wire PX1_ARST; // input wire PX1_ARST; // input
wire PX1_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode. wire PX1_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
wire [11:0] PX1_D; // output[11:0] wire [11:0] PX1_D; // output[11:0]
// SuppressWarnings VEditor : not used in HISPI mode
wire PX1_DCLK; // output sensor output clock (connect to sensor BPF output ) wire PX1_DCLK; // output sensor output clock (connect to sensor BPF output )
wire PX1_HACT; // output wire PX1_HACT; // output
wire PX1_VACT; // output wire PX1_VACT; // output
...@@ -201,6 +200,7 @@ parameter NUM_INTERRUPTS = 9; ...@@ -201,6 +200,7 @@ parameter NUM_INTERRUPTS = 9;
wire PX2_ARST; // input wire PX2_ARST; // input
wire PX2_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode. wire PX2_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
wire [11:0] PX2_D; // output[11:0] wire [11:0] PX2_D; // output[11:0]
// SuppressWarnings VEditor : not used in HISPI mode
wire PX2_DCLK; // output sensor output clock (connect to sensor BPF output ) wire PX2_DCLK; // output sensor output clock (connect to sensor BPF output )
wire PX2_HACT; // output wire PX2_HACT; // output
wire PX2_VACT; // output wire PX2_VACT; // output
...@@ -211,6 +211,7 @@ parameter NUM_INTERRUPTS = 9; ...@@ -211,6 +211,7 @@ parameter NUM_INTERRUPTS = 9;
wire PX3_ARST; // input wire PX3_ARST; // input
wire PX3_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode. wire PX3_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
wire [11:0] PX3_D; // output[11:0] wire [11:0] PX3_D; // output[11:0]
// SuppressWarnings VEditor : not used in HISPI mode
wire PX3_DCLK; // output sensor output clock (connect to sensor BPF output ) wire PX3_DCLK; // output sensor output clock (connect to sensor BPF output )
wire PX3_HACT; // output wire PX3_HACT; // output
wire PX3_VACT; // output wire PX3_VACT; // output
...@@ -221,6 +222,7 @@ parameter NUM_INTERRUPTS = 9; ...@@ -221,6 +222,7 @@ parameter NUM_INTERRUPTS = 9;
wire PX4_ARST; // input wire PX4_ARST; // input
wire PX4_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode. wire PX4_OFST = 1'b1; // input // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
wire [11:0] PX4_D; // output[11:0] wire [11:0] PX4_D; // output[11:0]
// SuppressWarnings VEditor : not used in HISPI mode
wire PX4_DCLK; // output sensor output clock (connect to sensor BPF output ) wire PX4_DCLK; // output sensor output clock (connect to sensor BPF output )
wire PX4_HACT; // output wire PX4_HACT; // output
wire PX4_VACT; // output wire PX4_VACT; // output
......
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sat May 14 06:38:56 2016 [*] Sat May 21 05:03:06 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160513194544675.fst" [dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160513194544675.fst"
[dumpfile_mtime] "Sat May 14 02:32:17 2016" [dumpfile_mtime] "Sat May 14 02:32:17 2016"
[dumpfile_size] 169964391 [dumpfile_size] 169964391
[savefile] "/home/andrey/git/x393/x393_testbench04.sav" [savefile] "/home/andrey/git/x393/x393_testbench04.sav"
[timestart] 42957700 [timestart] 0
[size] 1823 1180 [size] 1823 1180
[pos] 0 0 [pos] 0 0
*-15.461116 43097388 209370000 209396667 209423333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-25.461117 43097388 209370000 209396667 209423333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03. [treeopen] x393_testbench03.
[treeopen] x393_testbench03.read_compressor_frame_irq. [treeopen] x393_testbench03.read_compressor_frame_irq.
[treeopen] x393_testbench03.read_contol_register_irq. [treeopen] x393_testbench03.read_contol_register_irq.
...@@ -33,9 +33,10 @@ ...@@ -33,9 +33,10 @@
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_generate1_i.genblk2.status_generate_only_i. [treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_generate1_i.genblk2.status_generate_only_i.
[treeopen] x393_testbench03.x393_i.frame_sequencer_block[0]. [treeopen] x393_testbench03.x393_i.frame_sequencer_block[0].
[treeopen] x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i. [treeopen] x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i. [treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0]. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1]. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].
...@@ -255,7 +256,7 @@ x393_testbench03.sim_cmprs3_addr[31:0] ...@@ -255,7 +256,7 @@ x393_testbench03.sim_cmprs3_addr[31:0]
x393_testbench03.sim_cmprs3_data[63:0] x393_testbench03.sim_cmprs3_data[63:0]
@1000200 @1000200
-sim_afi1 -sim_afi1
@800200 @c00200
-sim_soc_interrupts -sim_soc_interrupts
@28 @28
x393_testbench03.sim_soc_interrupts_i.rst x393_testbench03.sim_soc_interrupts_i.rst
...@@ -318,7 +319,7 @@ x393_testbench03.sim_soc_interrupts_i.inta[8:0] ...@@ -318,7 +319,7 @@ x393_testbench03.sim_soc_interrupts_i.inta[8:0]
-group_end -group_end
@200 @200
- -
@1000200 @1401200
-sim_soc_interrupts -sim_soc_interrupts
@c00200 @c00200
-interrupts -interrupts
...@@ -909,6 +910,8 @@ x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.wpage_asa ...@@ -909,6 +910,8 @@ x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.wpage_asa
x393_testbench03.x393_i.frame_num[15:0] x393_testbench03.x393_i.frame_num[15:0]
@1401200 @1401200
-interrupts -interrupts
@c00200
-other_dbg
@c00022 @c00022
x393_testbench03.x393_i.cmd_seq_mux_i.status_generate_cmd_seq_mux_i.status[25:0] x393_testbench03.x393_i.cmd_seq_mux_i.status_generate_cmd_seq_mux_i.status[25:0]
@28 @28
...@@ -1014,6 +1017,7 @@ x393_testbench03.read_status_irq.rslt[31:0] ...@@ -1014,6 +1017,7 @@ x393_testbench03.read_status_irq.rslt[31:0]
(31)x393_testbench03.read_status_irq.rslt[31:0] (31)x393_testbench03.read_status_irq.rslt[31:0]
@1401200 @1401200
-group_end -group_end
-other_dbg
@c00200 @c00200
-all_sensor_data -all_sensor_data
@22 @22
...@@ -1388,7 +1392,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se ...@@ -1388,7 +1392,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-i2c -i2c
@1401200 @1401200
-frame_numbers -frame_numbers
@800200 @c00200
-sensor_i2c-0 -sensor_i2c-0
@28 @28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.mclk x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.mclk
...@@ -1429,15 +1433,128 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se ...@@ -1429,15 +1433,128 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
@22 @22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage_wr[3:0] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage_wr[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outw[5:0] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outw[5:0]
@23
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outw_r[5:0] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outw_r[5:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_next[5:0] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_next[5:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.page_r[3:0] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.page_r[3:0]
@28 @28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sync_to_seq x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sync_to_seq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.reset_on x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.reset_on
@1000200 @1401200
-sensor_i2c-0 -sensor_i2c-0
@800200
-sensor_memory
-top
@800022
x393_testbench03.x393_i.sens_rpage_set[3:0]
@28
(0)x393_testbench03.x393_i.sens_rpage_set[3:0]
(1)x393_testbench03.x393_i.sens_rpage_set[3:0]
(2)x393_testbench03.x393_i.sens_rpage_set[3:0]
(3)x393_testbench03.x393_i.sens_rpage_set[3:0]
@1001200
-group_end
@1000200
-top
@800200
-mcntrl393
@22
x393_testbench03.x393_i.mcntrl393_i.sens_rpage_set[3:0]
@800200
-mcntrl_linear_wr_sensor
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_page_rst_wr
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_page_rst_r
@c00028
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.busy_r
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_page_rst_neg
@29
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_page_rst_pos
@200
-
@1000200
-mcntrl_linear_wr_sensor
-mcntrl393
@c00200
-all_channels
@c00022
x393_testbench03.x393_i.sensors393_i.rpage_set[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.rpage_set[3:0]
(1)x393_testbench03.x393_i.sensors393_i.rpage_set[3:0]
(2)x393_testbench03.x393_i.sensors393_i.rpage_set[3:0]
(3)x393_testbench03.x393_i.sensors393_i.rpage_set[3:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.sensors393_i.rpage_next[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.rpage_next[3:0]
(1)x393_testbench03.x393_i.sensors393_i.rpage_next[3:0]
(2)x393_testbench03.x393_i.sensors393_i.rpage_next[3:0]
(3)x393_testbench03.x393_i.sensors393_i.rpage_next[3:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.sensors393_i.page_written[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.page_written[3:0]
(1)x393_testbench03.x393_i.sensors393_i.page_written[3:0]
(2)x393_testbench03.x393_i.sensors393_i.page_written[3:0]
(3)x393_testbench03.x393_i.sensors393_i.page_written[3:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.sensors393_i.buf_rd[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.buf_rd[3:0]
(1)x393_testbench03.x393_i.sensors393_i.buf_rd[3:0]
(2)x393_testbench03.x393_i.sensors393_i.buf_rd[3:0]
(3)x393_testbench03.x393_i.sensors393_i.buf_rd[3:0]
@1401200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.buf_dout[255:0]
@1401200
-all_channels
@800200
-chn0
-sensor_membuf_0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.prst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_valid
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.last_in_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.rpage_set
@c00028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.rst_pntr[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.rst_pntr[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.rst_pntr[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.rst_pntr[2:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.rpage_next
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_rd
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_dout[63:0]
@200
-
@1000200
-sensor_membuf_0
-chn0
-sensor_memory
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
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