Commit fbce217a authored by Andrey Filippov's avatar Andrey Filippov

minor code fixes to make it simulate with iverilog

parent 63198817
...@@ -8,4 +8,11 @@ ...@@ -8,4 +8,11 @@
</buildSpec> </buildSpec>
<natures> <natures>
</natures> </natures>
<linkedResources>
<link>
<name>ise_logs/ISEPartgen.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log</location>
</link>
</linkedResources>
</projectDescription> </projectDescription>
...@@ -246,8 +246,8 @@ module camsync (sclk, // @negedge ...@@ -246,8 +246,8 @@ module camsync (sclk, // @negedge
if (set_period) rep_en <= !high_zero; if (set_period) rep_en <= !high_zero;
end end
MSRL16 i_start_pclk16 (.Q(start_pclk16), .A('hf), .CLK(pclk), .D(start_pclk[2])); MSRL16 i_start_pclk16 (.Q(start_pclk16), .A(4'hf), .CLK(pclk), .D(start_pclk[2]));
MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A('hf), .CLK(pclk), .D(trigger1)); MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A(4'hf), .CLK(pclk), .D(trigger1));
//! synchronize start from sclk to pclk //! synchronize start from sclk to pclk
//! Generating repetition (period should be exactly N, not N+/-1) and output pulse //! Generating repetition (period should be exactly N, not N+/-1) and output pulse
......
...@@ -225,7 +225,7 @@ module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm); ...@@ -225,7 +225,7 @@ module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
assign Dq = Dq_out; assign Dq = Dq_out;
// Debug message // Debug message
wire Debug = 1'b1; // wire Debug = 1'b1;
// Timing Check // Timing Check
time MRD_chk; time MRD_chk;
......
...@@ -311,6 +311,7 @@ imu_timestamps i_imu_timestamps ( ...@@ -311,6 +311,7 @@ imu_timestamps i_imu_timestamps (
.ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored .ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
.ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high .ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
.dout(timestamps_rdata[15:0]));// output data .dout(timestamps_rdata[15:0]));// output data
wire [0:0] debug_state_unused;
rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal) rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles .bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles
.ser_di(ser_di), // rs232 (ttl) serial data in .ser_di(ser_di), // rs232 (ttl) serial data in
...@@ -322,7 +323,7 @@ rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal) ...@@ -322,7 +323,7 @@ rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.ser_do(ser_do), // serial data out(@posedge xclk) LSB first! .ser_do(ser_do), // serial data out(@posedge xclk) LSB first!
.ser_do_stb(ser_do_stb), // output data strobe (@posedge xclk), first cycle after ser_do becomes valid .ser_do_stb(ser_do_stb), // output data strobe (@posedge xclk), first cycle after ser_do becomes valid
// .debug(debug_state[4:0]), // .debug(debug_state[4:0]),
.debug(debug_state[15:12]), .debug({debug_state_unused,debug_state[15:12]}),
.bit_dur_cntr(debug_state[31:16]), .bit_dur_cntr(debug_state[31:16]),
.bit_cntr(debug_state[11:7]) .bit_cntr(debug_state[11:7])
); );
......
...@@ -497,16 +497,18 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2)) ...@@ -497,16 +497,18 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
reg [15:0] linAddr; reg [15:0] linAddr;
// wire [15:0] linAddr; //replacing with latches to ease timing // wire [15:0] linAddr; //replacing with latches to ease timing
wire [15:0] linAddr_input; wire [15:0] linAddr_input;
// assign linAddr_input[15:0] = (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}) +{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used wire [4:0] descr_stat_inc=descr_stat[8:4]+1;
assign linAddr_input[15:0] = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; assign linAddr_input[15:0] = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]};
always @ (negedge clk) if (stepsEn[1]) begin // address should be 1 always @ (negedge clk) if (stepsEn[1]) begin // address should be 1
//memctrl353/descrproc353.v:504: error: Concatenation operand "((descr_dyn['sd4:'sd0])==(descr_stat['sd13:'sd9]))?((descr_stat['sd8:'sd4])+('sd1)):(5'd0)" has indefinite width.
// seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
// ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0});
seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10 seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0}); ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat_inc):5'b0});
sa[7:3] <= mode?descr_dyn[4:0]:5'b0; sa[7:3] <= mode?descr_dyn[4:0]:5'b0;
linAddr[15:0] <= linAddr_input[15:0]; linAddr[15:0] <= linAddr_input[15:0];
// linAddr[15:0] <= (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]})+{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used
nxtTL <= nxtTLw; nxtTL <= nxtTLw;
tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0) tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0)
......
...@@ -174,14 +174,14 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -174,14 +174,14 @@ module lens_flat (sclk, /// system clock @negedge
// .A(FXY[17]?18'h1ffff:FXY[17:0]), // 18-bit multiplier input // .A(FXY[17]?18'h1ffff:FXY[17:0]), // 18-bit multiplier input
.A((FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff)), // 18-bit multiplier input .A((FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff)), // 18-bit multiplier input
.B({1'b0,scales[~color[1:0]]}), // 18-bit multiplier input .B({1'b0,scales[~color[1:0]]}), // 18-bit multiplier input
.BCIN(0), // 18-bit cascade input .BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[0]), // Clock enable input for the A port .CEA(lens_corr_out[0]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port .CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[1]), // Clock enable input for the P port .CEP(lens_corr_out[1]), // Clock enable input for the P port
.CLK(pclk), // Clock input .CLK(pclk), // Clock input
.RSTA(0), // Synchronous reset input for the A port .RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(0), // Synchronous reset input for the B port .RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(0) // Synchronous reset input for the P port .RSTP(1'b0) // Synchronous reset input for the P port
); );
...@@ -195,14 +195,14 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -195,14 +195,14 @@ module lens_flat (sclk, /// system clock @negedge
.P(mult_second_res[35:0]), // 36-bit multiplier output .P(mult_second_res[35:0]), // 36-bit multiplier output
.A(pix_zero[17:0]), // 18-bit multiplier input .A(pix_zero[17:0]), // 18-bit multiplier input
.B(mult_first_scaled[17:0]), // 18-bit multiplier input - always positive .B(mult_first_scaled[17:0]), // 18-bit multiplier input - always positive
.BCIN(0), // 18-bit cascade input .BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[2]), // Clock enable input for the A port .CEA(lens_corr_out[2]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port .CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[3]), // Clock enable input for the P port .CEP(lens_corr_out[3]), // Clock enable input for the P port
.CLK(pclk), // Clock input .CLK(pclk), // Clock input
.RSTA(0), // Synchronous reset input for the A port .RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(0), // Synchronous reset input for the B port .RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(0) // Synchronous reset input for the P port .RSTP(1'b0) // Synchronous reset input for the P port
); );
...@@ -216,7 +216,7 @@ lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result (signed) ...@@ -216,7 +216,7 @@ lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result (signed)
.first(fstart), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next" .first(fstart), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
.next(newline), /// calcualte next pixel .next(newline), /// calcualte next pixel
.F0(C[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned .F0(C[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned
.ERR0(0), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits .ERR0(24'b0), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
.A0(AY[18:0]), /// Ay .A0(AY[18:0]), /// Ay
.B0(BY[20:0]), /// By, signed .B0(BY[20:0]), /// By, signed
.F(FY[18:0]), .F(FY[18:0]),
......
...@@ -72,10 +72,11 @@ NET "hact_length*" TIG; ...@@ -72,10 +72,11 @@ NET "hact_length*" TIG;
*/ */
parameter MIN_VACT_PERIOD=130; // 3-130, to increase maximal value (130) - chnge counter width parameter MIN_VACT_PERIOD=130; // 3-130, to increase maximal value (130) - chnge counter width
`ifdef IVERILOG
parameter IS_SIMUL=0;
//synthesis translate_off
parameter IS_SIMUL=1; parameter IS_SIMUL=1;
`else
parameter IS_SIMUL=0;
`endif
//synthesis translate_on //synthesis translate_on
input cclk; // command clock (posedge, invert on input if needed) input cclk; // command clock (posedge, invert on input if needed)
......
...@@ -533,23 +533,23 @@ wire sensor_trigger; // signal to start CMOS sensor in sync mode ...@@ -533,23 +533,23 @@ wire sensor_trigger; // signal to start CMOS sensor in sync mode
wire confirmFrame2Compressor; // pulse to start reading a new frame to buffer for compressor (generated at start of each frame by the compressor) wire confirmFrame2Compressor; // pulse to start reading a new frame to buffer for compressor (generated at start of each frame by the compressor)
// mcontr will stop to read to channel FIFO at the end of frame, wait for confirmation // mcontr will stop to read to channel FIFO at the end of frame, wait for confirmation
`ifdef debug_compressor `ifdef debug_compressor
wire [31:0] printk_compressor; wire [31:0] printk_compressor;
`endif `endif
//ia //ia
`ifdef debug_stuffer `ifdef debug_stuffer
wire [7:0] testwire; wire [7:0] testwire;
//wire [31:0] printk; //wire [31:0] printk;
wire [3:0] tst_stuf_etrax; wire [3:0] tst_stuf_etrax;
reg [3:0] tst_cmd_cntr; reg [3:0] tst_cmd_cntr;
reg tst_rdy_after_eot; reg tst_rdy_after_eot;
// ,.test1( test_fifo[3:0]) // ,.test1( test_fifo[3:0])
// ,.test2( test_dma_wcntr[3:0]) // ,.test2( test_dma_wcntr[3:0])
wire dma0_enabled; // just for debug wire dma0_enabled; // just for debug
wire dma1_enabled; // just for debug wire dma1_enabled; // just for debug
`endif `endif
`ifdef debug_dma_count `ifdef debug_dma_count
wire [31:0] printk; wire [31:0] printk;
`endif `endif
/* /*
//xfer_over_irq //xfer_over_irq
......
...@@ -4,15 +4,15 @@ ...@@ -4,15 +4,15 @@
//`define PF //`define PF
//compressor waits for sensor //compressor waits for sensor
`define TEST_ABORT `define TEST_ABORT
`define SYNC_COMPRESS `define SYNC_COMPRESS
//TODO: when TEST_INSUFFICIENT_DATA, i_color_proc does not generate last0, because all_ready==0 when bcntr==0, //TODO: when TEST_INSUFFICIENT_DATA, i_color_proc does not generate last0, because all_ready==0 when bcntr==0,
// i.e. override ignore/ready from noMoreData until last0 // i.e. override ignore/ready from noMoreData until last0
//`define TEST_INSUFFICIENT_DATA //`define TEST_INSUFFICIENT_DATA
`define TRIGGERED_MODE `define TRIGGERED_MODE
`define CONTINUOUS_COMPRESSION `define CONTINUOUS_COMPRESSION
//`define TOO_HIGH_FPS //`define TOO_HIGH_FPS
`define ALL_SLOW_FPS `define ALL_SLOW_FPS
`define TEST_NO_WAIT_FRAME_SYNC `define TEST_NO_WAIT_FRAME_SYNC
//`define TRY_SLOW_FPS //`define TRY_SLOW_FPS
/// Enable flushing unfinished frame if there is no data in the memory (end of frame) /// Enable flushing unfinished frame if there is no data in the memory (end of frame)
...@@ -25,9 +25,9 @@ ...@@ -25,9 +25,9 @@
//`define FORCE_INTERNAL_TIMESTAMP // always use internal TS, ignore incoming //`define FORCE_INTERNAL_TIMESTAMP // always use internal TS, ignore incoming
`define TEST_BAD_FRAME //abbreviate one frame `define TEST_BAD_FRAME //abbreviate one frame
`define TEST_IMU `define TEST_IMU
module testbench353(); module testbench353();
parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses
...@@ -40,6 +40,13 @@ module testbench353(); ...@@ -40,6 +40,13 @@ module testbench353();
parameter CLK1_PER = 10.4; //96MHz parameter CLK1_PER = 10.4; //96MHz
parameter CLK3_PER = 83.33; //12MHz parameter CLK3_PER = 83.33; //12MHz
parameter CPU_PER=10.4; parameter CPU_PER=10.4;
`ifdef IVERILOG
initial $display("IVERILOG is defined");
`include "IVERILOG_INCLUDE.v"
`else
initial $display("IVERILOG is not defined");
parameter lxtname = "x353_1.lxt";
`endif
`ifdef SYNC_COMPRESS `ifdef SYNC_COMPRESS
parameter DEPEND=1'b1; parameter DEPEND=1'b1;
...@@ -84,12 +91,12 @@ module testbench353(); ...@@ -84,12 +91,12 @@ module testbench353();
wire [23:0] TRIG_PERIOD; wire [23:0] TRIG_PERIOD;
assign FRAME_COMPRESS_CYCLES=(WOI_WIDTH &'h3fff0) * (WOI_HEIGHT &'h3fff0) * CYCLES_PER_PIXEL + FPGA_XTRA_CYCLES; assign FRAME_COMPRESS_CYCLES=(WOI_WIDTH &'h3fff0) * (WOI_HEIGHT &'h3fff0) * CYCLES_PER_PIXEL + FPGA_XTRA_CYCLES;
assign FRAME_COMPRESS_CYCLES_INPUT=(FRAME_COMPRESS_CYCLES*CLK0_PER)/CLK1_PER; assign FRAME_COMPRESS_CYCLES_INPUT=(FRAME_COMPRESS_CYCLES*CLK0_PER)/CLK1_PER;
`ifdef ALL_SLOW_FPS `ifdef ALL_SLOW_FPS
assign TRIG_PERIOD = 2* FRAME_COMPRESS_CYCLES_INPUT; /// twice slower than maximal compressor can do assign TRIG_PERIOD = 2* FRAME_COMPRESS_CYCLES_INPUT; /// twice slower than maximal compressor can do
`else `else
`ifdef TOO_HIGH_FPS `ifdef TOO_HIGH_FPS
assign TRIG_PERIOD = VIRTUAL_WIDTH * (VIRTUAL_HEIGHT + TRIG_LINES + VBLANK); /// maximal sensor can do assign TRIG_PERIOD = VIRTUAL_WIDTH * (VIRTUAL_HEIGHT + TRIG_LINES + VBLANK); /// maximal sensor can do
`else `else
assign TRIG_PERIOD = FRAME_COMPRESS_CYCLES_INPUT; /// maximal compressor can do assign TRIG_PERIOD = FRAME_COMPRESS_CYCLES_INPUT; /// maximal compressor can do
// parameter TRIG_PERIOD= 1.5*(VIRTUAL_WIDTH * (VIRTUAL_HEIGHT + TRIG_LINES + VBLANK)); ///TODO: Improve (calculate) // parameter TRIG_PERIOD= 1.5*(VIRTUAL_WIDTH * (VIRTUAL_HEIGHT + TRIG_LINES + VBLANK)); ///TODO: Improve (calculate)
`endif `endif
...@@ -114,25 +121,25 @@ module testbench353(); ...@@ -114,25 +121,25 @@ module testbench353();
parameter X313_WA_IOPINS= 'h70; // bits [31:24] - enable channels (channel 0 -software, enabled at FPGA init) parameter X313_WA_IOPINS= 'h70; // bits [31:24] - enable channels (channel 0 -software, enabled at FPGA init)
parameter X313_WA_IOPINS_EN_TRIG_OUT= 'h0c000000; parameter X313_WA_IOPINS_EN_TRIG_OUT= 'h0c000000;
parameter X313_WA_IOPINS_DIS_TRIG_OUT='h08000000; parameter X313_WA_IOPINS_DIS_TRIG_OUT='h08000000;
parameter X313_WA_IOPINS_EN_IMU_OUT= 'hc0000000; parameter X313_WA_IOPINS_EN_IMU_OUT= 'hc0000000;
parameter X313_WA_IOPINS_DIS_IMU_OUT='h80000000; parameter X313_WA_IOPINS_DIS_IMU_OUT='h80000000;
parameter X313_WA_IMU_DATA= 'h7e; parameter X313_WA_IMU_DATA= 'h7e;
parameter X313_WA_IMU_CTRL= 'h7f; parameter X313_WA_IMU_CTRL= 'h7f;
parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check) parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready
parameter IMU_PERIOD= 'h800; // normal period parameter IMU_PERIOD= 'h800; // normal period
parameter IMU_AUTO_PERIOD= 'hffff0000; // period defined by IMU ready parameter IMU_AUTO_PERIOD= 'hffff0000; // period defined by IMU ready
parameter IMU_BIT_DURATION= 'h3; // actual F(scl) will be F(xclk)/2/(IMU_BIT_DURATION+1) parameter IMU_BIT_DURATION= 'h3; // actual F(scl) will be F(xclk)/2/(IMU_BIT_DURATION+1)
parameter IMU_READY_PERIOD=100000; //100usec parameter IMU_READY_PERIOD=100000; //100usec
parameter IMU_NREADY_DURATION=10000; //10usec parameter IMU_NREADY_DURATION=10000; //10usec
parameter IMU_GPS_BIT_PERIOD='h20; // serial communication duration of a bit (in system clocks) parameter IMU_GPS_BIT_PERIOD='h20; // serial communication duration of a bit (in system clocks)
// use start of trigger as a timestamp (in async mode to prevent timestamp jitter) // use start of trigger as a timestamp (in async mode to prevent timestamp jitter)
// parameter X313_WA_DCR1_EARLYTRIGEN='hc; //OBSOLETE! // parameter X313_WA_DCR1_EARLYTRIGEN='hc; //OBSOLETE!
...@@ -221,74 +228,74 @@ module testbench353(); ...@@ -221,74 +228,74 @@ module testbench353();
reg TEST_CPU_WR_OK; reg TEST_CPU_WR_OK;
reg TEST_CPU_RD_OK; reg TEST_CPU_RD_OK;
reg SERIAL_BIT = 1'b1; reg SERIAL_BIT = 1'b1;
reg GPS1SEC = 1'b0; reg GPS1SEC = 1'b0;
reg ODOMETER_PULSE= 1'b0; reg ODOMETER_PULSE= 1'b0;
integer SERIAL_DATA_FD; integer SERIAL_DATA_FD;
reg IMU_DATA_READY; reg IMU_DATA_READY;
/* /*
parameter IMU_READY_PERIOD=100000; //100usec parameter IMU_READY_PERIOD=100000; //100usec
parameter IMU_NREADY_DURATION=10000; //10usec parameter IMU_NREADY_DURATION=10000; //10usec
*/ */
`ifdef TEST_IMU `ifdef TEST_IMU
//wire [11:0] EXT; // bidirectional //wire [11:0] EXT; // bidirectional
wire IMU_SCL=EXT[0]; wire IMU_SCL=EXT[0];
wire IMU_SDA=EXT[1]; wire IMU_SDA=EXT[1];
wire IMU_MOSI=EXT[2]; wire IMU_MOSI=EXT[2];
wire IMU_MISO=EXT[3]; wire IMU_MISO=EXT[3];
reg IMU_EN; reg IMU_EN;
wire IMU_ACTIVE; wire IMU_ACTIVE;
wire IMU_NMOSI=!IMU_MOSI; wire IMU_NMOSI=!IMU_MOSI;
wire [5:1] IMU_TAPS; wire [5:1] IMU_TAPS;
reg IMU_LATE_ACKN; reg IMU_LATE_ACKN;
reg IMU_SCLK; reg IMU_SCLK;
reg IMU_MOSI_REVA; reg IMU_MOSI_REVA;
reg IMU_103695REVA; reg IMU_103695REVA;
wire IMU_MOSI_OUT; wire IMU_MOSI_OUT;
wire IMU_SCLK_OUT; wire IMU_SCLK_OUT;
assign IMU_MOSI_OUT=IMU_103695REVA?IMU_MOSI_REVA:IMU_MOSI; assign IMU_MOSI_OUT=IMU_103695REVA?IMU_MOSI_REVA:IMU_MOSI;
assign IMU_SCLK_OUT=IMU_103695REVA?(IMU_SCLK):IMU_SCL; assign IMU_SCLK_OUT=IMU_103695REVA?(IMU_SCLK):IMU_SCL;
always @ (posedge IMU_SDA) begin always @ (posedge IMU_SDA) begin
IMU_EN<=IMU_MOSI; IMU_EN<=IMU_MOSI;
end end
wire IMU_CS=IMU_103695REVA?!IMU_ACTIVE:!(IMU_EN &&IMU_SDA); wire IMU_CS=IMU_103695REVA?!IMU_ACTIVE:!(IMU_EN &&IMU_SDA);
reg IMU_MOSI_D; reg IMU_MOSI_D;
always @ (posedge IMU_SCLK_OUT) begin always @ (posedge IMU_SCLK_OUT) begin
// IMU_MOSI_D<=IMU_MOSI; // IMU_MOSI_D<=IMU_MOSI;
IMU_MOSI_D<=IMU_MOSI_OUT; IMU_MOSI_D<=IMU_MOSI_OUT;
end end
reg [15:0] IMU_LOOPBACK; reg [15:0] IMU_LOOPBACK;
always @ (negedge IMU_SCLK_OUT) begin always @ (negedge IMU_SCLK_OUT) begin
if (!IMU_CS) IMU_LOOPBACK[15:0]<={IMU_LOOPBACK[14:0],IMU_MOSI_D}; if (!IMU_CS) IMU_LOOPBACK[15:0]<={IMU_LOOPBACK[14:0],IMU_MOSI_D};
end end
assign EXT[3]=IMU_CS?IMU_DATA_READY:IMU_LOOPBACK[15]; assign EXT[3]=IMU_CS?IMU_DATA_READY:IMU_LOOPBACK[15];
PULLUP i_IMU_SDA (.O(IMU_SDA)); PULLUP i_IMU_SDA (.O(IMU_SDA));
PULLUP i_IMU_SCL (.O(IMU_SCL)); PULLUP i_IMU_SCL (.O(IMU_SCL));
initial begin initial begin
SERIAL_DATA_FD=$fopen("gps_data.dat","r"); SERIAL_DATA_FD=$fopen("gps_data.dat","r");
end end
always begin always begin
#(IMU_READY_PERIOD-IMU_NREADY_DURATION) IMU_DATA_READY=1'b0; #(IMU_READY_PERIOD-IMU_NREADY_DURATION) IMU_DATA_READY=1'b0;
#(IMU_NREADY_DURATION) IMU_DATA_READY=1'b1; #(IMU_NREADY_DURATION) IMU_DATA_READY=1'b1;
end end
assign EXT[4]=SERIAL_BIT; assign EXT[4]=SERIAL_BIT;
assign EXT[5]=GPS1SEC; assign EXT[5]=GPS1SEC;
assign EXT[6]=ODOMETER_PULSE; assign EXT[6]=ODOMETER_PULSE;
oneshot i_oneshot (.trigger(IMU_NMOSI), oneshot i_oneshot (.trigger(IMU_NMOSI),
.out(IMU_ACTIVE)); .out(IMU_ACTIVE));
dly5taps i_dly5taps (.dly_in(IMU_NMOSI), dly5taps i_dly5taps (.dly_in(IMU_NMOSI),
.dly_out(IMU_TAPS[5:1])); .dly_out(IMU_TAPS[5:1]));
always @ (negedge IMU_ACTIVE or posedge IMU_TAPS[5]) if (!IMU_ACTIVE) IMU_LATE_ACKN<= 1'b0; else IMU_LATE_ACKN<= 1'b1; always @ (negedge IMU_ACTIVE or posedge IMU_TAPS[5]) if (!IMU_ACTIVE) IMU_LATE_ACKN<= 1'b0; else IMU_LATE_ACKN<= 1'b1;
always @ (negedge IMU_LATE_ACKN or posedge IMU_TAPS[4]) if (!IMU_LATE_ACKN) IMU_SCLK<= 1'b1; else IMU_SCLK<= ~IMU_SCLK; always @ (negedge IMU_LATE_ACKN or posedge IMU_TAPS[4]) if (!IMU_LATE_ACKN) IMU_SCLK<= 1'b1; else IMU_SCLK<= ~IMU_SCLK;
always @ (negedge IMU_SCLK) IMU_MOSI_REVA<= IMU_NMOSI; always @ (negedge IMU_SCLK) IMU_MOSI_REVA<= IMU_NMOSI;
`endif `endif
// Inputs // Inputs
wire [11:0] PXD; wire [11:0] PXD;
...@@ -552,7 +559,8 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a ...@@ -552,7 +559,8 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
initial begin initial begin
$dumpfile("x353.lxt"); // $dumpfile("x353.lxt");
$dumpfile(lxtname);
$dumpvars(0,testbench353); $dumpvars(0,testbench353);
TTRIG = 1; TTRIG = 1;
CLK3 = 0; CLK3 = 0;
...@@ -577,41 +585,41 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a ...@@ -577,41 +585,41 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
BUS[7:0] =8'h0; BUS[7:0] =8'h0;
BUS_EN[7:0] =8'h0; BUS_EN[7:0] =8'h0;
BUS_RQ[7:0] =8'h0; BUS_RQ[7:0] =8'h0;
FOCUS_MODE = 2'h0; FOCUS_MODE = 2'h0;
IMU_103695REVA = 1'b0; IMU_103695REVA = 1'b0;
`ifdef LATE_DMA `ifdef LATE_DMA
`else `else
dma_en(0,1); dma_en(0,1);
`endif `endif
// temporary for IMU testing // temporary for IMU testing
// #200000; // #200000;
// $finish; // $finish;
#250000; #250000;
dma_en(0,1); dma_en(0,1);
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA = 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
#480000; cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
//#480000; cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA <= 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
#480000;
//#480000;
$finish; $finish;
`ifdef TEST_IMU `ifdef TEST_IMU
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
...@@ -630,7 +638,7 @@ $finish; ...@@ -630,7 +638,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -649,8 +657,8 @@ $finish; ...@@ -649,8 +657,8 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -668,7 +676,7 @@ $finish; ...@@ -668,7 +676,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -686,7 +694,7 @@ $finish; ...@@ -686,7 +694,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -704,7 +712,7 @@ $finish; ...@@ -704,7 +712,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -722,7 +730,7 @@ $finish; ...@@ -722,7 +730,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -740,7 +748,7 @@ $finish; ...@@ -740,7 +748,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -758,39 +766,40 @@ $finish; ...@@ -758,39 +766,40 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
`endif `endif
$finish; $finish;
//#250000; //#250000;
// dma_en(0,1); // dma_en(0,1);
//#480000; //#480000;
dma_en(0,1);
dma_en(0,1);
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA = 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
#480000; cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA <= 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
#480000;
$finish; $finish;
`ifdef TEST_IMU `ifdef TEST_IMU
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
...@@ -809,7 +818,7 @@ $finish; ...@@ -809,7 +818,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -828,8 +837,8 @@ $finish; ...@@ -828,8 +837,8 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -847,7 +856,7 @@ $finish; ...@@ -847,7 +856,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -865,7 +874,7 @@ $finish; ...@@ -865,7 +874,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -883,7 +892,7 @@ $finish; ...@@ -883,7 +892,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -901,7 +910,7 @@ $finish; ...@@ -901,7 +910,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -919,7 +928,7 @@ $finish; ...@@ -919,7 +928,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
...@@ -937,11 +946,11 @@ $finish; ...@@ -937,11 +946,11 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
`endif `endif
$finish; $finish;
//#250000; //#250000;
...@@ -951,30 +960,30 @@ $finish; ...@@ -951,30 +960,30 @@ $finish;
$finish; $finish;
end end
`ifdef TEST_IMU `ifdef TEST_IMU
initial begin initial begin
#10000; #10000;
while (!$feof (SERIAL_DATA_FD)) begin while (!$feof (SERIAL_DATA_FD)) begin
repeat (20*IMU_BIT_DURATION) begin wait (CLK0); wait (~CLK0); end repeat (20*IMU_BIT_DURATION) begin wait (CLK0); wait (~CLK0); end
send_serial_line; send_serial_line;
send_serial_bit('h0a); send_serial_bit('h0a);
GPS1SEC=1'b1; GPS1SEC=1'b1;
send_serial_line; send_serial_line;
send_serial_bit('h0a); send_serial_bit('h0a);
GPS1SEC=1'b0; GPS1SEC=1'b0;
send_serial_line; send_serial_line;
send_serial_bit('h0a); send_serial_bit('h0a);
send_serial_pause; send_serial_pause;
send_serial_pause; send_serial_pause;
ODOMETER_PULSE=1'b1; ODOMETER_PULSE=1'b1;
send_serial_pause; send_serial_pause;
ODOMETER_PULSE=1'b0; ODOMETER_PULSE=1'b0;
// repeat (20) send_serial_pause; // repeat (20) send_serial_pause;
end end
end end
`endif `endif
initial begin initial begin
#250000; #250000;
...@@ -1137,194 +1146,194 @@ end ...@@ -1137,194 +1146,194 @@ end
cpu_wr(X313_WA_CAMSYNCPER, SYNC_BIT_LENGTH); ///set (bit_length -1) (should be 2..255) cpu_wr(X313_WA_CAMSYNCPER, SYNC_BIT_LENGTH); ///set (bit_length -1) (should be 2..255)
cpu_wr(X313_WA_IOPINS, X313_WA_IOPINS_EN_TRIG_OUT); // Enable GPIO output from camsync module cpu_wr(X313_WA_IOPINS, X313_WA_IOPINS_EN_TRIG_OUT); // Enable GPIO output from camsync module
`ifdef TEST_IMU `ifdef TEST_IMU
cpu_wr(X313_WA_IOPINS, X313_WA_IOPINS_EN_IMU_OUT); // 'hc0000000; cpu_wr(X313_WA_IOPINS, X313_WA_IOPINS_EN_IMU_OUT); // 'hc0000000;
/* /*
reg we_config_imu; // bits 1:0, 2 - enable slot[1:0] reg we_config_imu; // bits 1:0, 2 - enable slot[1:0]
reg we_config_gps; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable reg we_config_gps; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_rst; // bit 16, 17 - enable - reset modules reg we_config_rst; // bit 16, 17 - enable - reset modules
*/ */
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
// cpu_wr(X313_WA_IMU_DATA, 'h3e695); // configure channels and reset // gps timestamp from 1sec input, positive // cpu_wr(X313_WA_IMU_DATA, 'h3e695); // configure channels and reset // gps timestamp from 1sec input, positive
// cpu_wr(X313_WA_IMU_DATA, 'h3e6b5); // configure channels and reset // gps timestamp from 1sec input, negative // cpu_wr(X313_WA_IMU_DATA, 'h3e6b5); // configure channels and reset // gps timestamp from 1sec input, negative
// cpu_wr(X313_WA_IMU_DATA, 'h3e6d5); // configure channels and reset // gps timestamp after pause // cpu_wr(X313_WA_IMU_DATA, 'h3e6d5); // configure channels and reset // gps timestamp after pause
// cpu_wr(X313_WA_IMU_DATA, 'h3e6f5); // configure channels and reset // gps timestamp at "$" start // cpu_wr(X313_WA_IMU_DATA, 'h3e6f5); // configure channels and reset // gps timestamp at "$" start
cpu_wr(X313_WA_IMU_DATA, 'h43e6f5); // configure channels and reset // gps timestamp at "$" start, reset configure_debug cpu_wr(X313_WA_IMU_DATA, 'h43e6f5); // configure channels and reset // gps timestamp at "$" start, reset configure_debug
cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration) cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration)
cpu_wr(X313_WA_IMU_DATA, 'h8007); // reset rs232 by 1 in MSB cpu_wr(X313_WA_IMU_DATA, 'h8007); // reset rs232 by 1 in MSB
cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration) cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration)
cpu_wr(X313_WA_IMU_DATA, 'h0007); // serial speed 8 cycles (period = 32 CLK0 cycles) cpu_wr(X313_WA_IMU_DATA, 'h0007); // serial speed 8 cycles (period = 32 CLK0 cycles)
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h20000); // remove reset cpu_wr(X313_WA_IMU_DATA, 'h20000); // remove reset
// encode 4 sentences // encode 4 sentences
/* /*
$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45 $GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B $GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36 $GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
*/ */
cpu_wr(X313_WA_IMU_CTRL, 'h20); // format write cpu_wr(X313_WA_IMU_CTRL, 'h20); // format write
// just ($GP)RMC, GGA, GSA and VTG // just ($GP)RMC, GGA, GSA and VTG
cpu_wr(X313_WA_IMU_DATA, 'h6); // cpu_wr(X313_WA_IMU_DATA, 'h6); //
cpu_wr(X313_WA_IMU_DATA, 'hf); // cpu_wr(X313_WA_IMU_DATA, 'hf); //
cpu_wr(X313_WA_IMU_DATA, 'he); // cpu_wr(X313_WA_IMU_DATA, 'he); //
cpu_wr(X313_WA_IMU_DATA, 'h0); // cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h9); // cpu_wr(X313_WA_IMU_DATA, 'h9); //
cpu_wr(X313_WA_IMU_DATA, 'h7); // cpu_wr(X313_WA_IMU_DATA, 'h7); //
cpu_wr(X313_WA_IMU_DATA, 'h6); // cpu_wr(X313_WA_IMU_DATA, 'h6); //
cpu_wr(X313_WA_IMU_DATA, 'hb); // cpu_wr(X313_WA_IMU_DATA, 'hb); //
cpu_wr(X313_WA_IMU_DATA, 'h1); // cpu_wr(X313_WA_IMU_DATA, 'h1); //
cpu_wr(X313_WA_IMU_DATA, 'hc); // cpu_wr(X313_WA_IMU_DATA, 'hc); //
cpu_wr(X313_WA_IMU_DATA, 'hf); // cpu_wr(X313_WA_IMU_DATA, 'hf); //
cpu_wr(X313_WA_IMU_DATA, 'h9); // cpu_wr(X313_WA_IMU_DATA, 'h9); //
cpu_wr(X313_WA_IMU_DATA, 'h8); // cpu_wr(X313_WA_IMU_DATA, 'h8); //
cpu_wr(X313_WA_IMU_DATA, 'h0); // cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h0); // cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h0); // cpu_wr(X313_WA_IMU_DATA, 'h0); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h30); // first format /// cpu_wr(X313_WA_IMU_CTRL, 'h30); // first format
//$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45 //$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
//0101010 000 : 'hb 'h2a 'h04 'h0 //0101010 000 : 'hb 'h2a 'h04 'h0
// cpu_wr(X313_WA_IMU_DATA, 'h0b); //number of fields including dummy comma // cpu_wr(X313_WA_IMU_DATA, 'h0b); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h0a); // testing - made 1 shorter than actual cpu_wr(X313_WA_IMU_DATA, 'h0a); // testing - made 1 shorter than actual
cpu_wr(X313_WA_IMU_DATA, 'h2a); // cpu_wr(X313_WA_IMU_DATA, 'h2a); //
cpu_wr(X313_WA_IMU_DATA, 'h04); // cpu_wr(X313_WA_IMU_DATA, 'h04); //
cpu_wr(X313_WA_IMU_DATA, 'h00); // cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h34); // second format /// cpu_wr(X313_WA_IMU_CTRL, 'h34); // second format
//$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B //$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
//0010 1000 0101 0 : 'h0e 'h14 'h0a 'h0 //0010 1000 0101 0 : 'h0e 'h14 'h0a 'h0
cpu_wr(X313_WA_IMU_DATA, 'h0e); //number of fields including dummy comma cpu_wr(X313_WA_IMU_DATA, 'h0e); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h14); // cpu_wr(X313_WA_IMU_DATA, 'h14); //
cpu_wr(X313_WA_IMU_DATA, 'h0a); // cpu_wr(X313_WA_IMU_DATA, 'h0a); //
cpu_wr(X313_WA_IMU_DATA, 'h00); // cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h38); // third format /// cpu_wr(X313_WA_IMU_CTRL, 'h38); // third format
//$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36 //$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
//01000000 00000000 00 : 'h11 'h01 'h00 'h0 //01000000 00000000 00 : 'h11 'h01 'h00 'h0
cpu_wr(X313_WA_IMU_DATA, 'h11); //number of fields including dummy comma cpu_wr(X313_WA_IMU_DATA, 'h11); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h01); // cpu_wr(X313_WA_IMU_DATA, 'h01); //
cpu_wr(X313_WA_IMU_DATA, 'h00); // cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_DATA, 'h00); // cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h3c); // fourth format /// cpu_wr(X313_WA_IMU_CTRL, 'h3c); // fourth format
//$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F //$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
//00101010 1 : 'h08 'haa 'h00 'h0 //00101010 1 : 'h08 'haa 'h00 'h0
cpu_wr(X313_WA_IMU_DATA, 'h08); //number of fields including dummy comma cpu_wr(X313_WA_IMU_DATA, 'h08); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'haa); // cpu_wr(X313_WA_IMU_DATA, 'haa); //
cpu_wr(X313_WA_IMU_DATA, 'h00); // cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_DATA, 'h00); // cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_CTRL, 4); // select register number 4
cpu_wr(X313_WA_IMU_DATA, 'h10); // x gyro low
cpu_wr(X313_WA_IMU_DATA, 'h12); // x gyro high
cpu_wr(X313_WA_IMU_DATA, 'h14); //
cpu_wr(X313_WA_IMU_DATA, 'h16); //
cpu_wr(X313_WA_IMU_DATA, 'h18); //
cpu_wr(X313_WA_IMU_DATA, 'h1a); //
cpu_wr(X313_WA_IMU_DATA, 'h1c); // x accel low
cpu_wr(X313_WA_IMU_DATA, 'h1e); //
cpu_wr(X313_WA_IMU_DATA, 'h20); //
cpu_wr(X313_WA_IMU_DATA, 'h22); //
cpu_wr(X313_WA_IMU_DATA, 'h24); //
cpu_wr(X313_WA_IMU_DATA, 'h26); // z accel high
cpu_wr(X313_WA_IMU_DATA, 'h40); // x delta ang low
cpu_wr(X313_WA_IMU_DATA, 'h42); // x delta ang high
cpu_wr(X313_WA_IMU_DATA, 'h44); //
cpu_wr(X313_WA_IMU_DATA, 'h46); //
cpu_wr(X313_WA_IMU_DATA, 'h48); //
cpu_wr(X313_WA_IMU_DATA, 'h4a); //
cpu_wr(X313_WA_IMU_DATA, 'h4c); // x delta vel low
cpu_wr(X313_WA_IMU_DATA, 'h4e); //
cpu_wr(X313_WA_IMU_DATA, 'h50); //
cpu_wr(X313_WA_IMU_DATA, 'h52); //
cpu_wr(X313_WA_IMU_DATA, 'h54); //
cpu_wr(X313_WA_IMU_DATA, 'h56); // z delta vel high
cpu_wr(X313_WA_IMU_CTRL, 4); // select register number 4 cpu_wr(X313_WA_IMU_DATA, 'h0e); // temperature
cpu_wr(X313_WA_IMU_DATA, 'h10); // x gyro low cpu_wr(X313_WA_IMU_DATA, 'h70); // time m/s
cpu_wr(X313_WA_IMU_DATA, 'h12); // x gyro high cpu_wr(X313_WA_IMU_DATA, 'h72); // time d/h
cpu_wr(X313_WA_IMU_DATA, 'h14); // cpu_wr(X313_WA_IMU_DATA, 'h74); // time y/m
cpu_wr(X313_WA_IMU_DATA, 'h16); //
cpu_wr(X313_WA_IMU_DATA, 'h18); // cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, 'h1a); // cpu_wr(X313_WA_IMU_DATA, 0); // reset IMU
cpu_wr(X313_WA_IMU_DATA, 'h1c); // x accel low cpu_wr(X313_WA_IMU_DATA, 0); // reset bit counter
cpu_wr(X313_WA_IMU_DATA, 'h1e); //
cpu_wr(X313_WA_IMU_DATA, 'h20); // #1000;
cpu_wr(X313_WA_IMU_DATA, 'h22); // cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, 'h24); // cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION); // set bit counter (clock frequency divider)
cpu_wr(X313_WA_IMU_DATA, 'h26); // z accel high
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, 'h40); // x delta ang low cpu_wr(X313_WA_IMU_DATA, IMU_PERIOD); // set period
cpu_wr(X313_WA_IMU_DATA, 'h42); // x delta ang high
cpu_wr(X313_WA_IMU_DATA, 'h44); // // set "odometer" message
cpu_wr(X313_WA_IMU_DATA, 'h46); // cpu_wr(X313_WA_IMU_CTRL, 'h40); // select start of message
cpu_wr(X313_WA_IMU_DATA, 'h48); // cpu_wr(X313_WA_IMU_DATA, 'h01234567); // Message first 4 bytes
cpu_wr(X313_WA_IMU_DATA, 'h4a); // cpu_wr(X313_WA_IMU_DATA, 'h12345678); //next
cpu_wr(X313_WA_IMU_DATA, 'h4c); // x delta vel low cpu_wr(X313_WA_IMU_DATA, 'h23456789); //next
cpu_wr(X313_WA_IMU_DATA, 'h4e); // cpu_wr(X313_WA_IMU_DATA, 'h3456789a); //next
cpu_wr(X313_WA_IMU_DATA, 'h50); // cpu_wr(X313_WA_IMU_DATA, 'h456789ab); //next
cpu_wr(X313_WA_IMU_DATA, 'h52); // cpu_wr(X313_WA_IMU_DATA, 'h56789abc); //next
cpu_wr(X313_WA_IMU_DATA, 'h54); // cpu_wr(X313_WA_IMU_DATA, 'h6789abcd); //next
cpu_wr(X313_WA_IMU_DATA, 'h56); // z delta vel high cpu_wr(X313_WA_IMU_DATA, 'h789abcde); //next
cpu_wr(X313_WA_IMU_DATA, 'h89abcdef); //next
cpu_wr(X313_WA_IMU_DATA, 'h0e); // temperature cpu_wr(X313_WA_IMU_DATA, 'h9abcdef0); //next
cpu_wr(X313_WA_IMU_DATA, 'h70); // time m/s cpu_wr(X313_WA_IMU_DATA, 'habcdef01); //next
cpu_wr(X313_WA_IMU_DATA, 'h72); // time d/h cpu_wr(X313_WA_IMU_DATA, 'hbcdef012); //next
cpu_wr(X313_WA_IMU_DATA, 'h74); // time y/m cpu_wr(X313_WA_IMU_DATA, 'hcdef0123); //next
cpu_wr(X313_WA_IMU_DATA, 'hdef01234); //next
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register // extra 8 bytes - will not be logged
cpu_wr(X313_WA_IMU_DATA, 0); // reset IMU cpu_wr(X313_WA_IMU_DATA, 'hef012345); //next
cpu_wr(X313_WA_IMU_DATA, 0); // reset bit counter cpu_wr(X313_WA_IMU_DATA, 'hf0123456); //next
#1000; // cpu_wr(1,32'h00000); // disable and reset dma
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register // cpu_wr(1,32'h20000); // enable DMA channel 1
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION); // set bit counter (clock frequency divider) cpu_wr(1,32'h00024); // disable and reset dma (both channels)
cpu_wr(1,32'h00028); // enable DMA channel 1
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register // cpu_wr(X313_WA_IMU_DATA, 1); // set period
cpu_wr(X313_WA_IMU_DATA, IMU_PERIOD); // set period
/*
// set "odometer" message
cpu_wr(X313_WA_IMU_CTRL, 'h40); // select start of message
cpu_wr(X313_WA_IMU_DATA, 'h01234567); // Message first 4 bytes
cpu_wr(X313_WA_IMU_DATA, 'h12345678); //next
cpu_wr(X313_WA_IMU_DATA, 'h23456789); //next
cpu_wr(X313_WA_IMU_DATA, 'h3456789a); //next
cpu_wr(X313_WA_IMU_DATA, 'h456789ab); //next
cpu_wr(X313_WA_IMU_DATA, 'h56789abc); //next
cpu_wr(X313_WA_IMU_DATA, 'h6789abcd); //next
cpu_wr(X313_WA_IMU_DATA, 'h789abcde); //next
cpu_wr(X313_WA_IMU_DATA, 'h89abcdef); //next
cpu_wr(X313_WA_IMU_DATA, 'h9abcdef0); //next
cpu_wr(X313_WA_IMU_DATA, 'habcdef01); //next
cpu_wr(X313_WA_IMU_DATA, 'hbcdef012); //next
cpu_wr(X313_WA_IMU_DATA, 'hcdef0123); //next
cpu_wr(X313_WA_IMU_DATA, 'hdef01234); //next
// extra 8 bytes - will not be logged
cpu_wr(X313_WA_IMU_DATA, 'hef012345); //next
cpu_wr(X313_WA_IMU_DATA, 'hf0123456); //next
// cpu_wr(1,32'h00000); // disable and reset dma
// cpu_wr(1,32'h20000); // enable DMA channel 1
cpu_wr(1,32'h00024); // disable and reset dma (both channels)
cpu_wr(1,32'h00028); // enable DMA channel 1
// cpu_wr(X313_WA_IMU_DATA, 1); // set period
/*
parameter X313_WA_IMU_DATA= 'h7e; parameter X313_WA_IMU_DATA= 'h7e;
parameter X313_WA_IMU_CTRL= 'h7f; parameter X313_WA_IMU_CTRL= 'h7f;
parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check) parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready
*/ */
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
cpu_rd_ce1(1); cpu_rd_ce1(1);
`endif `endif
program_quantization; program_quantization;
program_huffman; program_huffman;
program_curves; program_curves;
program_focus_filt; program_focus_filt;
program_coring; program_coring;
// lower 3 bits of left/right/top/bottom will be ignored. Window includes borders // lower 3 bits of left/right/top/bottom will be ignored. Window includes borders
// left[11:0], right[11:0], top[11:0], bottom[11:0], full_width[11:0], power, filter_sel[3:0]; // left[11:0], right[11:0], top[11:0], bottom[11:0], full_width[11:0], power, filter_sel[3:0];
...@@ -1578,8 +1587,8 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F ...@@ -1578,8 +1587,8 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
// cpu_wr(1, 32'h70000); // jpeg, dma enable - both channels !! // cpu_wr(1, 32'h70000); // jpeg, dma enable - both channels !!
// cpu_wr('h62,'h0d00000f); // cpu_wr('h62,'h0d00000f);
// cpu_wr('h62,'h01070000); // dma? // cpu_wr('h62,'h01070000); // dma?
cpu_wr('h62,'h0100002d); // dma enable, both channels cpu_wr('h62,'h0100002d); // dma enable, both channels
$display ("saturation=2"); $display ("saturation=2");
// cpu_wr(9, 32'h16c0120); // saturation=2 // cpu_wr(9, 32'h16c0120); // saturation=2
...@@ -1745,8 +1754,8 @@ task program_compressor; ...@@ -1745,8 +1754,8 @@ task program_compressor;
program_compressor ('h65,0,0,0, 2, 1,0,3); //focus mode 0 - sub dc, repetitive, mode 5 (jp46), shift 0 quality=100? program_compressor ('h65,0,0,0, 2, 1,0,3); //focus mode 0 - sub dc, repetitive, mode 5 (jp46), shift 0 quality=100?
program_compressor ('h66,0,0,0, 2, 1,1,3); //focus mode 0 - sub dc, repetitive, mode 2 (jp46), shift 0 quality=70? program_compressor ('h66,0,0,0, 2, 1,1,3); //focus mode 0 - sub dc, repetitive, mode 2 (jp46), shift 0 quality=70?
`endif `endif
`ifdef TEST_NO_WAIT_FRAME_SYNC `ifdef TEST_NO_WAIT_FRAME_SYNC
cpu_wr('h66,'h1a000002); // disable waiting for frame sync, leave waiting for dma fifo empty cpu_wr('h66,'h1a000002); // disable waiting for frame sync, leave waiting for dma fifo empty
`endif `endif
...@@ -1785,7 +1794,7 @@ task program_compressor; ...@@ -1785,7 +1794,7 @@ task program_compressor;
read256_ch3; read256_ch3;
`endif `endif
///TODO: There is a mixture of several test below, clean them up ///TODO: There is a mixture of several test below, clean them up
`ifdef TRY_SLOW_FPS `ifdef TRY_SLOW_FPS
wait (i_x353.i2c_frame_no[2:0]==7); wait (i_x353.i2c_frame_no[2:0]==7);
cpu_wr('h63,(X313_WA_CAMSYNCPER<<24) | 2*FRAME_COMPRESS_CYCLES_INPUT ); /// twice slower than frame compression cpu_wr('h63,(X313_WA_CAMSYNCPER<<24) | 2*FRAME_COMPRESS_CYCLES_INPUT ); /// twice slower than frame compression
...@@ -1795,7 +1804,7 @@ task program_compressor; ...@@ -1795,7 +1804,7 @@ task program_compressor;
`endif `endif
/* /*
// cpu_wr('h68,'h1a00800f); // ASAP enable waiting for frame sync, enable waiting for dma fifo empty, reset circuitry // cpu_wr('h68,'h1a00800f); // ASAP enable waiting for frame sync, enable waiting for dma fifo empty, reset circuitry
cpu_wr(X313_WA_DCR1, OUTPUTTS); // enables/disbles sending out timestamps with trigger pulse cpu_wr(X313_WA_DCR1, OUTPUTTS); // enables/disbles sending out timestamps with trigger pulse
...@@ -2302,7 +2311,7 @@ task program_quantization; ...@@ -2302,7 +2311,7 @@ task program_quantization;
end end
end end
endtask endtask
task program_coring; task program_coring;
// coring tables data // coring tables data
reg [15:0] coring_data[0:1023]; reg [15:0] coring_data[0:1023];
...@@ -2316,8 +2325,8 @@ task program_coring; ...@@ -2316,8 +2325,8 @@ task program_coring;
end end
end end
endtask endtask
task program_focus_filt; task program_focus_filt;
// focus quality filter data // focus quality filter data
...@@ -2478,84 +2487,84 @@ task program_compressor; ...@@ -2478,84 +2487,84 @@ task program_compressor;
end end
endtask endtask
task send_serial_bit; task send_serial_bit;
input [7:0] data_byte; input [7:0] data_byte;
reg [7:0] d; reg [7:0] d;
begin begin
d <= data_byte; d <= data_byte;
wait (CLK0); wait (~CLK0); wait (CLK0); wait (~CLK0);
// SERIAL_BIT should be 1 here // SERIAL_BIT should be 1 here
// Send start bit // Send start bit
SERIAL_BIT <= 1'b0; SERIAL_BIT <= 1'b0;
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
// Send 8 data bits, LSB first // Send 8 data bits, LSB first
repeat (8) begin repeat (8) begin
SERIAL_BIT <= d[0]; SERIAL_BIT <= d[0];
#1 d[7:0] <= {1'b0,d[7:1]}; #1 d[7:0] <= {1'b0,d[7:1]};
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end end
// Send stop bit // Send stop bit
SERIAL_BIT <= 1'b1; SERIAL_BIT <= 1'b1;
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end end
endtask endtask
task send_serial_pause; task send_serial_pause;
begin begin
wait (CLK0); wait (~CLK0); wait (CLK0); wait (~CLK0);
SERIAL_BIT <= 1'b1; SERIAL_BIT <= 1'b1;
repeat (16) begin repeat (16) begin
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end end
end end
endtask endtask
// SERIAL_DATA_FD=$fopen("gps_data.dat","r"); // SERIAL_DATA_FD=$fopen("gps_data.dat","r");
task send_serial_line; task send_serial_line;
integer char; integer char;
begin begin
char=0; char=0;
while (!$feof (SERIAL_DATA_FD) && (char != 'h0a)) begin while (!$feof (SERIAL_DATA_FD) && (char != 'h0a)) begin
char=$fgetc(SERIAL_DATA_FD); char=$fgetc(SERIAL_DATA_FD);
send_serial_bit(char); send_serial_bit(char);
end end
end end
endtask endtask
endmodule endmodule
module oneshot(trigger, module oneshot(trigger,
out); out);
input trigger; input trigger;
output out; output out;
reg out; reg out;
event start; event start;
parameter duration=4000; parameter duration=4000;
initial out= 0; initial out= 0;
always @ (posedge trigger) begin always @ (posedge trigger) begin
disable timeout; disable timeout;
#0 -> start; #0 -> start;
end end
always @start always @start
begin : timeout begin : timeout
out = 1; out = 1;
# duration out = 0; # duration out = 0;
end end
endmodule endmodule
module dly5taps (dly_in, module dly5taps (dly_in,
dly_out); dly_out);
input dly_in; input dly_in;
output [5:1] dly_out; output [5:1] dly_out;
reg [5:1] dly_out; reg [5:1] dly_out;
parameter dly=6; // delay per tap, ns parameter dly=6; // delay per tap, ns
always @ (dly_in) # dly dly_out[1] <= dly_in; always @ (dly_in) # dly dly_out[1] <= dly_in;
always @ (dly_out[1]) # dly dly_out[2] <= dly_out[1]; always @ (dly_out[1]) # dly dly_out[2] <= dly_out[1];
always @ (dly_out[2]) # dly dly_out[3] <= dly_out[2]; always @ (dly_out[2]) # dly dly_out[3] <= dly_out[2];
always @ (dly_out[3]) # dly dly_out[4] <= dly_out[3]; always @ (dly_out[3]) # dly dly_out[4] <= dly_out[3];
always @ (dly_out[4]) # dly dly_out[5] <= dly_out[4]; always @ (dly_out[4]) # dly dly_out[5] <= dly_out[4];
endmodule endmodule
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