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Commit d6e9be6b authored by Andrey Filippov's avatar Andrey Filippov
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fixing VDT warnings, splitting testbench file, adding modified primitive SLR version for simulation

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.project
View file @ d6e9be6b
...@@ -9,20 +9,50 @@ ...@@ -9,20 +9,50 @@
<natures> <natures>
</natures> </natures>
<linkedResources> <linkedResources>
<link>
<name>ise_logs/ISEMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEMap-20150726165658761.log</location>
</link>
<link>
<name>ise_logs/ISENGDBuild.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150726165546847.log</location>
</link>
<link>
<name>ise_logs/ISEPAR.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150726165911986.log</location>
</link>
<link> <link>
<name>ise_logs/ISEPartgen.log</name> <name>ise_logs/ISEPartgen.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log</location> <location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150726172041010.log</location>
</link>
<link>
<name>ise_logs/ISETraceMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150726213039147.log</location>
</link> </link>
<link> <link>
<name>ise_logs/ISExst.log</name> <name>ise_logs/ISExst.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150726141146079.log</location> <location>/home/andrey/git/x353/ise_logs/ISExst-20150726165049304.log</location>
</link>
<link>
<name>ise_state/x353-map.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-map-20150726165658761.tgz</location>
</link>
<link>
<name>ise_state/x353-ngdbuild.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150726165546847.tgz</location>
</link> </link>
<link> <link>
<name>ise_state/x353-synth.tgz</name> <name>ise_state/x353-synth.tgz</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150726135708468.tgz</location> <location>/home/andrey/git/x353/ise_state/x353-synth-20150726165049304.tgz</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
README.md
View file @ d6e9be6b
...@@ -18,7 +18,7 @@ Here is what makes it difficult: ...@@ -18,7 +18,7 @@ Here is what makes it difficult:
2. Last verion of the ISE (it is ISE 14.7) can not use the older code "as is" 2. Last verion of the ISE (it is ISE 14.7) can not use the older code "as is"
3. We were able to modify the Verilog code to be parsed by the current XST, but it does not 3. We were able to modify the Verilog code to be parsed by the current XST, but it does not
recognize some statements in the *.xcf constraints file (I had to rename original *.ucf to *.xcf). recognize some statements in the *.xcf constraints file (I had to rename original *.ucf to *.xcf).
4. Attempt to try old parser (Suggested by XST itself as the new parser is not the default for 4. Attempt to try old parser (suggested by XST itself as the new parser is not the default for
the Spartan 3e): the Spartan 3e):
``` ```
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default
......
compressor/color_proc353.v
View file @ d6e9be6b
...@@ -198,7 +198,7 @@ input hdr; // second green absolute, not difference ...@@ -198,7 +198,7 @@ input hdr; // second green absolute, not difference
reg four_blocks_r; reg four_blocks_r;
reg scale_diff_r; reg scale_diff_r;
reg hdr_r; reg hdr_r;
reg [1:0] tile_margin_r; reg [1:0] tile_margin_r; // SuppressThisWarning Veditor UNUSED
// reg [2:0] tile_shift_r; // reg [2:0] tile_shift_r;
reg [1:0] bayer_phase_r; reg [1:0] bayer_phase_r;
reg [3:0] bayer_phase_onehot; reg [3:0] bayer_phase_onehot;
...@@ -259,7 +259,7 @@ input hdr; // second green absolute, not difference ...@@ -259,7 +259,7 @@ input hdr; // second green absolute, not difference
last_from_sdram <= en & preline_was_0 && (prepix[4:0]==0); last_from_sdram <= en & preline_was_0 && (prepix[4:0]==0);
inc_sdrama <= en & (pre_first_pixel || (inc_sdrama && !last_from_sdram )); inc_sdrama <= en & (pre_first_pixel || (inc_sdrama && !last_from_sdram ));
if (pre_first_pixel) sdram_a9[8:0] <= sdrama_top_left[8:0]; if (pre_first_pixel) sdram_a9[8:0] <= sdrama_top_left[8:0];
else if (inc_sdrama) sdram_a9[8:0] <= sdram_a9[8:0] + (pre_start_of_line ? sdrama_line_inc[2:0] : 1); else if (inc_sdrama) sdram_a9[8:0] <= sdram_a9[8:0] + (pre_start_of_line ? sdrama_line_inc[2:0] : 3'b1);
if (!en || memWasInit) sdram_a9_page[1:0] <= 2'h0; if (!en || memWasInit) sdram_a9_page[1:0] <= 2'h0;
else if (last_from_sdram && inc_sdrama) sdram_a9_page[1:0] <= sdram_a9_page[1:0]+1; else if (last_from_sdram && inc_sdrama) sdram_a9_page[1:0] <= sdram_a9_page[1:0]+1;
...@@ -445,7 +445,7 @@ input hdr; // second green absolute, not difference ...@@ -445,7 +445,7 @@ input hdr; // second green absolute, not difference
if (first_pixel) begin if (first_pixel) begin
first0 <= willbe_first; first0 <= willbe_first;
last0 <= (bcntr[17:0]==17'b0); last0 <= (bcntr[17:0] == 18'b0);
end end
if (ccv_out_start) begin if (ccv_out_start) begin
first <= first0; first <= first0;
......
compressor/compressor333.v
View file @ d6e9be6b
...@@ -220,8 +220,8 @@ module compressor(// cwr, // CPU write - global clock ...@@ -220,8 +220,8 @@ module compressor(// cwr, // CPU write - global clock
// //
// control registetr bits // control registetr bits
wire cr_w; // data written to cr (1 cycle) - now just to reset legacy IRQ wire cr_w; // data written to cr (1 cycle) - now just to reset legacy IRQ
wire raw_dv; // input pixel data valid (pxd[7:0]may be sent to DMA buffer through multiplexor) wire raw_dv; // input pixel data valid (pxd[7:0]may be sent to DMA buffer through multiplexor) // SuppressThisWarning Veditor UNUSED
wire color_dv; // unused // color data valid (color_d[7:0] may be sent to DMA buffer through multiplexor) wire color_dv; // unused // color data valid (color_d[7:0] may be sent to DMA buffer through multiplexor)// SuppressThisWarning Veditor UNUSED
wire [ 9:0] color_d; // data out stream from color space converter (6X64 blocks for each MCU - 4Y, Cb,Cr) wire [ 9:0] color_d; // data out stream from color space converter (6X64 blocks for each MCU - 4Y, Cb,Cr)
wire [ 2:0] color_tn; // tile number in an MCU from color space converter (valid @ color_dv) wire [ 2:0] color_tn; // tile number in an MCU from color space converter (valid @ color_dv)
wire [ 8:0] color_avr; // [8:0] DC (average value) 9 bit signed for Y: 9'h000..9'h0ff, for C - 9h100..9'h000..9'h0ff wire [ 8:0] color_avr; // [8:0] DC (average value) 9 bit signed for Y: 9'h000..9'h0ff, for C - 9h100..9'h000..9'h0ff
...@@ -230,7 +230,7 @@ module compressor(// cwr, // CPU write - global clock ...@@ -230,7 +230,7 @@ module compressor(// cwr, // CPU write - global clock
// wire dct_en; // wire dct_en;
wire dct_start; wire dct_start;
wire dct_dv; wire dct_dv; // SuppressThisWarning Veditor UNUSED
wire [12:0] dct_out; wire [12:0] dct_out;
wire dct_last_in; // output high during input of the last of 64 pixels in a 8x8 block wire dct_last_in; // output high during input of the last of 64 pixels in a 8x8 block
wire dct_pre_first_out; // 1 cycle ahead of the first output in a 64 block wire dct_pre_first_out; // 1 cycle ahead of the first output in a 64 block
...@@ -245,7 +245,7 @@ module compressor(// cwr, // CPU write - global clock ...@@ -245,7 +245,7 @@ module compressor(// cwr, // CPU write - global clock
wire focus_ds; wire focus_ds;
// wire enc_first; // wire enc_first;
wire enc_last; wire enc_last; // SuppressThisWarning Veditor UNUSED
wire [15:0] enc_do; wire [15:0] enc_do;
wire enc_dv; wire enc_dv;
...@@ -664,8 +664,8 @@ FD i_is_compressing (.Q(is_compressing),.C(clk), .D(cmprs_en && (go_single || (i ...@@ -664,8 +664,8 @@ FD i_is_compressing (.Q(is_compressing),.C(clk), .D(cmprs_en && (go_single || (i
// single-cycle @ negedge sclk // single-cycle @ negedge sclk
`ifdef debug_compressor `ifdef debug_compressor
wire debug_bcntrIsZero; wire debug_bcntrIsZero;
wire [17:0] debug_bcntr; wire [17:0] debug_bcntr; //SuppressThisWarning Veditor UNUSED
`endif `endif
color_proc i_color_proc(.clk(clk), // pixel clock 37.5MHz color_proc i_color_proc(.clk(clk), // pixel clock 37.5MHz
.en(cmprs_en), // Enable (0 will reset states) .en(cmprs_en), // Enable (0 will reset states)
...@@ -1080,7 +1080,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk) ...@@ -1080,7 +1080,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk)
reg [23:0] cr; ///AF: reg [23:0] cr;
reg [17:0] ntiles; reg [17:0] ntiles;
reg [15:0] ntiles0; reg [15:0] ntiles0;
reg [17:0] ntiles1; reg [17:0] ntiles1;
...@@ -1095,7 +1095,8 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk) ...@@ -1095,7 +1095,8 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk)
assign rcs[1:0]={cwe && rs, cwe && ~rs}; assign rcs[1:0]={cwe && rs, cwe && ~rs};
reg rcs0_d, rcs0_dd, rcs1_d; reg rcs0_d, rcs0_dd;
///AF: reg rcs1_d;
reg [2:0] rcs1d; reg [2:0] rcs1d;
reg [1:0] is_compressing_sclk; // sync to negedge sclk reg [1:0] is_compressing_sclk; // sync to negedge sclk
...@@ -1168,7 +1169,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk) ...@@ -1168,7 +1169,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk)
// always @ (posedge clk) cr[23:0] <=cri[23:0]; // make it sync // always @ (posedge clk) cr[23:0] <=cri[23:0]; // make it sync
always @ (negedge sclk) if (rcs[1]) ntiles0[15:0] <= di[15:0]; always @ (negedge sclk) if (rcs[1]) ntiles0[15:0] <= di[15:0];
// always @ (negedge sclk) if (rcs1_d) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]}; // always @ (negedge sclk) if (rcs1_d) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]};
always @ (negedge sclk) if (rcs1d[0]) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]}; always @ (negedge sclk) if (rcs1d[0]) ntiles1[17:0] <= {di[ 1:0],ntiles0[15:0]};
always @ (negedge sclk) if (rcs1d[2]) ntiles1_prev[17:0] <= ntiles1[17:0]; always @ (negedge sclk) if (rcs1d[2]) ntiles1_prev[17:0] <= ntiles1[17:0];
// rcs1d[2:0]<={rcs1d[1:0],rcs[1]}; // rcs1d[2:0]<={rcs1d[1:0],rcs[1]};
......
compressor/csconvert_mono.v
View file @ d6e9be6b
...@@ -129,7 +129,10 @@ module csconvert_jp4diff (en, ...@@ -129,7 +129,10 @@ module csconvert_jp4diff (en,
reg dly_1; reg dly_1;
reg [14:0] dly_16; reg [14:0] dly_16;
reg dly_17; reg dly_17;
wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17:dly_16):(bayer_phase[0]?dly_1:pre_first_in); // wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17:dly_16):(bayer_phase[0]?dly_1:pre_first_in);
///AF2015 - What was supposed to be here for "dly_16" (15 bits, expected 1) - any non-zero or [14]?
// wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: (|dly_16)):(bayer_phase[0]?dly_1:pre_first_in);
wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: dly_16[14]):(bayer_phase[0]?dly_1:pre_first_in);
reg [7:0] iadr; reg [7:0] iadr;
reg iadr_run; reg iadr_run;
reg [1:0] mux_plus_sel; reg [1:0] mux_plus_sel;
......
compressor/focus_sharp.v
View file @ d6e9be6b
...@@ -234,7 +234,8 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0]; ...@@ -234,7 +234,8 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0];
use_k_dly[5:0]<={use_k_dly[4:0],use_coef}; use_k_dly[5:0]<={use_k_dly[4:0],use_coef};
acc_ldval <= !(|start2[7:6]); acc_ldval <= !(|start2[7:6]);
if (acc_clear || (acc_corr && acc_blk[23])) acc_blk[23:0] <= {1'b0,{23{acc_ldval}}}; if (acc_clear || (acc_corr && acc_blk[23])) acc_blk[23:0] <= {1'b0,{23{acc_ldval}}};
else if (acc_add) acc_blk[23:0] <= acc_blk[23:0]+mult_p[35:8]; ///AF: else if (acc_add) acc_blk[23:0] <= acc_blk[23:0]+mult_p[35:8];
else if (acc_add) acc_blk[23:0] <= acc_blk[23:0]+mult_p[31:8];
if (acc_to_out) fdo[11:0] <= (|acc_blk[23:20])?12'hfff:acc_blk[19:8]; // positive, 0..0xfff if (acc_to_out) fdo[11:0] <= (|acc_blk[23:20])?12'hfff:acc_blk[19:8]; // positive, 0..0xfff
if (acc_to_out) sum_blk[22:0] <= acc_blk[22:0]; // accumulator for the sum ((a[i]*d[i])^2), copied at block end if (acc_to_out) sum_blk[22:0] <= acc_blk[22:0]; // accumulator for the sum ((a[i]*d[i])^2), copied at block end
...@@ -291,17 +292,11 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0]; ...@@ -291,17 +292,11 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0];
); );
RAM16X1D i_tn0 (.D(tni[0]),.DPO(tn[0]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn1 (.D(tni[1]),.DPO(tn[1]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn2 (.D(tni[2]),.DPO(tn[2]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_first (.D(firsti),.DPO(first),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn0 (.D(tni[0]),.DPO(tn[0]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb)); RAM16X1D i_last (.D(lasti), .DPO(last), .A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn1 (.D(tni[1]),.DPO(tn[1]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_tn2 (.D(tni[2]),.DPO(tn[2]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_first (.D(firsti),.DPO(first),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_last (.D(lasti), .DPO(last), .A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAMB16_S18_S18 i_focus_dct_tab ( RAMB16_S18_S18 i_focus_dct_tab (
.DOA(tdo[15:0]), // Port A 16-bit Data Output .DOA(tdo[15:0]), // Port A 16-bit Data Output
......
compressor/huffman333.v
View file @ d6e9be6b
...@@ -70,7 +70,7 @@ module huffman (pclk, // half frequency, sync to incoming data ...@@ -70,7 +70,7 @@ module huffman (pclk, // half frequency, sync to incoming data
wire [19:0] tables_out; wire [19:0] tables_out;
wire [15:0] hcode; // table output huffman code (1..16 bits) wire [15:0] hcode; // table output huffman code (1..16 bits)
wire [ 3:0] hlen; // table - code length only 4 LSBs are used wire [ 3:0] hlen; // table - code length only 4 LSBs are used
wire [11:0] unused; wire [11:0] unused; // SuppressThisWarning Veditor UNUSED
reg [ 7:0] haddr_r; // index in huffman table reg [ 7:0] haddr_r; // index in huffman table
wire [ 7:0] haddr_next; wire [ 7:0] haddr_next;
wire [ 8:0] haddr; // index in huffman table (after latches) wire [ 8:0] haddr; // index in huffman table (after latches)
...@@ -340,7 +340,7 @@ module huff_fifo (pclk, ...@@ -340,7 +340,7 @@ module huff_fifo (pclk,
reg [9:0] ra_r; reg [9:0] ra_r;
wire [9:0] ra; wire [9:0] ra;
wire [15:0] q; wire [15:0] q;
reg load_q; reg load_q; // SuppressThisWarning Veditor VDT_BUG
wire [15:0] fifo_o; wire [15:0] fifo_o;
reg ds1; // ds delayed by one pclk to give time to block ram to write data. Not needed likely. reg ds1; // ds delayed by one pclk to give time to block ram to write data. Not needed likely.
reg synci; reg synci;
...@@ -404,7 +404,6 @@ module huff_fifo (pclk, ...@@ -404,7 +404,6 @@ module huff_fifo (pclk,
LD i_ra1 (.Q(ra[1]),.G(clk),.D(ra_r[1])); LD i_ra1 (.Q(ra[1]),.G(clk),.D(ra_r[1]));
LD i_ra0 (.Q(ra[0]),.G(clk),.D(ra_r[0])); LD i_ra0 (.Q(ra[0]),.G(clk),.D(ra_r[0]));
always @ (posedge clk) begin always @ (posedge clk) begin
// load_q <= dav?want_read:re_r;
load_q <= dav?want_read_early:re_r; load_q <= dav?want_read_early:re_r;
end end
LD_1 i_q15 (.Q( q[15]),.G(clk),.D(load_q?fifo_o[15]:q[15])); LD_1 i_q15 (.Q( q[15]),.G(clk),.D(load_q?fifo_o[15]:q[15]));
......
compressor/xdct353.v
View file @ d6e9be6b
...@@ -223,6 +223,7 @@ This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of t ...@@ -223,6 +223,7 @@ This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of t
reg[9:0] xa0_in, xa1_in, xa2_in, xa3_in, xa4_in, xa5_in, xa6_in, xa7_in; reg[9:0] xa0_in, xa1_in, xa2_in, xa3_in, xa4_in, xa5_in, xa6_in, xa7_in;
reg[9:0] xa0_reg, xa1_reg, xa2_reg, xa3_reg, xa4_reg, xa5_reg, xa6_reg, xa7_reg; reg[9:0] xa0_reg, xa1_reg, xa2_reg, xa3_reg, xa4_reg, xa5_reg, xa6_reg, xa7_reg;
reg[9:0] addsub1a_comp,addsub2a_comp,addsub3a_comp,addsub4a_comp; reg[9:0] addsub1a_comp,addsub2a_comp,addsub3a_comp,addsub4a_comp;
reg[10:0] add_sub1a,add_sub2a,add_sub3a,add_sub4a; reg[10:0] add_sub1a,add_sub2a,add_sub3a,add_sub4a;
reg save_sign1a, save_sign2a, save_sign3a, save_sign4a; reg save_sign1a, save_sign2a, save_sign3a, save_sign4a;
reg[17:0] p1a,p2a,p3a,p4a; reg[17:0] p1a,p2a,p3a,p4a;
...@@ -384,15 +385,22 @@ always @ (negedge clk) ...@@ -384,15 +385,22 @@ always @ (negedge clk)
// 9th clk for registering shifted input and 10th clk for add_sub // 9th clk for registering shifted input and 10th clk for add_sub
// to synchronize the i value to the add_sub value, i value is incremented // to synchronize the i value to the add_sub value, i value is incremented
// only after 10 clks // only after 10 clks
// Adding these wires to get rid of the MSB that is always 0
wire [10:0] addsub1a_comp_w = add_sub1a[10]? (-add_sub1a) : add_sub1a;
wire [10:0] addsub2a_comp_w = add_sub2a[10]? (-add_sub2a) : add_sub2a;
wire [10:0] addsub3a_comp_w = add_sub3a[10]? (-add_sub3a) : add_sub3a;
wire [10:0] addsub4a_comp_w = add_sub4a[10]? (-add_sub4a) : add_sub4a;
always @ (negedge clk) begin always @ (negedge clk) begin
save_sign1a <= add_sub1a[10]; save_sign1a <= add_sub1a[10];
save_sign2a <= add_sub2a[10]; save_sign2a <= add_sub2a[10];
save_sign3a <= add_sub3a[10]; save_sign3a <= add_sub3a[10];
save_sign4a <= add_sub4a[10]; save_sign4a <= add_sub4a[10];
addsub1a_comp <= add_sub1a[10]? (-add_sub1a) : add_sub1a; addsub1a_comp <= addsub1a_comp_w[9:0]; //add_sub1a[10]? (-add_sub1a) : add_sub1a;
addsub2a_comp <= add_sub2a[10]? (-add_sub2a) : add_sub2a; addsub2a_comp <= addsub2a_comp_w[9:0]; //add_sub2a[10]? (-add_sub2a) : add_sub2a;
addsub3a_comp <= add_sub3a[10]? (-add_sub3a) : add_sub3a; addsub3a_comp <= addsub3a_comp_w[9:0]; //add_sub3a[10]? (-add_sub3a) : add_sub3a;
addsub4a_comp <= add_sub4a[10]? (-add_sub4a) : add_sub4a; addsub4a_comp <= addsub4a_comp_w[9:0]; //add_sub4a[10]? (-add_sub4a) : add_sub4a;
end end
assign p1a_all = addsub1a_comp * memory1a[15:0]; assign p1a_all = addsub1a_comp * memory1a[15:0];
...@@ -504,7 +512,7 @@ wire sxregs; ...@@ -504,7 +512,7 @@ wire sxregs;
wire sxregs_d8; wire sxregs_d8;
reg enable_toggle; reg enable_toggle;
reg en_started; reg en_started;
wire disdv;
SRL16 i_endv (.Q(endv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(start)); // dly=14+1 SRL16 i_endv (.Q(endv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(start)); // dly=14+1
SRL16 i_disdv (.Q(disdv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(rd_cntr[5:0]==6'h3f)); // dly=14+1 SRL16 i_disdv (.Q(disdv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(rd_cntr[5:0]==6'h3f)); // dly=14+1
...@@ -621,6 +629,11 @@ always @ (posedge clk) ...@@ -621,6 +629,11 @@ always @ (posedge clk)
add_sub4b <= ({xb4_reg[15],xb4_reg[15:0]} - {xb3_reg[15],xb3_reg[15:0]}); add_sub4b <= ({xb4_reg[15],xb4_reg[15:0]} - {xb3_reg[15],xb3_reg[15:0]});
end end
// Adding these wires to get rid of the MSB that is always 0
wire [16:0] addsub1b_comp_w = add_sub1b[16]? (-add_sub1b) : add_sub1b;
wire [16:0] addsub2b_comp_w = add_sub2b[16]? (-add_sub2b) : add_sub2b;
wire [16:0] addsub3b_comp_w = add_sub3b[16]? (-add_sub3b) : add_sub3b;
wire [16:0] addsub4b_comp_w = add_sub4b[16]? (-add_sub4b) : add_sub4b;
always @ (posedge clk) begin always @ (posedge clk) begin
// save_sign1b <= add_sub1b[10]; // save_sign1b <= add_sub1b[10];
...@@ -635,21 +648,26 @@ always @ (posedge clk) begin ...@@ -635,21 +648,26 @@ always @ (posedge clk) begin
save_sign2b <= add_sub2b[16]; save_sign2b <= add_sub2b[16];
save_sign3b <= add_sub3b[16]; save_sign3b <= add_sub3b[16];
save_sign4b <= add_sub4b[16]; save_sign4b <= add_sub4b[16];
addsub1b_comp <= add_sub1b[16]? (-add_sub1b) : add_sub1b; addsub1b_comp <= addsub1b_comp_w[15:0]; // add_sub1b[16]? (-add_sub1b) : add_sub1b;
addsub2b_comp <= add_sub2b[16]? (-add_sub2b) : add_sub2b; addsub2b_comp <= addsub2b_comp_w[15:0]; // add_sub2b[16]? (-add_sub2b) : add_sub2b;
addsub3b_comp <= add_sub3b[16]? (-add_sub3b) : add_sub3b; addsub3b_comp <= addsub3b_comp_w[15:0]; // add_sub3b[16]? (-add_sub3b) : add_sub3b;
addsub4b_comp <= add_sub4b[16]? (-add_sub4b) : add_sub4b; addsub4b_comp <= addsub4b_comp_w[15:0]; // add_sub4b[16]? (-add_sub4b) : add_sub4b;
end end
// assign p1b_all = addsub1b_comp * memory1a[15:0]; // assign p1b_all = addsub1b_comp * memory1a[15:0];
// assign p2b_all = addsub2b_comp * memory2a[15:0]; // assign p2b_all = addsub2b_comp * memory2a[15:0];
// assign p3b_all = addsub3b_comp * memory3a[15:0]; // assign p3b_all = addsub3b_comp * memory3a[15:0];
// assign p4b_all = addsub4b_comp * memory4a[15:0]; // assign p4b_all = addsub4b_comp * memory4a[15:0];
assign p1b_all = addsub1b_comp[15:0] * memory1a[15:0]; ///AF2015:
assign p2b_all = addsub2b_comp[15:0] * memory2a[15:0]; // assign p1b_all = addsub1b_comp[15:0] * memory1a[15:0];
assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0]; // assign p2b_all = addsub2b_comp[15:0] * memory2a[15:0];
assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0]; // assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0];
// assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0];
assign p1b_all = addsub1b_comp * memory1a;
assign p2b_all = addsub2b_comp * memory2a;
assign p3b_all = addsub3b_comp * memory3a;
assign p4b_all = addsub4b_comp * memory4a;
always @ (posedge clk) always @ (posedge clk)
begin begin
......
control/camsync.v
View file @ d6e9be6b
...@@ -119,7 +119,7 @@ module camsync (sclk, // @negedge ...@@ -119,7 +119,7 @@ module camsync (sclk, // @negedge
reg [31:0] restart_cntr; // restart period counter reg [31:0] restart_cntr; // restart period counter
reg [1:0] restart_cntr_run; // restart counter running reg [1:0] restart_cntr_run; // restart counter running
wire restart; // restart out sync wire restart; // restart out sync
reg [8:0] out_pulse_cntr; ///AF: reg [8:0] out_pulse_cntr;
reg trigger_condition; // GPIO input trigger condition met reg trigger_condition; // GPIO input trigger condition met
reg trigger_condition_d; // GPIO input trigger condition met, delayed (for edge detection) reg trigger_condition_d; // GPIO input trigger condition met, delayed (for edge detection)
reg trigger_condition_filtered; // trigger condition filtered reg trigger_condition_filtered; // trigger condition filtered
...@@ -140,7 +140,7 @@ module camsync (sclk, // @negedge ...@@ -140,7 +140,7 @@ module camsync (sclk, // @negedge
wire pre_start_out_pulse; wire pre_start_out_pulse;
reg start_out_pulse; /// start generation of output pulse. In internal trigger mode uses delay counter, in external - no delay reg start_out_pulse; /// start generation of output pulse. In internal trigger mode uses delay counter, in external - no delay
reg pre_start; ///AF: reg pre_start;
reg [31:0] pre_period; reg [31:0] pre_period;
reg [ 7:0] bit_length='hff; /// Output pulse duration or bit duration in timestamp mode reg [ 7:0] bit_length='hff; /// Output pulse duration or bit duration in timestamp mode
/// input will be filtered with (bit_length>>2) duration /// input will be filtered with (bit_length>>2) duration
...@@ -228,7 +228,7 @@ module camsync (sclk, // @negedge ...@@ -228,7 +228,7 @@ module camsync (sclk, // @negedge
// if (wen[3]) repeat_period[31:0] <= did[31:0]; // if (wen[3]) repeat_period[31:0] <= did[31:0];
if (wen[3]) pre_period[31:0] <= did[31:0]; if (wen[3]) pre_period[31:0] <= did[31:0];
if (wen[3]) high_zero = did[31:8]==24'b0; if (wen[3]) high_zero <= did[31:8]==24'b0;
// start <= wen[3] && (did[31:0]!=32'h0); // start <= wen[3] && (did[31:0]!=32'h0);
......
control/clkios353.v
View file @ d6e9be6b
...@@ -45,7 +45,7 @@ module dcm333( ...@@ -45,7 +45,7 @@ module dcm333(
output xclk; output xclk;
output SDCLK, SDNCLK; output SDCLK, SDNCLK;
input [1:0] phsel; input [1:0] phsel;
input sdcl_fb; input sdcl_fb; // SuppressThisWarning Veditor UNUSED - was designed to use external pin sync (maybe still use it?)
input dcm_rst, dcm_incdec, dcm_en, dcm_clk; input dcm_rst, dcm_incdec, dcm_en, dcm_clk;
output dcm_done; output dcm_done;
......
control/cmd_sequencer.v
View file @ d6e9be6b
...@@ -160,7 +160,7 @@ FD_1 i_initialized ( .Q(initialized), .C(sclk), .D(por[1] && ( initialized || (r ...@@ -160,7 +160,7 @@ FD_1 i_initialized ( .Q(initialized), .C(sclk), .D(por[1] && ( initialized || (r
we_fifo_wp <= wen_d[1] || wpage0_inc; we_fifo_wp <= wen_d[1] || wpage0_inc;
if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0]; if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 7'h0:(fifo_wr_pointers_outw_r[5:0]+1); if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri
// command seq fifo (RAMB16_S9_S18) // command seq fifo (RAMB16_S9_S18)
......
control/dma_fifo353.v
View file @ d6e9be6b
...@@ -131,7 +131,7 @@ module dma_fifo_sync ( clk, // system clock, 120MHz? (currentle negedge used) ...@@ -131,7 +131,7 @@ module dma_fifo_sync ( clk, // system clock, 120MHz? (currentle negedge used)
burst_start_sync[1:0] <= {burst_start_sync[0],~first_four_r[2] & first_four_r[1]}; burst_start_sync[1:0] <= {burst_start_sync[0],~first_four_r[2] & first_four_r[1]};
first_four_r[2:0]={first_four_r[1:0],first_four}; first_four_r[2:0] <= {first_four_r[1:0],first_four};
empties[3:0] <= {4{!rst && (infifo[9:0]==10'h0) && !dreq && !dack_r[1]}} & {empties[2:0],1'b1}; empties[3:0] <= {4{!rst && (infifo[9:0]==10'h0) && !dreq && !dack_r[1]}} & {empties[2:0],1'b1};
......
control/i2c_writeonly.v
View file @ d6e9be6b
...@@ -201,8 +201,8 @@ module i2c_writeonly (sclk, // @negedge ...@@ -201,8 +201,8 @@ module i2c_writeonly (sclk, // @negedge
bytes_cmd <= wen_d[0] && is_ctl && di_1[11]; bytes_cmd <= wen_d[0] && is_ctl && di_1[11];
dly_cmd <= wen_d[0] && is_ctl && di_1[ 8]; dly_cmd <= wen_d[0] && is_ctl && di_1[ 8];
// setting control parameters // setting control parameters
if (bytes_cmd) i2c_bytes[1:0]=di_2[10:9]; if (bytes_cmd) i2c_bytes[1:0] <= di_2[10:9];
if (dly_cmd) i2c_dly[7:0] =di_2[ 7:0]; if (dly_cmd) i2c_dly[7:0] <= di_2[ 7:0];
if (reset_cmd || (run_cmd && !di_2[12])) i2c_enrun <= 1'b0; if (reset_cmd || (run_cmd && !di_2[12])) i2c_enrun <= 1'b0;
else if (run_cmd && di_2[12]) i2c_enrun <= 1'b1; else if (run_cmd && di_2[12]) i2c_enrun <= 1'b1;
// write pointer memory // write pointer memory
...@@ -220,7 +220,7 @@ module i2c_writeonly (sclk, // @negedge ...@@ -220,7 +220,7 @@ module i2c_writeonly (sclk, // @negedge
we_fifo_wp <= wen_d[1] || wpage0_inc; we_fifo_wp <= wen_d[1] || wpage0_inc;
if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0]; if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 7'h0:(fifo_wr_pointers_outw_r[5:0]+1); if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri
// command i2c fifo (RAMB16_S9_S18) // command i2c fifo (RAMB16_S9_S18)
......
control/interrupts_vector333.v
View file @ d6e9be6b
...@@ -55,7 +55,7 @@ module interrupts_vector(sclk, // @negedge ...@@ -55,7 +55,7 @@ module interrupts_vector(sclk, // @negedge
wire [15:0] irq_insa; wire [15:0] irq_insa;
reg [15:0] irq_insb; reg [15:0] irq_insb;
reg [15:0] irq_insc; //single cycle sync interrupt request. reg [15:0] irq_insc; //single cycle sync interrupt request.
wire [15:0] irq_rst; ///AF: wire [15:0] irq_rst;
reg rst_rqs, en_rqs, dis_rqs, pre_set_irqv, set_irqv; reg rst_rqs, en_rqs, dis_rqs, pre_set_irqv, set_irqv;
reg [ 3:0] irqv_a; // irq vectors table write address reg [ 3:0] irqv_a; // irq vectors table write address
reg [ 7:0] irqv_d; // irq vectors table write data reg [ 7:0] irqv_d; // irq vectors table write data
...@@ -190,7 +190,7 @@ module interrupts_vector(sclk, // @negedge ...@@ -190,7 +190,7 @@ module interrupts_vector(sclk, // @negedge
FD_1 i_irq_um_15 (.C(sclk), .D(~(rst_rq[15]) & (irq_insc[15] | irq_um[15])), .Q(irq_um[15])); FD_1 i_irq_um_15 (.C(sclk), .D(~(rst_rq[15]) & (irq_insc[15] | irq_um[15])), .Q(irq_um[15]));
myRAM16X8D_1 i_vecttab (.D(irqv_d[7:0]), .WE(set_irqv), .clk(sclk), .AW(irqv_a[3:0]), .AR(irqn_r[3:0]), .QR(irqv[7:0])); myRAM16X8D_1 i_vecttab (.D(irqv_d[7:0]), .WE(set_irqv), .clk(sclk), .AW(irqv_a[3:0]), .AR(irqn_r[3:0]), .QR(irqv[7:0]), .QW());
always @ (negedge sclk) begin always @ (negedge sclk) begin
if (pre_wen) did[15:0] <= di[15:0]; if (pre_wen) did[15:0] <= di[15:0];
...@@ -208,8 +208,8 @@ module interrupts_vector(sclk, // @negedge ...@@ -208,8 +208,8 @@ module interrupts_vector(sclk, // @negedge
set_irqv <= pre_set_irqv; set_irqv <= pre_set_irqv;
if (pre_set_irqv) irqv_a[3:0] <= did[11:8]; if (pre_set_irqv) irqv_a[3:0] <= did[11:8];
if (pre_set_irqv) irqv_d[7:0] <= did[ 7:0]; if (pre_set_irqv) irqv_d[7:0] <= did[ 7:0];
rst_rq[15:0] <= ({15{rst_rqs}} & did[15:0]) | rst_rq_inta[15:0]; rst_rq[15:0] <= ({16{rst_rqs}} & did[15:0]) | rst_rq_inta[15:0];
dis_rq[15:0] <= ({15{dis_rqs}} & did[15:0]); dis_rq[15:0] <= ({16{dis_rqs}} & did[15:0]);
// en_rq [15:0] <= ({15{ en_rqs}} & did[15:0]); // en_rq [15:0] <= ({15{ en_rqs}} & did[15:0]);
inta_s[5:0] <= {inta_s[4:0], inta}; inta_s[5:0] <= {inta_s[4:0], inta};
......
control/ioports353.v
View file @ d6e9be6b
...@@ -539,10 +539,15 @@ module dqs2 (c0,/*c90,*/c270, ...@@ -539,10 +539,15 @@ module dqs2 (c0,/*c90,*/c270,
input c0,/*c90,*/c270,t; input c0,/*c90,*/c270,t;
inout UDQS, LDQS; inout UDQS, LDQS;
output udqsr90,ldqsr90,udqsr270,ldqsr270; output udqsr90,ldqsr90,udqsr270,ldqsr270;
wire t0,t1,t2,tr; wire t0,t1,tr;
///AF: wire t2;
FD_1 #(.INIT(1'b1)) i_t0 (.C(c0),.D(t),.Q(t0)); FD_1 #(.INIT(1'b1)) i_t0 (.C(c0),.D(t),.Q(t0));
FD #(.INIT(1'b1)) i_t1 (.C(c0),.D(t0),.Q(t1)); FD #(.INIT(1'b1)) i_t1 (.C(c0),.D(t0),.Q(t1));
FD #(.INIT(1'b1)) i_t2 (.C(c270),.D(t0),.Q(t2)); ///AF: FD #(.INIT(1'b1)) i_t2 (.C(c270),.D(t0),.Q(t2));
assign tr= t1;
dqs2_0 i_dqsu(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({udqsr270,udqsr90}),.dq(UDQS));
dqs2_0 i_dqsl(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({ldqsr270,ldqsr90}),.dq(LDQS));
endmodule endmodule
module dqs2_0(c0,/*c90,*/c270,t,q,dq); module dqs2_0(c0,/*c90,*/c270,t,q,dq);
...@@ -563,7 +568,7 @@ module dqs2_0(c0,/*c90,*/c270,t,q,dq); ...@@ -563,7 +568,7 @@ module dqs2_0(c0,/*c90,*/c270,t,q,dq);
// as in IFDDRCPE.v // as in IFDDRCPE.v
FDCPE_1 #(.INIT(1'b1)) i_q0 (.C(c270), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0])); FDCPE_1 #(.INIT(1'b0)) i_q0 (.C(c270), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0]));
FDCPE i_q1 (.C(c270),.CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[1])); FDCPE i_q1 (.C(c270),.CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[1]));
// synthesis attribute IOB of i_q0 is "TRUE" // synthesis attribute IOB of i_q0 is "TRUE"
// synthesis attribute IOB of i_q1 is "TRUE" // synthesis attribute IOB of i_q1 is "TRUE"
...@@ -577,7 +582,7 @@ endmodule ...@@ -577,7 +582,7 @@ endmodule
module sddrdm(c0,/*c90,*/c270,d,dq); module sddrdm(c0,/*c90,*/c270,d,dq);
input c0,/*c90,*/c270; input c0,/*c90,*/c270;
input [1:0] d; input [1:0] d;
inout dq; inout dq; //SuppressThisWarning Veditor UNUSED
sddrdm0 i_dq (.c0(c0),/*.c90(c90),*/.c270(c270),.d(d),.dq(dq)); sddrdm0 i_dq (.c0(c0),/*.c90(c90),*/.c270(c270),.d(d),.dq(dq));
// s--ynthesis attribute KEEP_HIERARCHY of i_dq is "TRUE" // s--ynthesis attribute KEEP_HIERARCHY of i_dq is "TRUE"
endmodule endmodule
......
control/rtc353.v
View file @ d6e9be6b
...@@ -260,7 +260,7 @@ module timestamp353( mclk, // system clock (negedge) ...@@ -260,7 +260,7 @@ module timestamp353( mclk, // system clock (negedge)
else if (hacti && !hact_d) vact_pend <= 1'b0; else if (hacti && !hact_d) vact_pend <= 1'b0;
if (hacti && !hact_d) odd_line <= !vact_pend && !odd_line; if (hacti && !hact_d) odd_line <= !vact_pend && !odd_line;
// if (hacti && !hact_d) line[3:0] <= vact_pend?4'h1:{line[2:0],1'b0}; // if (hacti && !hact_d) line[3:0] <= vact_pend?4'h1:{line[2:0],1'b0};
if (hacti && !hact_d) line[2:0] <= vact_pend?4'h1:{line[1:0],1'b0}; if (hacti && !hact_d) line[2:0] <= vact_pend ? 3'h1 : {line[1:0],1'b0};
if (hacti && !hact_d) ts_line <= tsmode[1]? (vact_pend || line[0] ) : (!vact_pend && (line[1] || line[2])); if (hacti && !hact_d) ts_line <= tsmode[1]? (vact_pend || line[0] ) : (!vact_pend && (line[1] || line[2]));
...@@ -282,9 +282,9 @@ module timestamp353( mclk, // system clock (negedge) ...@@ -282,9 +282,9 @@ module timestamp353( mclk, // system clock (negedge)
// else ts_data[25:0]<= 16'h0; // else ts_data[25:0]<= 16'h0;
ts_active_r <= ts_active; ts_active_r <= ts_active;
ts_line_r <= ts_line; ts_line_r <= ts_line;
if (ts_active_r) ts_data[25:0]<= {ts_data[24:0],1'b0}; if (ts_active_r) ts_data[25:0] <= {ts_data[24:0],1'b0};
else if (ts_line_r) ts_data[25:0]<= odd_line?sec[31:6]:{sec[5:0],usec[19:0]}; else if (ts_line_r) ts_data[25:0] <= odd_line?sec[31:6]:{sec[5:0],usec[19:0]};
else ts_data[25:0]<= 16'h0; else ts_data[25:0] <= 26'h0;
end end
endmodule endmodule
......
extras/10364.v
View file @ d6e9be6b
...@@ -135,7 +135,7 @@ FDCE_1 i_enable_mot_clk (.C(clk),.CE(we_ctl && di_d[1]),.CLR(1'b0), ...@@ -135,7 +135,7 @@ FDCE_1 i_enable_mot_clk (.C(clk),.CE(we_ctl && di_d[1]),.CLR(1'b0),
// reset at simulation // reset at simulation
assign sequence_next[1:0]=sequence[1:0]+1; assign sequence_next[1:0]=sequence[1:0]+1;
assign sequence_next[3:2]=(sequence[1:0]==3'b11)?((sequence[3:2]==3'b11)?2'b01:(sequence[3:2]+1)):sequence[3:2]; assign sequence_next[3:2]=(sequence[1:0]==2'b11)?((sequence[3:2]==2'b11)?2'b01:(sequence[3:2]+1)):sequence[3:2];
FD i_sequence_0(.C(xclk),.D(sequence_next[0]), .Q(sequence[0])); FD i_sequence_0(.C(xclk),.D(sequence_next[0]), .Q(sequence[0]));
FD i_sequence_1(.C(xclk),.D(sequence_next[1]), .Q(sequence[1])); FD i_sequence_1(.C(xclk),.D(sequence_next[1]), .Q(sequence[1]));
FD i_sequence_2(.C(xclk),.D(sequence_next[2]), .Q(sequence[2])); FD i_sequence_2(.C(xclk),.D(sequence_next[2]), .Q(sequence[2]));
...@@ -342,6 +342,9 @@ endmodule ...@@ -342,6 +342,9 @@ endmodule
/// Combine old (freom register file) /new encoded periods, inc/dec pulses to prepare a 6-bit (partial) index for a RAM table. /// Combine old (freom register file) /new encoded periods, inc/dec pulses to prepare a 6-bit (partial) index for a RAM table.
/// Together with the position error (another 6 bits) the full 12-bit undex provides 1 4-bit PWM code from the RAM table /// Together with the position error (another 6 bits) the full 12-bit undex provides 1 4-bit PWM code from the RAM table
/// Updates direction immediately, period - if inc_dec or when new period > saved period (so it will be updated even if the motor is stopped) /// Updates direction immediately, period - if inc_dec or when new period > saved period (so it will be updated even if the motor is stopped)
/// AF2015: Replace eith a function?
module calc_speed (clk, // posedge, 80 MHz module calc_speed (clk, // posedge, 80 MHz
en_in, // enable (just for simulation), for real - let it on even when motors are off en_in, // enable (just for simulation), for real - let it on even when motors are off
process, // increment (with limit) period process, // increment (with limit) period
...@@ -355,11 +358,11 @@ module calc_speed (clk, // posedge, 80 MHz ...@@ -355,11 +358,11 @@ module calc_speed (clk, // posedge, 80 MHz
enc_period_this // [4:0] encoded period for the register file/ table index enc_period_this // [4:0] encoded period for the register file/ table index
); );
parameter IGNORE_EN=1; parameter IGNORE_EN=1;
input clk; // posedge, 80MHz input clk; // posedge, 80MHz // SuppressThisWarning Veditor UNUSED
input en_in; // enable, 0 resets period counter - simulation only input en_in; // enable, 0 resets period counter - simulation only
input process; // increment (with limit) period input process; // increment (with limit) period // SuppressThisWarning Veditor UNUSED
input inc_dec; // encoder pulse detected input inc_dec; // encoder pulse detected
input inc; // encoder position increment input inc; // encoder position increment // SuppressThisWarning Veditor UNUSED
input dec; // encoder position decrement input dec; // encoder position decrement
input [4:0] enc_period_curr; // encoded current period (still running if !inc_dec) input [4:0] enc_period_curr; // encoded current period (still running if !inc_dec)
input dir_last; // last stored direction (from register file) input dir_last; // last stored direction (from register file)
...@@ -560,14 +563,14 @@ module motor_pwm( clk, // posedge, 80MHz ...@@ -560,14 +563,14 @@ module motor_pwm( clk, // posedge, 80MHz
output [2:0] new_pwm; // [2:0] output [2:0] new_pwm; // [2:0]
output [1:0] mot; // [1:0] - data to be copied to the motor outputs output [1:0] mot; // [1:0] - data to be copied to the motor outputs
reg [9:0] pwm_cycle_count; reg [9:0] pwm_cycle_count; /// AF2015: Seems to be a bug - 2 MSBs are never used (only 8 LSB)
reg pwm_cycle_next; reg pwm_cycle_next;
reg [3:0] pwm_delay_count; reg [3:0] pwm_delay_count; /// AF2015: Seems to be a bug - 1 MSB is never used (only 3 LSB)
reg pwm_delay_end; reg pwm_delay_end;
reg [2:0] pwm_phase; reg [2:0] pwm_phase;
wire [2:0] spreaded_phase; wire [2:0] spreaded_phase;
wire pwn_on; wire pwn_on; // SuppressThisWarning Veditor UNUSED
wire pwn_off; wire pwn_off; // SuppressThisWarning Veditor UNUSED
wire [2:0] new_pwm; wire [2:0] new_pwm;
wire stop_cmd; wire stop_cmd;
wire [3:0] pwm_diff; wire [3:0] pwm_diff;
...@@ -575,7 +578,7 @@ module motor_pwm( clk, // posedge, 80MHz ...@@ -575,7 +578,7 @@ module motor_pwm( clk, // posedge, 80MHz
assign spreaded_phase[2:0]= pwm_phase[2:0]+spread[2:0]; assign spreaded_phase[2:0]= pwm_phase[2:0]+spread[2:0];
assign pwn_on= pwm_cycle_next && (spreaded_phase == 0) && (pwm_code != 0); assign pwn_on= pwm_cycle_next && (spreaded_phase == 0) && (pwm_code != 0);
assign pwn_off=pwm_cycle_next && (spreaded_phase == pwm_code); assign pwn_off=pwm_cycle_next && (spreaded_phase == pwm_code[2:0]);
assign stop_cmd= !en || (pwm_code==8) ; assign stop_cmd= !en || (pwm_code==8) ;
assign pwm_diff[3:0]={1'b0,pwm_code[2:0]}-{1'b0,spreaded_phase[2:0]}; assign pwm_diff[3:0]={1'b0,pwm_code[2:0]}-{1'b0,spreaded_phase[2:0]};
...@@ -584,10 +587,14 @@ module motor_pwm( clk, // posedge, 80MHz ...@@ -584,10 +587,14 @@ module motor_pwm( clk, // posedge, 80MHz
assign new_pwm[2]=!en || (pwm_cycle_next? (new_pwm[1:0]!=cur_pwm[1:0]):(cur_pwm[2]&& !pwm_delay_end)); assign new_pwm[2]=!en || (pwm_cycle_next? (new_pwm[1:0]!=cur_pwm[1:0]):(cur_pwm[2]&& !pwm_delay_end));
assign mot[1:0]=(stop_cmd || new_pwm[2])? 2'b0:(new_pwm[1]?{new_pwm[0],!new_pwm[0]}:2'b11); assign mot[1:0]=(stop_cmd || new_pwm[2])? 2'b0:(new_pwm[1]?{new_pwm[0],!new_pwm[0]}:2'b11);
always @ (posedge clk) if (pre_first) begin // change these registers once per cycle of all motors always @ (posedge clk) if (pre_first) begin // change these registers once per cycle of all motors
pwm_cycle_count<= (!en || (pwm_cycle_count==0))?pwm_cycle:(pwm_cycle_count-1);
/// AF2015: pwm_cycle_count<= (!en || (pwm_cycle_count==0)) ? pwm_cycle:(pwm_cycle_count-1);
pwm_cycle_count<= (!en || (pwm_cycle_count==0)) ? {2'b0,pwm_cycle}:(pwm_cycle_count-1);
pwm_cycle_next<= en && (pwm_cycle_count==0); pwm_cycle_next<= en && (pwm_cycle_count==0);
// pwm_delay_count<= (!en || (pwm_delay_count==0))?0:(pwm_cycle_next?pwm_delay: (pwm_delay_count-1));
pwm_delay_count<= (!en || pwm_cycle_next)?pwm_delay:((pwm_delay_count==0)?0: (pwm_delay_count-1)); /// AF2015: pwm_delay_count<= (!en || pwm_cycle_next)?pwm_delay:((pwm_delay_count==0)?0: (pwm_delay_count-1));
pwm_delay_count<= (!en || pwm_cycle_next)?{1'b0,pwm_delay}:((pwm_delay_count==0)? 4'b0: (pwm_delay_count-1));
pwm_delay_end<= en && (pwm_delay_count==1); pwm_delay_end<= en && (pwm_delay_count==1);
pwm_phase<= (!en)? 0: (pwm_phase + pwm_cycle_next); // divide by 8 pwm_phase<= (!en)? 0: (pwm_phase + pwm_cycle_next); // divide by 8
end end
......
extras/imu_logger.v
View file @ d6e9be6b
...@@ -311,7 +311,7 @@ imu_timestamps i_imu_timestamps ( ...@@ -311,7 +311,7 @@ imu_timestamps i_imu_timestamps (
.ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored .ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
.ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high .ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
.dout(timestamps_rdata[15:0]));// output data .dout(timestamps_rdata[15:0]));// output data
wire [0:0] debug_state_unused; wire [0:0] debug_state_unused; // SuppressThisWarning Veditor UNUSED
rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal) rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles .bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles
.ser_di(ser_di), // rs232 (ttl) serial data in .ser_di(ser_di), // rs232 (ttl) serial data in
...@@ -415,7 +415,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge ...@@ -415,7 +415,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge
reg [3:1] chn1hot; // channels 1-hot - granted and ready, priority applied reg [3:1] chn1hot; // channels 1-hot - granted and ready, priority applied
reg rq_not_zero; // at least one channel is ready for processing (same time as chn1hot[3:0]) reg rq_not_zero; // at least one channel is ready for processing (same time as chn1hot[3:0])
reg [1:0] channel; reg [1:0] channel;
reg start; ///AF: reg start;
reg busy; reg busy;
wire wstart; wire wstart;
reg ts_en; reg ts_en;
...@@ -462,7 +462,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge ...@@ -462,7 +462,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge
channels_ready[2] & ~|channels_ready[1:0], channels_ready[2] & ~|channels_ready[1:0],
channels_ready[1] & ~channels_ready[0]}; channels_ready[1] & ~channels_ready[0]};
start <= wstart; ///AF: start <= wstart;
if ((seq_cntr[4:0]=='h1e) || rst) busy <= 1'b0; if ((seq_cntr[4:0]=='h1e) || rst) busy <= 1'b0;
else if (rq_not_zero) busy <= 1'b1; else if (rq_not_zero) busy <= 1'b1;
...@@ -765,10 +765,12 @@ module imu_spi ( sclk, // system clock, negedge ...@@ -765,10 +765,12 @@ module imu_spi ( sclk, // system clock, negedge
stall_dur[7:0] <= stall_dur_mclk[7:0]; stall_dur[7:0] <= stall_dur_mclk[7:0];
bit_duration_zero <= (bit_duration[7:0]==8'h0); bit_duration_zero <= (bit_duration[7:0]==8'h0);
clk_div[1:0]=en?(clk_div[1:0]+1):2'b0; clk_div[1:0] <= en?(clk_div[1:0]+1):2'b0;
clk_en[3:0] <= {clk_en[2:0],clk_div[1:0]==2'h3}; clk_en[3:0] <= {clk_en[2:0],clk_div[1:0]==2'h3};
if (bit_duration_zero || (bit_duration_cntr[7:0]==8'h0)) bit_duration_cntr[7:0]<=bit_duration[7:0]; if (bit_duration_zero || (bit_duration_cntr[7:0]==8'h0)) bit_duration_cntr[7:0]<=bit_duration[7:0];
else bit_duration_cntr[7:0] <= bit_duration_cntr[7:0]-1; else bit_duration_cntr[7:0] <= bit_duration_cntr[7:0]-1;
clk_en[3:0] <= {clk_en[2:0],bit_duration_cntr[7:0]==8'h3}; // change 9'h3 to enforce frequency limit clk_en[3:0] <= {clk_en[2:0],bit_duration_cntr[7:0]==8'h3}; // change 9'h3 to enforce frequency limit
end end
...@@ -795,7 +797,7 @@ module imu_spi ( sclk, // system clock, negedge ...@@ -795,7 +797,7 @@ module imu_spi ( sclk, // system clock, negedge
else if (end_spi) seq_counter[9:0] <= 10'h001; else if (end_spi) seq_counter[9:0] <= 10'h001;
else if (clk_en[3] && (seq_state[1:0]!=2'h0) && !stall) seq_counter[9:0] <= seq_counter[9:0] - 1; else if (clk_en[3] && (seq_state[1:0]!=2'h0) && !stall) seq_counter[9:0] <= seq_counter[9:0] - 1;
set_mosi_prepare <= clk_en[2] && first_prepare; set_mosi_prepare <= clk_en[2] && first_prepare;
set_mosi_spi <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && (seq_counter[9:5]!=6'h0) && !stall; // last word use zero set_mosi_spi <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && (seq_counter[9:5] != 5'h0) && !stall; // last word use zero
// no stall before the first word // no stall before the first word
if (!en) skip_stall <= 1'b0; if (!en) skip_stall <= 1'b0;
...@@ -1109,7 +1111,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal) ...@@ -1109,7 +1111,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal)
reg wait_just_pause; reg wait_just_pause;
wire wstart; wire wstart;
wire [4:0] debug; wire [4:0] debug;
reg [4:0] debug0; // {was_ts_stb, was_start, was_error, was_ser_di_1, was_ser_di_0} - once after reset reg [4:0] debug0; // {was_ts_stb, was_start, was_error, was_ser_di_1, was_ser_di_0} - once after reset // SuppressThisWarning Veditor UNUSED
assign reset_wait_pause= (restart[1] && !restart[0]) || (wait_pause && !wait_start && !ser_di); assign reset_wait_pause= (restart[1] && !restart[0]) || (wait_pause && !wait_start && !ser_di);
assign error=!ser_filt_di && last_half_bit && bit_half_end && receiving_byte; assign error=!ser_filt_di && last_half_bit && bit_half_end && receiving_byte;
assign sample_bit=shift_en && bit_half_end && !bit_cntr[0]; assign sample_bit=shift_en && bit_half_end && !bit_cntr[0];
...@@ -1161,7 +1163,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal) ...@@ -1161,7 +1163,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal)
if (ser_rst) debug0[4:0] <=5'b0; if (ser_rst) debug0[4:0] <=5'b0;
else debug0[4:0] <= debug | {ts_stb,start,error,ser_di_d,~ser_di_d}; else debug0[4:0] <= debug | {ts_stb,start,error,ser_di_d[0],~ser_di_d[0]};
end end
endmodule endmodule
...@@ -1571,7 +1573,7 @@ module imu_timestamps ( ...@@ -1571,7 +1573,7 @@ module imu_timestamps (
rq_sclk2[1] & ~rq_sclk2[0], rq_sclk2[1] & ~rq_sclk2[0],
rq_sclk2[0]}; rq_sclk2[0]};
pri_sclk_d[3:0] <= pri_sclk[3:0]; pri_sclk_d[3:0] <= pri_sclk[3:0];
proc[9:0] <= {proc[9:0], wstart}; proc[9:0] <= {proc[8:0], wstart};
if (proc[0]) wa[3:2] <= {|pri_sclk_d[3:2], pri_sclk_d[3] | pri_sclk_d[1]}; if (proc[0]) wa[3:2] <= {|pri_sclk_d[3:2], pri_sclk_d[3] | pri_sclk_d[1]};
if (proc[0]) sec_latched[31:0] <= sec[31:0]; if (proc[0]) sec_latched[31:0] <= sec[31:0];
if (proc[0]) usec_latched[19:0] <= usec[19:0]; if (proc[0]) usec_latched[19:0] <= usec[19:0];
......
extras/motors_tb.v
View file @ d6e9be6b
...@@ -7,17 +7,15 @@ module testbench(); ...@@ -7,17 +7,15 @@ module testbench();
parameter CLK2WA= 1; parameter CLK2WA= 1;
parameter WA2WD= 1; parameter WA2WD= 1;
parameter aaaa=0; ///AF: parameter aaaa=0;
parameter aaaa=1; ///AF: parameter aaaa=1;
reg sclk,xclk; reg sclk,xclk;
reg [15:0] wd; reg [15:0] wd;
reg wa; reg wa;
reg we; reg we;
wire [15:0] rd; wire [31:0] rd; // SuppressThisWarning Veditor UNUSED
// reg [1:0] encod1;
// reg [1:0] encod2;
// reg [1:0] encod3;
wire [1:0] encod1; wire [1:0] encod1;
wire [1:0] encod2; wire [1:0] encod2;
wire [1:0] encod3; wire [1:0] encod3;
...@@ -71,7 +69,7 @@ motor i_motor3 (.clk(xclk), ...@@ -71,7 +69,7 @@ motor i_motor3 (.clk(xclk),
initial begin initial begin
$dumpfile("motors.lxt"); $dumpfile("motors.lxt");
$dumpvars(0,testbench.i_three_motor_driver); $dumpvars(0,testbench.i_three_motor_driver); // SuppressThisWarning Veditor VDT_BUG
/* /*
$dumpvars(0,testbench.i_three_motor_driver.addr); $dumpvars(0,testbench.i_three_motor_driver.addr);
$dumpvars(0,testbench.i_three_motor_driver.reg_addr); $dumpvars(0,testbench.i_three_motor_driver.reg_addr);
...@@ -95,7 +93,7 @@ motor i_motor3 (.clk(xclk), ...@@ -95,7 +93,7 @@ motor i_motor3 (.clk(xclk),
$dumpvars(0,testbench.i_three_motor_driver.i_motor_pwm); $dumpvars(0,testbench.i_three_motor_driver.i_motor_pwm);
*/ */
$dumpvars(0,testbench.rd); $dumpvars(0,testbench.rd);
$dumpvars(0,testbench.i_motor1); $dumpvars(0,testbench.i_motor1); // SuppressThisWarning Veditor VDT_BUG - it is resolved
$dumpvars(0,testbench.i_motor2.position); $dumpvars(0,testbench.i_motor2.position);
$dumpvars(0,testbench.i_motor2.speed); $dumpvars(0,testbench.i_motor2.speed);
$dumpvars(0,testbench.i_motor3.position); $dumpvars(0,testbench.i_motor3.position);
...@@ -194,7 +192,7 @@ $finish; ...@@ -194,7 +192,7 @@ $finish;
task program_table; task program_table;
reg [31:0] data[0:511]; reg [31:0] data[0:511]; // SuppressThisWarning Veditor VDT_BUG - assigned in system task
integer i; integer i;
begin begin
$readmemh("motor.dat",data); $readmemh("motor.dat",data);
...@@ -216,12 +214,12 @@ module motor (clk, ...@@ -216,12 +214,12 @@ module motor (clk,
enc); enc);
parameter SAMPLE_PERIOD=100; // ns parameter SAMPLE_PERIOD=100; // ns
parameter VMAX=1000.0; /// pulses/sec parameter VMAX=1000.0; /// pulses/sec
parameter EMF= 0.5; /// part of the voltage that is caused by rotation (remaining goes to current -> force->acceleration). Not yet used parameter EMF= 0.5; /// part of the voltage that is caused by rotation (remaining goes to current -> force->acceleration). Not yet used // SuppressThisWarning Veditor UNUSED
// parameter ACCEL=10.0; /// number of VMAX/sec if full power is applied, speed==0 // parameter ACCEL=10.0; /// number of VMAX/sec if full power is applied, speed==0
parameter ACCEL=300.0; /// number of VMAX/sec if full power is applied, speed==0 parameter ACCEL=300.0; /// number of VMAX/sec if full power is applied, speed==0
// no simulation of friction yet // no simulation of friction yet
input clk; input clk; // SuppressThisWarning Veditor UNUSED
input en; input en; // SuppressThisWarning Veditor UNUSED
input [1:0] pwr; input [1:0] pwr;
output [1:0] enc; output [1:0] enc;
...@@ -229,8 +227,8 @@ module motor (clk, ...@@ -229,8 +227,8 @@ module motor (clk,
real position, position0; real position, position0;
real speed, speed0; real speed, speed0;
// time t,t0; // time t,t0;
integer itime; ///AF: integer itime;
real rtime; ///AF: real rtime;
reg [1:0] enc; reg [1:0] enc;
reg [1:0] enc_bin; reg [1:0] enc_bin;
real t,t0, dt, e,f; real t,t0, dt, e,f;
...@@ -249,10 +247,10 @@ module motor (clk, ...@@ -249,10 +247,10 @@ module motor (clk,
t=$time; t=$time;
dt=(t-t0)/1000000000; // in seconds dt=(t-t0)/1000000000; // in seconds
case (pwr) case (pwr)
0: f<=(speed>0)?-1.0:1.0; 0: f = (speed>0)?-1.0:1.0;
1: f<=1.0; 1: f = 1.0;
2: f<=-1.0; 2: f = -1.0;
3: f<=0.0; 3: f = 0.0;
endcase endcase
e=f-speed/VMAX; e=f-speed/VMAX;
speed=speed0+ACCEL*VMAX*e*dt; speed=speed0+ACCEL*VMAX*e*dt;
...@@ -261,7 +259,7 @@ module motor (clk, ...@@ -261,7 +259,7 @@ module motor (clk,
#1; #1;
// itime=sim_time; // itime=sim_time;
// rtime=sim_time; // rtime=sim_time;
enc[1:0] <= {enc_bin[1],enc_bin[1] ^ enc_bin[0]}; enc[1:0] = {enc_bin[1],enc_bin[1] ^ enc_bin[0]};
t0=t; t0=t;
speed0=speed; speed0=speed;
position0=position; position0=position;
......
general/macros353.v
View file @ d6e9be6b
...@@ -31,7 +31,11 @@ module MSRL16 (Q, A, CLK, D); ...@@ -31,7 +31,11 @@ module MSRL16 (Q, A, CLK, D);
output Q; output Q;
input [3:0] A; input [3:0] A;
input CLK, D; input CLK, D;
SRL16 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D)); `ifdef SIMULATION
SRL16_MOD #(.INVERT(1'b0)) i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`else
SRL16 i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`endif
endmodule endmodule
...@@ -39,7 +43,11 @@ module MSRL16_1 (Q, A, CLK, D); ...@@ -39,7 +43,11 @@ module MSRL16_1 (Q, A, CLK, D);
output Q; output Q;
input [3:0] A; input [3:0] A;
input CLK, D; input CLK, D;
SRL16_1 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D)); `ifdef SIMULATION
SRL16_MOD #(.INVERT(1'b1)) i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`else
SRL16_1 i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`endif
endmodule endmodule
module myRAM_WxD_D(D,WE,clk,AW,AR,QW,QR); module myRAM_WxD_D(D,WE,clk,AW,AR,QW,QR);
...@@ -73,3 +81,43 @@ parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1; ...@@ -73,3 +81,43 @@ parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
assign QW= ram[AW]; assign QW= ram[AW];
assign QR= ram[AR]; assign QR= ram[AR];
endmodule endmodule
// Fixing Xilinx SLR16_x
module SRL16_MOD #(
parameter INIT = 16'h0000,
parameter INVERT = 0 // *_1 - invert
) (
output Q,
input A0,
input A1,
input A2,
input A3,
input CLK,
input D);
reg [15:0] data;
wire clk_;
wire [3:0] a = {A3, A2, A1, A0};
assign Q = (data == 16'h0) ? 1'b0 :
((data == 16'hffff) ? 1'b1 : data[a]);
assign clk_ = INVERT? (~CLK) : CLK;
initial
begin
assign data = INIT;
while (clk_ === 1'b1 || clk_ === 1'bX)
#10;
deassign data;
end
always @(posedge clk_)
begin
{data[15:0]} <= #100 {data[14:0], D};
end
endmodule
imu_sim2_include.vh 0 → 100644
View file @ d6e9be6b
/*******************************************************************************
* Include file: imu_sim2_include.vh
* Date:2015-07-26
* Author: Andrey Filippov
* Description: Moved here all simulation for IMU logger
*
* Copyright (c) 2015 Elphel, Inc .
* imu_sim2_include.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* imu_sim_include2.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`ifdef TEST_IMU
cpu_wr(X313_WA_IOPINS, X313_WA_IOPINS_EN_IMU_OUT); // 'hc0000000;
/*
reg we_config_imu; // bits 1:0, 2 - enable slot[1:0]
reg we_config_gps; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_rst; // bit 16, 17 - enable - reset modules
*/
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
// cpu_wr(X313_WA_IMU_DATA, 'h3e695); // configure channels and reset // gps timestamp from 1sec input, positive
// cpu_wr(X313_WA_IMU_DATA, 'h3e6b5); // configure channels and reset // gps timestamp from 1sec input, negative
// cpu_wr(X313_WA_IMU_DATA, 'h3e6d5); // configure channels and reset // gps timestamp after pause
// cpu_wr(X313_WA_IMU_DATA, 'h3e6f5); // configure channels and reset // gps timestamp at "$" start
cpu_wr(X313_WA_IMU_DATA, 'h43e6f5); // configure channels and reset // gps timestamp at "$" start, reset configure_debug
cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration)
cpu_wr(X313_WA_IMU_DATA, 'h8007); // reset rs232 by 1 in MSB
cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration)
cpu_wr(X313_WA_IMU_DATA, 'h0007); // serial speed 8 cycles (period = 32 CLK0 cycles)
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h20000); // remove reset
// encode 4 sentences
/*
$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
*/
cpu_wr(X313_WA_IMU_CTRL, 'h20); // format write
// just ($GP)RMC, GGA, GSA and VTG
cpu_wr(X313_WA_IMU_DATA, 'h6); //
cpu_wr(X313_WA_IMU_DATA, 'hf); //
cpu_wr(X313_WA_IMU_DATA, 'he); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h9); //
cpu_wr(X313_WA_IMU_DATA, 'h7); //
cpu_wr(X313_WA_IMU_DATA, 'h6); //
cpu_wr(X313_WA_IMU_DATA, 'hb); //
cpu_wr(X313_WA_IMU_DATA, 'h1); //
cpu_wr(X313_WA_IMU_DATA, 'hc); //
cpu_wr(X313_WA_IMU_DATA, 'hf); //
cpu_wr(X313_WA_IMU_DATA, 'h9); //
cpu_wr(X313_WA_IMU_DATA, 'h8); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h30); // first format
//$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
//0101010 000 : 'hb 'h2a 'h04 'h0
// cpu_wr(X313_WA_IMU_DATA, 'h0b); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h0a); // testing - made 1 shorter than actual
cpu_wr(X313_WA_IMU_DATA, 'h2a); //
cpu_wr(X313_WA_IMU_DATA, 'h04); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h34); // second format
//$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
//0010 1000 0101 0 : 'h0e 'h14 'h0a 'h0
cpu_wr(X313_WA_IMU_DATA, 'h0e); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h14); //
cpu_wr(X313_WA_IMU_DATA, 'h0a); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h38); // third format
//$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
//01000000 00000000 00 : 'h11 'h01 'h00 'h0
cpu_wr(X313_WA_IMU_DATA, 'h11); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h01); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h3c); // fourth format
//$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
//00101010 1 : 'h08 'haa 'h00 'h0
cpu_wr(X313_WA_IMU_DATA, 'h08); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'haa); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_CTRL, 4); // select register number 4
cpu_wr(X313_WA_IMU_DATA, 'h10); // x gyro low
cpu_wr(X313_WA_IMU_DATA, 'h12); // x gyro high
cpu_wr(X313_WA_IMU_DATA, 'h14); //
cpu_wr(X313_WA_IMU_DATA, 'h16); //
cpu_wr(X313_WA_IMU_DATA, 'h18); //
cpu_wr(X313_WA_IMU_DATA, 'h1a); //
cpu_wr(X313_WA_IMU_DATA, 'h1c); // x accel low
cpu_wr(X313_WA_IMU_DATA, 'h1e); //
cpu_wr(X313_WA_IMU_DATA, 'h20); //
cpu_wr(X313_WA_IMU_DATA, 'h22); //
cpu_wr(X313_WA_IMU_DATA, 'h24); //
cpu_wr(X313_WA_IMU_DATA, 'h26); // z accel high
cpu_wr(X313_WA_IMU_DATA, 'h40); // x delta ang low
cpu_wr(X313_WA_IMU_DATA, 'h42); // x delta ang high
cpu_wr(X313_WA_IMU_DATA, 'h44); //
cpu_wr(X313_WA_IMU_DATA, 'h46); //
cpu_wr(X313_WA_IMU_DATA, 'h48); //
cpu_wr(X313_WA_IMU_DATA, 'h4a); //
cpu_wr(X313_WA_IMU_DATA, 'h4c); // x delta vel low
cpu_wr(X313_WA_IMU_DATA, 'h4e); //
cpu_wr(X313_WA_IMU_DATA, 'h50); //
cpu_wr(X313_WA_IMU_DATA, 'h52); //
cpu_wr(X313_WA_IMU_DATA, 'h54); //
cpu_wr(X313_WA_IMU_DATA, 'h56); // z delta vel high
cpu_wr(X313_WA_IMU_DATA, 'h0e); // temperature
cpu_wr(X313_WA_IMU_DATA, 'h70); // time m/s
cpu_wr(X313_WA_IMU_DATA, 'h72); // time d/h
cpu_wr(X313_WA_IMU_DATA, 'h74); // time y/m
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, 0); // reset IMU
cpu_wr(X313_WA_IMU_DATA, 0); // reset bit counter
#1000;
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION); // set bit counter (clock frequency divider)
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_PERIOD); // set period
// set "odometer" message
cpu_wr(X313_WA_IMU_CTRL, 'h40); // select start of message
cpu_wr(X313_WA_IMU_DATA, 'h01234567); // Message first 4 bytes
cpu_wr(X313_WA_IMU_DATA, 'h12345678); //next
cpu_wr(X313_WA_IMU_DATA, 'h23456789); //next
cpu_wr(X313_WA_IMU_DATA, 'h3456789a); //next
cpu_wr(X313_WA_IMU_DATA, 'h456789ab); //next
cpu_wr(X313_WA_IMU_DATA, 'h56789abc); //next
cpu_wr(X313_WA_IMU_DATA, 'h6789abcd); //next
cpu_wr(X313_WA_IMU_DATA, 'h789abcde); //next
cpu_wr(X313_WA_IMU_DATA, 'h89abcdef); //next
cpu_wr(X313_WA_IMU_DATA, 'h9abcdef0); //next
cpu_wr(X313_WA_IMU_DATA, 'habcdef01); //next
cpu_wr(X313_WA_IMU_DATA, 'hbcdef012); //next
cpu_wr(X313_WA_IMU_DATA, 'hcdef0123); //next
cpu_wr(X313_WA_IMU_DATA, 'hdef01234); //next
// extra 8 bytes - will not be logged
cpu_wr(X313_WA_IMU_DATA, 'hef012345); //next
cpu_wr(X313_WA_IMU_DATA, 'hf0123456); //next
// cpu_wr(1,32'h00000); // disable and reset dma
// cpu_wr(1,32'h20000); // enable DMA channel 1
cpu_wr(1,32'h00024); // disable and reset dma (both channels)
cpu_wr(1,32'h00028); // enable DMA channel 1
// cpu_wr(X313_WA_IMU_DATA, 1); // set period
/*
parameter X313_WA_IMU_DATA= 'h7e;
parameter X313_WA_IMU_CTRL= 'h7f;
parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready
*/
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
`endif
\ No newline at end of file
imu_sim_include.vh 0 → 100644
View file @ d6e9be6b
This diff is collapsed.
imu_sim_init_include.vh 0 → 100644
View file @ d6e9be6b
/*******************************************************************************
* Include file: imu_sim_init_include.vh
* Date:2015-07-26
* Author: Andrey Filippov
* Description: Moved here all simulation for IMU logger
*
* Copyright (c) 2015 Elphel, Inc .
* imu_sim_init_include.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* imu_sim_init_include.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`ifdef TEST_IMU
//wire [11:0] EXT; // bidirectional
wire IMU_SCL=EXT[0];
wire IMU_SDA=EXT[1];
wire IMU_MOSI=EXT[2];
wire IMU_MISO=EXT[3]; //SuppressThisWarning Veditor UNUSED
reg IMU_EN;
wire IMU_ACTIVE;
wire IMU_NMOSI=!IMU_MOSI;
wire [5:1] IMU_TAPS;
reg IMU_LATE_ACKN;
reg IMU_SCLK;
reg IMU_MOSI_REVA;
reg IMU_103695REVA;
wire IMU_MOSI_OUT;
wire IMU_SCLK_OUT;
assign IMU_MOSI_OUT=IMU_103695REVA?IMU_MOSI_REVA:IMU_MOSI;
assign IMU_SCLK_OUT=IMU_103695REVA?(IMU_SCLK):IMU_SCL;
always @ (posedge IMU_SDA) begin
IMU_EN<=IMU_MOSI;
end
wire IMU_CS=IMU_103695REVA?!IMU_ACTIVE:!(IMU_EN &&IMU_SDA);
reg IMU_MOSI_D;
always @ (posedge IMU_SCLK_OUT) begin
// IMU_MOSI_D<=IMU_MOSI;
IMU_MOSI_D<=IMU_MOSI_OUT;
end
reg [15:0] IMU_LOOPBACK;
always @ (negedge IMU_SCLK_OUT) begin
if (!IMU_CS) IMU_LOOPBACK[15:0]<={IMU_LOOPBACK[14:0],IMU_MOSI_D};
end
assign EXT[3]=IMU_CS?IMU_DATA_READY:IMU_LOOPBACK[15];
PULLUP i_IMU_SDA (.O(IMU_SDA));
PULLUP i_IMU_SCL (.O(IMU_SCL));
initial begin
SERIAL_DATA_FD=$fopen("gps_data.dat","r");
end
always begin
#(IMU_READY_PERIOD-IMU_NREADY_DURATION) IMU_DATA_READY=1'b0;
#(IMU_NREADY_DURATION) IMU_DATA_READY=1'b1;
end
assign EXT[4]=SERIAL_BIT;
assign EXT[5]=GPS1SEC;
assign EXT[6]=ODOMETER_PULSE;
oneshot i_oneshot (.trigger(IMU_NMOSI),
.out(IMU_ACTIVE));
dly5taps i_dly5taps (.dly_in(IMU_NMOSI),
.dly_out(IMU_TAPS[5:1]));
always @ (negedge IMU_ACTIVE or posedge IMU_TAPS[5]) if (!IMU_ACTIVE) IMU_LATE_ACKN<= 1'b0; else IMU_LATE_ACKN<= 1'b1;
always @ (negedge IMU_LATE_ACKN or posedge IMU_TAPS[4]) if (!IMU_LATE_ACKN) IMU_SCLK<= 1'b1; else IMU_SCLK<= ~IMU_SCLK;
always @ (negedge IMU_SCLK) IMU_MOSI_REVA<= IMU_NMOSI;
`endif
\ No newline at end of file
imu_sim_tasks_include.vh 0 → 100644
View file @ d6e9be6b
/*******************************************************************************
* Include file: imu_sim_tasks_include.vh
* Date:2015-07-26
* Author: Andrey Filippov
* Description: Moved here all simulation tasks for IMU logger
*
* Copyright (c) 2015 Elphel, Inc .
* imu_sim_tasks_include.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* imu_sim_tasks_include.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`ifdef TEST_IMU
task send_serial_bit;
input [7:0] data_byte;
reg [7:0] d;
begin
d <= data_byte;
wait (CLK0); wait (~CLK0);
// SERIAL_BIT should be 1 here
// Send start bit
SERIAL_BIT <= 1'b0;
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
// Send 8 data bits, LSB first
repeat (8) begin
SERIAL_BIT <= d[0];
#1 d[7:0] <= {1'b0,d[7:1]};
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end
// Send stop bit
SERIAL_BIT <= 1'b1;
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end
endtask
task send_serial_pause;
begin
wait (CLK0); wait (~CLK0);
SERIAL_BIT <= 1'b1;
repeat (16) begin
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end
end
endtask
// SERIAL_DATA_FD=$fopen("gps_data.dat","r");
task send_serial_line;
integer char;
begin
char=0;
while (!$feof (SERIAL_DATA_FD) && (char != 'h0a)) begin
char=$fgetc(SERIAL_DATA_FD);
send_serial_bit(char);
end
end
endtask
`endif
\ No newline at end of file
memctrl353/descrproc353.v
View file @ d6e9be6b
...@@ -455,11 +455,13 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2)) ...@@ -455,11 +455,13 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
wire [4:0] padlen; wire [4:0] padlen;
assign padlen=((mode && (descr_stat[8:4]==5'h1f))?(descr_stat[13:9]+1'b1):descr_stat[13:9])+1; assign padlen=((mode && (descr_stat[8:4]==5'h1f))?(descr_stat[13:9]+1'b1):descr_stat[13:9])+1;
reg [15:0] linAddr; /// AF2015: was reg [15:0] linAddr;
reg [16:0] linAddr;
// wire [15:0] linAddr; //replacing with latches to ease timing // wire [15:0] linAddr; //replacing with latches to ease timing
wire [15:0] linAddr_input; ///AAF2015: wire [15:0] linAddr_input;
wire [18:0] linAddr_input; // to match multipler result, 2 MSBs are still discarded
wire [4:0] descr_stat_inc=descr_stat[8:4]+1; wire [4:0] descr_stat_inc=descr_stat[8:4]+1;
assign linAddr_input[15:0] = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; assign linAddr_input = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]};
always @ (negedge clk) if (stepsEn[1]) begin // address should be 1 always @ (negedge clk) if (stepsEn[1]) begin // address should be 1
...@@ -469,7 +471,8 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2)) ...@@ -469,7 +471,8 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10 seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat_inc):5'b0}); ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat_inc):5'b0});
sa[7:3] <= mode?descr_dyn[4:0]:5'b0; sa[7:3] <= mode?descr_dyn[4:0]:5'b0;
linAddr[15:0] <= linAddr_input[15:0]; ///AAF2015: linAddr <= linAddr_input[12:0];
linAddr <= linAddr_input[16:0];
nxtTL <= nxtTLw; nxtTL <= nxtTLw;
tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0) tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0)
...@@ -526,7 +529,8 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2)) ...@@ -526,7 +529,8 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
{descr_stat[3:0],8'b0,mode? {descr_stat[3:0],8'b0,mode?
descr_dyn[9:5]: descr_dyn[9:5]:
descr_dyn[4:0]}: descr_dyn[4:0]}:
{linAddr[15:0]})); /// AF2015: was {linAddr[16:0]}));
{linAddr[16:0]}));
end end
//photofinish hack //photofinish hack
always @ (negedge clk) if (stepsEn[1]) begin always @ (negedge clk) if (stepsEn[1]) begin
......
memctrl353/mcontr353.v
View file @ d6e9be6b
...@@ -359,13 +359,13 @@ module mcontr( ...@@ -359,13 +359,13 @@ module mcontr(
bufCntr256 i_bufCntr0 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[0]), .init(ch_prefirstdrun), .bank(nBuf[1:0]), bufCntr256 i_bufCntr0 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[0]), .init(ch_prefirstdrun), .bank(nBuf[1:0]),
.drun_rd(1'b0), .drun_wr(ch_drun_wr), .dlast(ch_dlast), .drun_rd(1'b0), .drun_wr(ch_drun_wr), .dlast(ch_dlast),
.a(bmad0[8:0]), .en(ch0en), .done(dnch[0])); .a(bmad0[8:0]), .en(ch0en), .done(dnch[0]),.we());
bufCntr256 i_bufCntr1 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[1]), .init(ch_prefirstdrun), .bank(nBuf[1:0]), bufCntr256 i_bufCntr1 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[1]), .init(ch_prefirstdrun), .bank(nBuf[1:0]),
.drun_rd(ch_drun_rd), .drun_wr(1'b0), .dlast(ch_dlast), .drun_rd(ch_drun_rd), .drun_wr(1'b0), .dlast(ch_dlast),
.a(bmad1[8:0]), .we(ch1we), .done(dnch[1])); .a(bmad1[8:0]), .we(ch1we), .done(dnch[1]), .en());
bufCntr256 i_bufCntr2 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[2]), .init(ch_prefirstdrun), .bank(nBuf[1:0]), bufCntr256 i_bufCntr2 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[2]), .init(ch_prefirstdrun), .bank(nBuf[1:0]),
.drun_rd(ch_drun_rd), .drun_wr(1'b0), .dlast(ch_dlast), .drun_rd(ch_drun_rd), .drun_wr(1'b0), .dlast(ch_dlast),
.a(bmad2[8:0]), .we(ch2we), .done(dnch[2])); .a(bmad2[8:0]), .we(ch2we), .done(dnch[2]), .en());
bufCntr256 i_bufCntr3 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[3]), .init(ch_prefirstdrun), .bank(nBuf[1:0]), bufCntr256 i_bufCntr3 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[3]), .init(ch_prefirstdrun), .bank(nBuf[1:0]),
.drun_rd(ch_drun_rd), .drun_wr(ch_drun_wr), .dlast(ch_dlast), .drun_rd(ch_drun_rd), .drun_wr(ch_drun_wr), .dlast(ch_dlast),
.a(bmad3[8:0]), .en (ch3en), .we(ch3owe), .done(dnch[3]) .a(bmad3[8:0]), .en (ch3en), .we(ch3owe), .done(dnch[3])
...@@ -451,7 +451,9 @@ end ...@@ -451,7 +451,9 @@ end
.done(dnch[0]), // data transfer over .done(dnch[0]), // data transfer over
.rq(chnReq[0]), // request (level, sync to iclk) .rq(chnReq[0]), // request (level, sync to iclk)
.rqInit(chnReqInit[0]), // request to Init channel (level, sync to iclk) .rqInit(chnReqInit[0]), // request to Init channel (level, sync to iclk)
.rdy(ch0rdy)); // external ready output .rdy(ch0rdy), // external ready output
.rdy_async(), // output
.wrempty()); // output
channelRequest i_channelRequest1 (.rst(!enSDRAM), // probably for simulation only... channelRequest i_channelRequest1 (.rst(!enSDRAM), // probably for simulation only...
.init(chReqInit[1]), // 1 cycle long, sync to iclk .init(chReqInit[1]), // 1 cycle long, sync to iclk
...@@ -464,7 +466,10 @@ end ...@@ -464,7 +466,10 @@ end
.done(dnch[1]), // data transfer over .done(dnch[1]), // data transfer over
.rq(chnReq[1]), // request (level, sync to iclk) .rq(chnReq[1]), // request (level, sync to iclk)
.rqInit(chnReqInit[1]), // request to Init channel (level, sync to iclk) .rqInit(chnReqInit[1]), // request to Init channel (level, sync to iclk)
.rdy(ch1rdy)); // external ready output .rdy(ch1rdy), // external ready output
.rdy_async(), // output
.wrempty()); // output
channelRequest i_channelRequest2 (.rst(!enSDRAM), // probably for simulation only... channelRequest i_channelRequest2 (.rst(!enSDRAM), // probably for simulation only...
.init(chReqInit[2]), // 1 cycle long, sync to iclk .init(chReqInit[2]), // 1 cycle long, sync to iclk
...@@ -477,7 +482,9 @@ end ...@@ -477,7 +482,9 @@ end
.done(dnch[2]), // data transfer over .done(dnch[2]), // data transfer over
.rq(chnReq[2]), // request (level, sync to iclk) .rq(chnReq[2]), // request (level, sync to iclk)
.rqInit(chnReqInit[2]), // request to Init channel (level, sync to iclk) .rqInit(chnReqInit[2]), // request to Init channel (level, sync to iclk)
.rdy(ch2rdy)); // external ready output .rdy(ch2rdy), // external ready output
.rdy_async(), // output
.wrempty()); // output
channelRequest_1 i_channelRequest3 (.rst(!enSDRAM), // probably for simulation only... channelRequest_1 i_channelRequest3 (.rst(!enSDRAM), // probably for simulation only...
.init(chReqInit[3]), // 1 cycle long, sync to iclk. For now - do nothing in dcc mode .init(chReqInit[3]), // 1 cycle long, sync to iclk. For now - do nothing in dcc mode
...@@ -680,7 +687,7 @@ module channelRequest (rst, // only for simulation? ...@@ -680,7 +687,7 @@ module channelRequest (rst, // only for simulation?
assign ready_off= !cntrsValid || (ecnt[2:0] == rcnt[2:0]); assign ready_off= !cntrsValid || (ecnt[2:0] == rcnt[2:0]);
always @ (posedge eclk or posedge rst) always @ (posedge eclk or posedge rst)
if (rst) ecnt <= 2'b0; if (rst) ecnt <= 3'b0;
else if (start) ecnt[2:0] <= next_ecnt; else if (start) ecnt[2:0] <= next_ecnt;
// reduce latency of rdy - valid next cycle after start // reduce latency of rdy - valid next cycle after start
...@@ -768,7 +775,7 @@ module channelRequest_1 (rst, // only for simulation? ...@@ -768,7 +775,7 @@ module channelRequest_1 (rst, // only for simulation?
assign ready_off= !cntrsValid || (ecnt[2:0] == rcnt[2:0]); assign ready_off= !cntrsValid || (ecnt[2:0] == rcnt[2:0]);
always @ (negedge eclk or posedge rst) always @ (negedge eclk or posedge rst)
if (rst) ecnt <= 2'b0; if (rst) ecnt <= 3'b0;
else if (start) ecnt[2:0] <= next_ecnt; else if (start) ecnt[2:0] <= next_ecnt;
// reduce latency of rdy - valid next cycle after start // reduce latency of rdy - valid next cycle after start
......
memctrl353/sdseq353.v
View file @ d6e9be6b
...@@ -185,8 +185,8 @@ module sdseq (clk0, // global clock 75-100MHz (hope to get to 120MHz with Sparta ...@@ -185,8 +185,8 @@ module sdseq (clk0, // global clock 75-100MHz (hope to get to 120MHz with Sparta
prenext_wr <= drun_wr && pre_next_old; prenext_wr <= drun_wr && pre_next_old;
next <= prenext_refr || prenext_wr || (!drun_wr && pre_next_old); // add m0 and refr here too next <= prenext_refr || prenext_wr || (!drun_wr && pre_next_old); // add m0 and refr here too
decLeft <= (prenext_m1s || prenext_m1d || prenext_m0); // add m0 and refr here too decLeft <= (prenext_m1s || prenext_m1d || prenext_m0); // add m0 and refr here too
if (first) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]); if (first) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
///AF2015 - revert: if (first || rst) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
else if (decLeft) left[4:0] <= left[4:0] -1; else if (decLeft) left[4:0] <= left[4:0] -1;
end end
......
sensor/lens_flat.v
View file @ d6e9be6b
...@@ -87,7 +87,7 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -87,7 +87,7 @@ module lens_flat (sclk, /// system clock @negedge
reg [20:0] BY; /// By reg [20:0] BY; /// By
reg [18:0] C; /// C reg [18:0] C; /// C
reg [16:0] scales[0:3]; // per-color coefficients reg [16:0] scales[0:3]; // per-color coefficients
reg [16:0] scales_r; ///AF: reg [16:0] scales_r;
reg [15:0] fatzero_in; /// zero level to subtract before multiplication reg [15:0] fatzero_in; /// zero level to subtract before multiplication
reg [15:0] fatzero_out; /// zero level to add after multiplication reg [15:0] fatzero_out; /// zero level to add after multiplication
reg [ 3:0] post_scale; /// shift product after first multiplier - maybe needed when using decimation reg [ 3:0] post_scale; /// shift product after first multiplier - maybe needed when using decimation
...@@ -95,7 +95,7 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -95,7 +95,7 @@ module lens_flat (sclk, /// system clock @negedge
wire [18:0] FY; /// F(0,y) wire [18:0] FY; /// F(0,y)
wire [23:0] ERR_Y; /// running error for the first column wire [23:0] ERR_Y; /// running error for the first column
wire [18:0] FXY; /// F(x,y) wire [18:0] FXY; /// F(x,y)
reg [18:0] FXY_sat; ///AF: reg [18:0] FXY_sat;
reg [ 4:0] lens_corr_out; /// lens correction out valid (first clock from column0 ) reg [ 4:0] lens_corr_out; /// lens correction out valid (first clock from column0 )
/// copied form sensorpix353.v /// copied form sensorpix353.v
reg bayer_nset; reg bayer_nset;
...@@ -158,7 +158,7 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -158,7 +158,7 @@ module lens_flat (sclk, /// system clock @negedge
3'h7:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:26]) ? 18'h1ffff:mult_first_res[26: 9]; 3'h7:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:26]) ? 18'h1ffff:mult_first_res[26: 9];
endcase endcase
if (lens_corr_out[4]) pixdo[15:0]=pre_pixdo_with_zero[20]? 16'h0: /// negative - use 0 if (lens_corr_out[4]) pixdo[15:0] <= pre_pixdo_with_zero[20]? 16'h0: /// negative - use 0
((|pre_pixdo_with_zero[19:16])?16'hffff: ///>0xffff - limit by 0xffff ((|pre_pixdo_with_zero[19:16])?16'hffff: ///>0xffff - limit by 0xffff
pre_pixdo_with_zero[15:0]); pre_pixdo_with_zero[15:0]);
end end
...@@ -324,6 +324,7 @@ module lens_flat_line( ...@@ -324,6 +324,7 @@ module lens_flat_line(
if (first_d) F[F_WIDTH-1:0] <= F1[ F_WIDTH-1:0]; if (first_d) F[F_WIDTH-1:0] <= F1[ F_WIDTH-1:0];
else if (next_d) F[F_WIDTH-1:0] <= F[F_WIDTH-1:0]+{{(F_WIDTH-(DF_WIDTH)){dF[(DF_WIDTH)-1]}},dF[(DF_WIDTH)-1:0]}; else if (next_d) F[F_WIDTH-1:0] <= F[F_WIDTH-1:0]+{{(F_WIDTH-(DF_WIDTH)){dF[(DF_WIDTH)-1]}},dF[(DF_WIDTH)-1:0]};
if (first_d) A2X[F_SHIFT+1:1] <= {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]}; if (first_d) A2X[F_SHIFT+1:1] <= {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]};
else if (next) A2X[F_SHIFT+1:1] <= A2X[F_SHIFT+1:1] + {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]}; else if (next) A2X[F_SHIFT+1:1] <= A2X[F_SHIFT+1:1] + {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]};
end end
......
sensor/sensor12bits.v
View file @ d6e9be6b
...@@ -17,8 +17,8 @@ input MCLK, // Master clock ...@@ -17,8 +17,8 @@ input MCLK, // Master clock
ARO, // Array read Out. ARO, // Array read Out.
ARST, // Array Reset. Active low ARST, // Array Reset. Active low
OE, // output enable active low OE, // output enable active low
SCL; // I2C clock SCL; // I2C clock // SuppressThisWarning Veditor: Not yet implemented
inout SDA; // I2C data inout SDA; // I2C data // SuppressThisWarning Veditor: Not yet implemented
input OFST; // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode. input OFST; // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
output [11:0] D; // data output output [11:0] D; // data output
...@@ -33,7 +33,7 @@ parameter ncols = 66; //58; //56; // 129; //128; //1288; ...@@ -33,7 +33,7 @@ parameter ncols = 66; //58; //56; // 129; //128; //1288;
parameter nrows = 18; // 16; // 1032; parameter nrows = 18; // 16; // 1032;
parameter nrowb = 1; // number of "blank rows" from vact to 1-st hact parameter nrowb = 1; // number of "blank rows" from vact to 1-st hact
parameter nrowa = 1; // number of "blank rows" from last hact to end of vact parameter nrowa = 1; // number of "blank rows" from last hact to end of vact
parameter nAV = 24; //240; // clocks from ARO to VACT (actually from en_dclkd) parameter nAV = 24; //240; // clocks from ARO to VACT (actually from en_dclkd) // SuppressThisWarning Veditor UNUSED
parameter nbpf = 20; //16; // bpf length parameter nbpf = 20; //16; // bpf length
parameter ngp1 = 8; // bpf to hact parameter ngp1 = 8; // bpf to hact
parameter nVLO = 1; // VACT=0 in video mode (clocks) parameter nVLO = 1; // VACT=0 in video mode (clocks)
...@@ -64,7 +64,7 @@ parameter t_HACT= ncols; // 1288 ...@@ -64,7 +64,7 @@ parameter t_HACT= ncols; // 1288
parameter t_afterHACT=lline-nbpf-ngp1-ncols; // 352 parameter t_afterHACT=lline-nbpf-ngp1-ncols; // 352
parameter t_lastline= nrowa*lline+1; // 1664 parameter t_lastline= nrowa*lline+1; // 1664
reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels // SuppressThisWarning Veditor VDT_BUG - assigned in system task
// $readmemh("sensor.dat",sensor_data); // $readmemh("sensor.dat",sensor_data);
......
sensor/sensorpads353.v
View file @ d6e9be6b
...@@ -86,7 +86,7 @@ module sensorpads (/// interface to DCM ...@@ -86,7 +86,7 @@ module sensorpads (/// interface to DCM
output pclk2x; output pclk2x;
input vact; input vact;
input hact; //output in fillfactory mode input hact; //output in fillfactory mode
inout bpf; // output in fillfactory mode inout bpf; // output in fillfactory mode // SuppressThisWarning Veditor - not used as output
inout [11:0] pxd; //actually only 2 LSBs are inouts inout [11:0] pxd; //actually only 2 LSBs are inouts
inout mrst; inout mrst;
output arst; output arst;
......
x353.v
View file @ d6e9be6b
This diff is collapsed.
x353.xcf
View file @ d6e9be6b
...@@ -201,14 +201,14 @@ TIMESPEC "TS_CLK1" = PERIOD "CLK1" 10.4 ns HIGH 50 %; #96MHz ...@@ -201,14 +201,14 @@ TIMESPEC "TS_CLK1" = PERIOD "CLK1" 10.4 ns HIGH 50 %; #96MHz
#TIMESPEC "TS_CLK1" = PERIOD "CLK1" 18.4 ns HIGH 50 %; #TEMPORARY TO FIND A PROBLEM #TIMESPEC "TS_CLK1" = PERIOD "CLK1" 18.4 ns HIGH 50 %; #TEMPORARY TO FIND A PROBLEM
TIMEGRP "CPU_ADDR" = pads("A<*>"); TIMEGRP "CPU_ADDR" = PADS("A<*>");
TIMEGRP "CPU_ADDRCE" = "CPU_ADDR" pads("CE*"); TIMEGRP "CPU_ADDRCE" = "CPU_ADDR" PADS("CE*");
TIMEGRP "CPU_DATA" = pads("D<*>"); TIMEGRP "CPU_DATA" = PADS("D<*>");
TIMEGRP "WE" = pads("WE"); TIMEGRP "WE" = PADS("WE");
TIMEGRP "OE" = pads("OE"); TIMEGRP "OE" = PADS("OE");
TIMEGRP "DACK_PAD"= pads("DACK*"); TIMEGRP "DACK_PAD"= PADS("DACK*");
TIMEGRP "DREQ_PAD"= pads("DREQ*"); TIMEGRP "DREQ_PAD"= PADS("DREQ*");
TIMEGRP "ALLPADS"= pads("*"); TIMEGRP "ALLPADS"= PADS("*");
NET "idack0" TPTHRU = "IDACK0_TP"; NET "idack0" TPTHRU = "IDACK0_TP";
NET "idack1" TPTHRU = "IDACK1_TP"; NET "idack1" TPTHRU = "IDACK1_TP";
...@@ -217,8 +217,8 @@ NET "idack1" TPTHRU = "IDACK1_TP"; ...@@ -217,8 +217,8 @@ NET "idack1" TPTHRU = "IDACK1_TP";
#TIMESPEC "TS_DACK_DREQ0" = FROM "DACK_PAD" THRU "IDACK0_TP" THRU "IDREQ0_TP" TO "DREQ_PAD" 9.5 ns; #TIMESPEC "TS_DACK_DREQ0" = FROM "DACK_PAD" THRU "IDACK0_TP" THRU "IDREQ0_TP" TO "DREQ_PAD" 9.5 ns;
#TIMESPEC "TS_DACK_DREQ1" = FROM "DACK_PAD" THRU "IDACK1_TP" THRU "IDREQ1_TP" TO "DREQ_PAD" 9.5 ns; #TIMESPEC "TS_DACK_DREQ1" = FROM "DACK_PAD" THRU "IDACK1_TP" THRU "IDREQ1_TP" TO "DREQ_PAD" 9.5 ns;
NET "*/cwr" TNM_NET = "TNM_CWR"; NET "*/cwr" TNM_NET = "TNM_CWR";
TIMEGRP "TG_CWRDEST" = "TNM_CWR" except latches ("*"); # RAMS, FFS TIMEGRP "TG_CWRDEST" = "TNM_CWR" except LATCHES ("*"); # RAMS, FFS
###MARK1# TIMEGRP "TG_LATCHES_A" = latches ("i_sysinterface/i_a*"); ###MARK1# TIMEGRP "TG_LATCHES_A" = LATCHES ("i_sysinterface/i_a*");
NET "DACK*" TNM_NET = "DACK"; NET "DACK*" TNM_NET = "DACK";
NET "SDA0*" TNM_NET = "SDA0"; NET "SDA0*" TNM_NET = "SDA0";
NET "sclk0" TNM_NET = "TNM_CLK0"; NET "sclk0" TNM_NET = "TNM_CLK0";
...@@ -242,8 +242,8 @@ NET "i_sensorpads/i_sensor_phase/mode_14bits_sync" TIG; ...@@ -242,8 +242,8 @@ NET "i_sensorpads/i_sensor_phase/mode_14bits_sync" TIG;
NET "hact_length*" TIG; NET "hact_length*" TIG;
NET "cb_*" TIG; NET "cb_*" TIG;
TIMEGRP "TG_CLK1" = pads("CLK1"); TIMEGRP "TG_CLK1" = PADS("CLK1");
TIMEGRP "TG_DCLK" = pads("DCLK"); TIMEGRP "TG_DCLK" = PADS("DCLK");
#TIMESPEC "TS_SENSORCLOCK" = FROM "TG_CLK1" TO "TG_DCLK" 14.0 ns; #TIMESPEC "TS_SENSORCLOCK" = FROM "TG_CLK1" TO "TG_DCLK" 14.0 ns;
...@@ -268,65 +268,65 @@ TIMESPEC "TS_DACK0" = FROM "DACK" TO "ALLPADS" 17 ns; ...@@ -268,65 +268,65 @@ TIMESPEC "TS_DACK0" = FROM "DACK" TO "ALLPADS" 17 ns;
TIMEGRP "TG_ALL_SYNC"= FFS RAMS MULTS; TIMEGRP "TG_ALL_SYNC"= FFS RAMS MULTS;
TIMEGRP "TG_DOUBLECYCS2"= ffs("i_mcontr/i_descrproc/seq_par*") TIMEGRP "TG_DOUBLECYCS2"= FFS("i_mcontr/i_descrproc/seq_par*")
ffs("i_mcontr/i_descrproc/sa*") FFS("i_mcontr/i_descrproc/sa*")
ffs("i_mcontr/i_descrproc/nxtTL*") FFS("i_mcontr/i_descrproc/nxtTL*")
ffs("i_mcontr/i_descrproc/tile*") FFS("i_mcontr/i_descrproc/tile*")
ffs("i_mcontr/i_descrproc/mode*") FFS("i_mcontr/i_descrproc/mode*")
ffs("i_mcontr/i_descrproc/WnR*") FFS("i_mcontr/i_descrproc/WnR*")
ffs("i_mcontr/i_descrproc/depend*") FFS("i_mcontr/i_descrproc/depend*")
ffs("i_mcontr/i_descrproc/nextFrame*") FFS("i_mcontr/i_descrproc/nextFrame*")
ffs("i_mcontr/i_descrproc/suspXfer*") FFS("i_mcontr/i_descrproc/suspXfer*")
ffs("i_mcontr/i_descrproc/lineNumSource*") FFS("i_mcontr/i_descrproc/lineNumSource*")
ffs("i_mcontr/i_descrproc/lineNumDest*") FFS("i_mcontr/i_descrproc/lineNumDest*")
ffs("i_mcontr/i_descrproc/prevStripSource*") FFS("i_mcontr/i_descrproc/prevStripSource*")
ffs("i_mcontr/i_descrproc/last_lines_reg*") FFS("i_mcontr/i_descrproc/last_lines_reg*")
ffs("i_mcontr/i_descrproc/first_tile_reg*") FFS("i_mcontr/i_descrproc/first_tile_reg*")
ffs("i_mcontr/i_descrproc/first_tile_dest*") FFS("i_mcontr/i_descrproc/first_tile_dest*")
ffs("i_mcontr/i_descrproc/nxtTFr*") FFS("i_mcontr/i_descrproc/nxtTFr*")
ffs("i_mcontr/i_descrproc/srcAtStart*") FFS("i_mcontr/i_descrproc/srcAtStart*")
mults("i_mcontr/i_descrproc/linAddr*"); MULTS("i_mcontr/i_descrproc/linAddr*");
TIMESPEC "TS_DOUBLECYCS2" = FROM "TG_DOUBLECYCS2" TO "TG_ALL_SYNC" "TS_CLK0" * 2; TIMESPEC "TS_DOUBLECYCS2" = FROM "TG_DOUBLECYCS2" TO "TG_ALL_SYNC" "TS_CLK0" * 2;
TIMEGRP "TG_FAST_SRC3"= ffs("*stepsE*") ffs("*stepsI*") ffs("*stepsDwe*"); TIMEGRP "TG_FAST_SRC3"= FFS("*stepsE*") FFS("*stepsI*") FFS("*stepsDwe*");
TIMEGRP "TG_SLOW_SRC3" = TG_ALL_SYNC EXCEPT "TG_FAST_SRC3"; TIMEGRP "TG_SLOW_SRC3" = TG_ALL_SYNC EXCEPT "TG_FAST_SRC3";
TIMEGRP "TG_DOUBLEDEST3"= ffs("i_mcontr/i_descrproc/seq_par*") TIMEGRP "TG_DOUBLEDEST3"= FFS("i_mcontr/i_descrproc/seq_par*")
ffs("i_mcontr/i_descrproc/sa*") FFS("i_mcontr/i_descrproc/sa*")
ffs("i_mcontr/i_descrproc/nxtTL*") FFS("i_mcontr/i_descrproc/nxtTL*")
ffs("i_mcontr/i_descrproc/tile*") FFS("i_mcontr/i_descrproc/tile*")
ffs("i_mcontr/i_descrproc/mode*") FFS("i_mcontr/i_descrproc/mode*")
ffs("i_mcontr/i_descrproc/WnR*") FFS("i_mcontr/i_descrproc/WnR*")
ffs("i_mcontr/i_descrproc/depend*") FFS("i_mcontr/i_descrproc/depend*")
ffs("i_mcontr/i_descrproc/nextFrame*") FFS("i_mcontr/i_descrproc/nextFrame*")
ffs("i_mcontr/i_descrproc/nextBlocksEn*") FFS("i_mcontr/i_descrproc/nextBlocksEn*")
ffs("i_mcontr/i_descrproc/suspXfer*") FFS("i_mcontr/i_descrproc/suspXfer*")
ffs("i_mcontr/i_descrproc/lineNumSource*") FFS("i_mcontr/i_descrproc/lineNumSource*")
ffs("i_mcontr/i_descrproc/lineNumDest*") FFS("i_mcontr/i_descrproc/lineNumDest*")
ffs("i_mcontr/i_descrproc/prevStripSource*") FFS("i_mcontr/i_descrproc/prevStripSource*")
ffs("i_mcontr/i_descrproc/rovr*") FFS("i_mcontr/i_descrproc/rovr*")
ffs("i_mcontr/i_descrproc/last_lines_reg*") FFS("i_mcontr/i_descrproc/last_lines_reg*")
ffs("i_mcontr/i_descrproc/first_tile_reg*") FFS("i_mcontr/i_descrproc/first_tile_reg*")
ffs("i_mcontr/i_descrproc/first_tile_dest*") FFS("i_mcontr/i_descrproc/first_tile_dest*")
ffs("i_mcontr/i_descrproc/nxtTFr*") FFS("i_mcontr/i_descrproc/nxtTFr*")
ffs("i_mcontr/i_descrproc/nxtTF_p*") FFS("i_mcontr/i_descrproc/nxtTF_p*")
ffs("i_mcontr/i_descrproc/srcAtStart*") FFS("i_mcontr/i_descrproc/srcAtStart*")
mults("i_mcontr/i_descrproc/linAddr*"); MULTS("i_mcontr/i_descrproc/linAddr*");
TIMESPEC "TS_DOUBLECYCS3" = FROM "TG_SLOW_SRC3" TO "TG_DOUBLEDEST3" "TS_CLK0" * 2; TIMESPEC "TS_DOUBLECYCS3" = FROM "TG_SLOW_SRC3" TO "TG_DOUBLEDEST3" "TS_CLK0" * 2;
## Next - redundant? ## Next - redundant?
##TIMESPEC "TS_DOUBLECYCS4" = FROM FFS("*i_chArbit/chNum*") TO "TG_DOUBLEDEST3" TS_CLK0*2; ##TIMESPEC "TS_DOUBLECYCS4" = FROM FFS("*i_chArbit/chNum*") TO "TG_DOUBLEDEST3" TS_CLK0*2;
TIMEGRP "TG_HUFFRAMS"= rams ("*i_huffman*") ; TIMEGRP "TG_HUFFRAMS"= RAMS ("*i_huffman*") ;
#FIXME: Constraint <TIMEGRP "TG_HUFFFFS" ... does not match any design objects. #FIXME: Constraint <TIMEGRP "TG_HUFFFFS" ... does not match any design objects.
TIMEGRP "TG_HUFFFFS"= ffs ("*i_huffman*") TIMEGRP "TG_HUFFFFS"= FFS ("*i_huffman*")
ffs ("*i_stuffer*") ; FFS ("*i_stuffer*") ;
TIMEGRP "TG_HUFFLATCHES"= latches ("*i_huffman*") ; TIMEGRP "TG_HUFFLATCHES"= LATCHES ("*i_huffman*") ;
# some registers in Huffman module are isolated from others through latches too - never used? # some registers in Huffman module are isolated from others through latches too - never used?
##TIMEGRP "TG_HUFFFFS_ISOLOUT" = ffs ("*i_huff_fifo/load_q"); ##TIMEGRP "TG_HUFFFFS_ISOLOUT" = FFS ("*i_huff_fifo/load_q");
TIMEGRP "TG_STUFFER_WAS_READY_EARLY" = latches ("i_compressor/i_huffman/i_stuffer_was_rdy_early") ; TIMEGRP "TG_STUFFER_WAS_READY_EARLY" = LATCHES ("i_compressor/i_huffman/i_stuffer_was_rdy_early") ;
TIMEGRP "TG_HUFF_FIFO_LOAD_Q" = ffs ("i_compressor/i_huffman/i_huff_fifo/load_q") ; TIMEGRP "TG_HUFF_FIFO_LOAD_Q" = FFS ("i_compressor/i_huffman/i_huff_fifo/load_q") ;
TIMEGRP "TG_COMPRESSOR"= ffs ("*i_compressor*") ; TIMEGRP "TG_COMPRESSOR"= FFS ("*i_compressor*") ;
### THe two below constraints are not needed, they are covered by "TS_HUFFLATCHES" and "TS_HUFFLATCHESI" ### THe two below constraints are not needed, they are covered by "TS_HUFFLATCHES" and "TS_HUFFLATCHESI"
## TIMESPEC "TS_HUFF_FIFO_LOAD_Q"= FROM "TG_STUFFER_WAS_READY_EARLY" TO "TG_HUFFFFS" "TS_CLK0" * 0.625; ## TIMESPEC "TS_HUFF_FIFO_LOAD_Q"= FROM "TG_STUFFER_WAS_READY_EARLY" TO "TG_HUFFFFS" "TS_CLK0" * 0.625;
## TIMESPEC "TS_STUFFER_WAS_READY_EARLY"= FROM "TG_HUFFFFS" TO "TG_STUFFER_WAS_READY_EARLY" "TS_CLK0" * 0.7; ## TIMESPEC "TS_STUFFER_WAS_READY_EARLY"= FROM "TG_HUFFFFS" TO "TG_STUFFER_WAS_READY_EARLY" "TS_CLK0" * 0.7;
...@@ -376,8 +376,8 @@ TIMESPEC "TS_PCLK_PCLK2X" = FROM "TNM_PCLK" TO "TNM_PCLK2X" TIG; ...@@ -376,8 +376,8 @@ TIMESPEC "TS_PCLK_PCLK2X" = FROM "TNM_PCLK" TO "TNM_PCLK2X" TIG;
TIMEGRP "TG_HIST_DOUBLE_DEST"= ffs("*hist_post*"); TIMEGRP "TG_HIST_DOUBLE_DEST"= FFS("*hist_post*");
TIMEGRP "TG_HIST_DOUBLE_SRC "= ffs("*hist_pre*"); TIMEGRP "TG_HIST_DOUBLE_SRC "= FFS("*hist_pre*");
TIMESPEC "TS_HIST_DOUBLECYC1" = FROM FFS("*hist_pre*") TO FFS("*hist_post*") "TS_CLK1" ; TIMESPEC "TS_HIST_DOUBLECYC1" = FROM FFS("*hist_pre*") TO FFS("*hist_post*") "TS_CLK1" ;
...@@ -388,10 +388,10 @@ INST "i_histogram/size_height_*" TIG; ...@@ -388,10 +388,10 @@ INST "i_histogram/size_height_*" TIG;
INST "i_histogram/minus_pos_left_*" TIG; INST "i_histogram/minus_pos_left_*" TIG;
INST "i_histogram/pos_left_is_zero*" TIG; INST "i_histogram/pos_left_is_zero*" TIG;
TIMEGRP "TG_HIST_DOUBLE2_SRC"= ffs("i_histogram/pix_cntr*"); TIMEGRP "TG_HIST_DOUBLE2_SRC"= FFS("i_histogram/pix_cntr*");
TIMEGRP "TG_HIST_DOUBLE2_DST"= ffs("i_histogram/pix_cntr*") TIMEGRP "TG_HIST_DOUBLE2_DST"= FFS("i_histogram/pix_cntr*")
ffs("i_histogram/line_started*") FFS("i_histogram/line_started*")
ffs("i_histogram/line_ended*") ; FFS("i_histogram/line_ended*") ;
TIMESPEC "TS_HIST_DOUBLECYC2" = FROM "TG_HIST_DOUBLE2_SRC" TO "TG_HIST_DOUBLE2_DST" "TS_CLK1" ; TIMESPEC "TS_HIST_DOUBLECYC2" = FROM "TG_HIST_DOUBLE2_SRC" TO "TG_HIST_DOUBLE2_DST" "TS_CLK1" ;
......
x353_1.sav
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x353_1.tf
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