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Commit d6e9be6b authored by Andrey Filippov's avatar Andrey Filippov
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fixing VDT warnings, splitting testbench file, adding modified primitive SLR version for simulation

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.project
View file @ d6e9be6b
...@@ -9,20 +9,50 @@ ...@@ -9,20 +9,50 @@
<natures> <natures>
</natures> </natures>
<linkedResources> <linkedResources>
<link>
<name>ise_logs/ISEMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEMap-20150726165658761.log</location>
</link>
<link>
<name>ise_logs/ISENGDBuild.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150726165546847.log</location>
</link>
<link>
<name>ise_logs/ISEPAR.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150726165911986.log</location>
</link>
<link> <link>
<name>ise_logs/ISEPartgen.log</name> <name>ise_logs/ISEPartgen.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log</location> <location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150726172041010.log</location>
</link>
<link>
<name>ise_logs/ISETraceMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150726213039147.log</location>
</link> </link>
<link> <link>
<name>ise_logs/ISExst.log</name> <name>ise_logs/ISExst.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150726141146079.log</location> <location>/home/andrey/git/x353/ise_logs/ISExst-20150726165049304.log</location>
</link>
<link>
<name>ise_state/x353-map.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-map-20150726165658761.tgz</location>
</link>
<link>
<name>ise_state/x353-ngdbuild.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150726165546847.tgz</location>
</link> </link>
<link> <link>
<name>ise_state/x353-synth.tgz</name> <name>ise_state/x353-synth.tgz</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150726135708468.tgz</location> <location>/home/andrey/git/x353/ise_state/x353-synth-20150726165049304.tgz</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
README.md
View file @ d6e9be6b
...@@ -18,7 +18,7 @@ Here is what makes it difficult: ...@@ -18,7 +18,7 @@ Here is what makes it difficult:
2. Last verion of the ISE (it is ISE 14.7) can not use the older code "as is" 2. Last verion of the ISE (it is ISE 14.7) can not use the older code "as is"
3. We were able to modify the Verilog code to be parsed by the current XST, but it does not 3. We were able to modify the Verilog code to be parsed by the current XST, but it does not
recognize some statements in the *.xcf constraints file (I had to rename original *.ucf to *.xcf). recognize some statements in the *.xcf constraints file (I had to rename original *.ucf to *.xcf).
4. Attempt to try old parser (Suggested by XST itself as the new parser is not the default for 4. Attempt to try old parser (suggested by XST itself as the new parser is not the default for
the Spartan 3e): the Spartan 3e):
``` ```
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default
......
compressor/color_proc353.v
View file @ d6e9be6b
...@@ -198,7 +198,7 @@ input hdr; // second green absolute, not difference ...@@ -198,7 +198,7 @@ input hdr; // second green absolute, not difference
reg four_blocks_r; reg four_blocks_r;
reg scale_diff_r; reg scale_diff_r;
reg hdr_r; reg hdr_r;
reg [1:0] tile_margin_r; reg [1:0] tile_margin_r; // SuppressThisWarning Veditor UNUSED
// reg [2:0] tile_shift_r; // reg [2:0] tile_shift_r;
reg [1:0] bayer_phase_r; reg [1:0] bayer_phase_r;
reg [3:0] bayer_phase_onehot; reg [3:0] bayer_phase_onehot;
...@@ -259,7 +259,7 @@ input hdr; // second green absolute, not difference ...@@ -259,7 +259,7 @@ input hdr; // second green absolute, not difference
last_from_sdram <= en & preline_was_0 && (prepix[4:0]==0); last_from_sdram <= en & preline_was_0 && (prepix[4:0]==0);
inc_sdrama <= en & (pre_first_pixel || (inc_sdrama && !last_from_sdram )); inc_sdrama <= en & (pre_first_pixel || (inc_sdrama && !last_from_sdram ));
if (pre_first_pixel) sdram_a9[8:0] <= sdrama_top_left[8:0]; if (pre_first_pixel) sdram_a9[8:0] <= sdrama_top_left[8:0];
else if (inc_sdrama) sdram_a9[8:0] <= sdram_a9[8:0] + (pre_start_of_line ? sdrama_line_inc[2:0] : 1); else if (inc_sdrama) sdram_a9[8:0] <= sdram_a9[8:0] + (pre_start_of_line ? sdrama_line_inc[2:0] : 3'b1);
if (!en || memWasInit) sdram_a9_page[1:0] <= 2'h0; if (!en || memWasInit) sdram_a9_page[1:0] <= 2'h0;
else if (last_from_sdram && inc_sdrama) sdram_a9_page[1:0] <= sdram_a9_page[1:0]+1; else if (last_from_sdram && inc_sdrama) sdram_a9_page[1:0] <= sdram_a9_page[1:0]+1;
...@@ -445,7 +445,7 @@ input hdr; // second green absolute, not difference ...@@ -445,7 +445,7 @@ input hdr; // second green absolute, not difference
if (first_pixel) begin if (first_pixel) begin
first0 <= willbe_first; first0 <= willbe_first;
last0 <= (bcntr[17:0]==17'b0); last0 <= (bcntr[17:0] == 18'b0);
end end
if (ccv_out_start) begin if (ccv_out_start) begin
first <= first0; first <= first0;
......
compressor/compressor333.v
View file @ d6e9be6b
...@@ -220,8 +220,8 @@ module compressor(// cwr, // CPU write - global clock ...@@ -220,8 +220,8 @@ module compressor(// cwr, // CPU write - global clock
// //
// control registetr bits // control registetr bits
wire cr_w; // data written to cr (1 cycle) - now just to reset legacy IRQ wire cr_w; // data written to cr (1 cycle) - now just to reset legacy IRQ
wire raw_dv; // input pixel data valid (pxd[7:0]may be sent to DMA buffer through multiplexor) wire raw_dv; // input pixel data valid (pxd[7:0]may be sent to DMA buffer through multiplexor) // SuppressThisWarning Veditor UNUSED
wire color_dv; // unused // color data valid (color_d[7:0] may be sent to DMA buffer through multiplexor) wire color_dv; // unused // color data valid (color_d[7:0] may be sent to DMA buffer through multiplexor)// SuppressThisWarning Veditor UNUSED
wire [ 9:0] color_d; // data out stream from color space converter (6X64 blocks for each MCU - 4Y, Cb,Cr) wire [ 9:0] color_d; // data out stream from color space converter (6X64 blocks for each MCU - 4Y, Cb,Cr)
wire [ 2:0] color_tn; // tile number in an MCU from color space converter (valid @ color_dv) wire [ 2:0] color_tn; // tile number in an MCU from color space converter (valid @ color_dv)
wire [ 8:0] color_avr; // [8:0] DC (average value) 9 bit signed for Y: 9'h000..9'h0ff, for C - 9h100..9'h000..9'h0ff wire [ 8:0] color_avr; // [8:0] DC (average value) 9 bit signed for Y: 9'h000..9'h0ff, for C - 9h100..9'h000..9'h0ff
...@@ -230,7 +230,7 @@ module compressor(// cwr, // CPU write - global clock ...@@ -230,7 +230,7 @@ module compressor(// cwr, // CPU write - global clock
// wire dct_en; // wire dct_en;
wire dct_start; wire dct_start;
wire dct_dv; wire dct_dv; // SuppressThisWarning Veditor UNUSED
wire [12:0] dct_out; wire [12:0] dct_out;
wire dct_last_in; // output high during input of the last of 64 pixels in a 8x8 block wire dct_last_in; // output high during input of the last of 64 pixels in a 8x8 block
wire dct_pre_first_out; // 1 cycle ahead of the first output in a 64 block wire dct_pre_first_out; // 1 cycle ahead of the first output in a 64 block
...@@ -245,7 +245,7 @@ module compressor(// cwr, // CPU write - global clock ...@@ -245,7 +245,7 @@ module compressor(// cwr, // CPU write - global clock
wire focus_ds; wire focus_ds;
// wire enc_first; // wire enc_first;
wire enc_last; wire enc_last; // SuppressThisWarning Veditor UNUSED
wire [15:0] enc_do; wire [15:0] enc_do;
wire enc_dv; wire enc_dv;
...@@ -664,8 +664,8 @@ FD i_is_compressing (.Q(is_compressing),.C(clk), .D(cmprs_en && (go_single || (i ...@@ -664,8 +664,8 @@ FD i_is_compressing (.Q(is_compressing),.C(clk), .D(cmprs_en && (go_single || (i
// single-cycle @ negedge sclk // single-cycle @ negedge sclk
`ifdef debug_compressor `ifdef debug_compressor
wire debug_bcntrIsZero; wire debug_bcntrIsZero;
wire [17:0] debug_bcntr; wire [17:0] debug_bcntr; //SuppressThisWarning Veditor UNUSED
`endif `endif
color_proc i_color_proc(.clk(clk), // pixel clock 37.5MHz color_proc i_color_proc(.clk(clk), // pixel clock 37.5MHz
.en(cmprs_en), // Enable (0 will reset states) .en(cmprs_en), // Enable (0 will reset states)
...@@ -1080,7 +1080,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk) ...@@ -1080,7 +1080,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk)
reg [23:0] cr; ///AF: reg [23:0] cr;
reg [17:0] ntiles; reg [17:0] ntiles;
reg [15:0] ntiles0; reg [15:0] ntiles0;
reg [17:0] ntiles1; reg [17:0] ntiles1;
...@@ -1095,7 +1095,8 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk) ...@@ -1095,7 +1095,8 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk)
assign rcs[1:0]={cwe && rs, cwe && ~rs}; assign rcs[1:0]={cwe && rs, cwe && ~rs};
reg rcs0_d, rcs0_dd, rcs1_d; reg rcs0_d, rcs0_dd;
///AF: reg rcs1_d;
reg [2:0] rcs1d; reg [2:0] rcs1d;
reg [1:0] is_compressing_sclk; // sync to negedge sclk reg [1:0] is_compressing_sclk; // sync to negedge sclk
...@@ -1168,7 +1169,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk) ...@@ -1168,7 +1169,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk)
// always @ (posedge clk) cr[23:0] <=cri[23:0]; // make it sync // always @ (posedge clk) cr[23:0] <=cri[23:0]; // make it sync
always @ (negedge sclk) if (rcs[1]) ntiles0[15:0] <= di[15:0]; always @ (negedge sclk) if (rcs[1]) ntiles0[15:0] <= di[15:0];
// always @ (negedge sclk) if (rcs1_d) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]}; // always @ (negedge sclk) if (rcs1_d) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]};
always @ (negedge sclk) if (rcs1d[0]) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]}; always @ (negedge sclk) if (rcs1d[0]) ntiles1[17:0] <= {di[ 1:0],ntiles0[15:0]};
always @ (negedge sclk) if (rcs1d[2]) ntiles1_prev[17:0] <= ntiles1[17:0]; always @ (negedge sclk) if (rcs1d[2]) ntiles1_prev[17:0] <= ntiles1[17:0];
// rcs1d[2:0]<={rcs1d[1:0],rcs[1]}; // rcs1d[2:0]<={rcs1d[1:0],rcs[1]};
......
compressor/csconvert_mono.v
View file @ d6e9be6b
...@@ -129,7 +129,10 @@ module csconvert_jp4diff (en, ...@@ -129,7 +129,10 @@ module csconvert_jp4diff (en,
reg dly_1; reg dly_1;
reg [14:0] dly_16; reg [14:0] dly_16;
reg dly_17; reg dly_17;
wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17:dly_16):(bayer_phase[0]?dly_1:pre_first_in); // wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17:dly_16):(bayer_phase[0]?dly_1:pre_first_in);
///AF2015 - What was supposed to be here for "dly_16" (15 bits, expected 1) - any non-zero or [14]?
// wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: (|dly_16)):(bayer_phase[0]?dly_1:pre_first_in);
wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: dly_16[14]):(bayer_phase[0]?dly_1:pre_first_in);
reg [7:0] iadr; reg [7:0] iadr;
reg iadr_run; reg iadr_run;
reg [1:0] mux_plus_sel; reg [1:0] mux_plus_sel;
......
compressor/focus_sharp.v
View file @ d6e9be6b
...@@ -234,7 +234,8 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0]; ...@@ -234,7 +234,8 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0];
use_k_dly[5:0]<={use_k_dly[4:0],use_coef}; use_k_dly[5:0]<={use_k_dly[4:0],use_coef};
acc_ldval <= !(|start2[7:6]); acc_ldval <= !(|start2[7:6]);
if (acc_clear || (acc_corr && acc_blk[23])) acc_blk[23:0] <= {1'b0,{23{acc_ldval}}}; if (acc_clear || (acc_corr && acc_blk[23])) acc_blk[23:0] <= {1'b0,{23{acc_ldval}}};
else if (acc_add) acc_blk[23:0] <= acc_blk[23:0]+mult_p[35:8]; ///AF: else if (acc_add) acc_blk[23:0] <= acc_blk[23:0]+mult_p[35:8];
else if (acc_add) acc_blk[23:0] <= acc_blk[23:0]+mult_p[31:8];
if (acc_to_out) fdo[11:0] <= (|acc_blk[23:20])?12'hfff:acc_blk[19:8]; // positive, 0..0xfff if (acc_to_out) fdo[11:0] <= (|acc_blk[23:20])?12'hfff:acc_blk[19:8]; // positive, 0..0xfff
if (acc_to_out) sum_blk[22:0] <= acc_blk[22:0]; // accumulator for the sum ((a[i]*d[i])^2), copied at block end if (acc_to_out) sum_blk[22:0] <= acc_blk[22:0]; // accumulator for the sum ((a[i]*d[i])^2), copied at block end
...@@ -291,17 +292,11 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0]; ...@@ -291,17 +292,11 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0];
); );
RAM16X1D i_tn0 (.D(tni[0]),.DPO(tn[0]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn1 (.D(tni[1]),.DPO(tn[1]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn2 (.D(tni[2]),.DPO(tn[2]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_first (.D(firsti),.DPO(first),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn0 (.D(tni[0]),.DPO(tn[0]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb)); RAM16X1D i_last (.D(lasti), .DPO(last), .A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn1 (.D(tni[1]),.DPO(tn[1]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_tn2 (.D(tni[2]),.DPO(tn[2]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_first (.D(firsti),.DPO(first),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_last (.D(lasti), .DPO(last), .A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAMB16_S18_S18 i_focus_dct_tab ( RAMB16_S18_S18 i_focus_dct_tab (
.DOA(tdo[15:0]), // Port A 16-bit Data Output .DOA(tdo[15:0]), // Port A 16-bit Data Output
......
compressor/huffman333.v
View file @ d6e9be6b
...@@ -70,7 +70,7 @@ module huffman (pclk, // half frequency, sync to incoming data ...@@ -70,7 +70,7 @@ module huffman (pclk, // half frequency, sync to incoming data
wire [19:0] tables_out; wire [19:0] tables_out;
wire [15:0] hcode; // table output huffman code (1..16 bits) wire [15:0] hcode; // table output huffman code (1..16 bits)
wire [ 3:0] hlen; // table - code length only 4 LSBs are used wire [ 3:0] hlen; // table - code length only 4 LSBs are used
wire [11:0] unused; wire [11:0] unused; // SuppressThisWarning Veditor UNUSED
reg [ 7:0] haddr_r; // index in huffman table reg [ 7:0] haddr_r; // index in huffman table
wire [ 7:0] haddr_next; wire [ 7:0] haddr_next;
wire [ 8:0] haddr; // index in huffman table (after latches) wire [ 8:0] haddr; // index in huffman table (after latches)
...@@ -340,7 +340,7 @@ module huff_fifo (pclk, ...@@ -340,7 +340,7 @@ module huff_fifo (pclk,
reg [9:0] ra_r; reg [9:0] ra_r;
wire [9:0] ra; wire [9:0] ra;
wire [15:0] q; wire [15:0] q;
reg load_q; reg load_q; // SuppressThisWarning Veditor VDT_BUG
wire [15:0] fifo_o; wire [15:0] fifo_o;
reg ds1; // ds delayed by one pclk to give time to block ram to write data. Not needed likely. reg ds1; // ds delayed by one pclk to give time to block ram to write data. Not needed likely.
reg synci; reg synci;
...@@ -404,7 +404,6 @@ module huff_fifo (pclk, ...@@ -404,7 +404,6 @@ module huff_fifo (pclk,
LD i_ra1 (.Q(ra[1]),.G(clk),.D(ra_r[1])); LD i_ra1 (.Q(ra[1]),.G(clk),.D(ra_r[1]));
LD i_ra0 (.Q(ra[0]),.G(clk),.D(ra_r[0])); LD i_ra0 (.Q(ra[0]),.G(clk),.D(ra_r[0]));
always @ (posedge clk) begin always @ (posedge clk) begin
// load_q <= dav?want_read:re_r;
load_q <= dav?want_read_early:re_r; load_q <= dav?want_read_early:re_r;
end end
LD_1 i_q15 (.Q( q[15]),.G(clk),.D(load_q?fifo_o[15]:q[15])); LD_1 i_q15 (.Q( q[15]),.G(clk),.D(load_q?fifo_o[15]:q[15]));
......
compressor/xdct353.v
View file @ d6e9be6b
...@@ -223,6 +223,7 @@ This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of t ...@@ -223,6 +223,7 @@ This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of t
reg[9:0] xa0_in, xa1_in, xa2_in, xa3_in, xa4_in, xa5_in, xa6_in, xa7_in; reg[9:0] xa0_in, xa1_in, xa2_in, xa3_in, xa4_in, xa5_in, xa6_in, xa7_in;
reg[9:0] xa0_reg, xa1_reg, xa2_reg, xa3_reg, xa4_reg, xa5_reg, xa6_reg, xa7_reg; reg[9:0] xa0_reg, xa1_reg, xa2_reg, xa3_reg, xa4_reg, xa5_reg, xa6_reg, xa7_reg;
reg[9:0] addsub1a_comp,addsub2a_comp,addsub3a_comp,addsub4a_comp; reg[9:0] addsub1a_comp,addsub2a_comp,addsub3a_comp,addsub4a_comp;
reg[10:0] add_sub1a,add_sub2a,add_sub3a,add_sub4a; reg[10:0] add_sub1a,add_sub2a,add_sub3a,add_sub4a;
reg save_sign1a, save_sign2a, save_sign3a, save_sign4a; reg save_sign1a, save_sign2a, save_sign3a, save_sign4a;
reg[17:0] p1a,p2a,p3a,p4a; reg[17:0] p1a,p2a,p3a,p4a;
...@@ -384,15 +385,22 @@ always @ (negedge clk) ...@@ -384,15 +385,22 @@ always @ (negedge clk)
// 9th clk for registering shifted input and 10th clk for add_sub // 9th clk for registering shifted input and 10th clk for add_sub
// to synchronize the i value to the add_sub value, i value is incremented // to synchronize the i value to the add_sub value, i value is incremented
// only after 10 clks // only after 10 clks
// Adding these wires to get rid of the MSB that is always 0
wire [10:0] addsub1a_comp_w = add_sub1a[10]? (-add_sub1a) : add_sub1a;
wire [10:0] addsub2a_comp_w = add_sub2a[10]? (-add_sub2a) : add_sub2a;
wire [10:0] addsub3a_comp_w = add_sub3a[10]? (-add_sub3a) : add_sub3a;
wire [10:0] addsub4a_comp_w = add_sub4a[10]? (-add_sub4a) : add_sub4a;
always @ (negedge clk) begin always @ (negedge clk) begin
save_sign1a <= add_sub1a[10]; save_sign1a <= add_sub1a[10];
save_sign2a <= add_sub2a[10]; save_sign2a <= add_sub2a[10];
save_sign3a <= add_sub3a[10]; save_sign3a <= add_sub3a[10];
save_sign4a <= add_sub4a[10]; save_sign4a <= add_sub4a[10];
addsub1a_comp <= add_sub1a[10]? (-add_sub1a) : add_sub1a; addsub1a_comp <= addsub1a_comp_w[9:0]; //add_sub1a[10]? (-add_sub1a) : add_sub1a;
addsub2a_comp <= add_sub2a[10]? (-add_sub2a) : add_sub2a; addsub2a_comp <= addsub2a_comp_w[9:0]; //add_sub2a[10]? (-add_sub2a) : add_sub2a;
addsub3a_comp <= add_sub3a[10]? (-add_sub3a) : add_sub3a; addsub3a_comp <= addsub3a_comp_w[9:0]; //add_sub3a[10]? (-add_sub3a) : add_sub3a;
addsub4a_comp <= add_sub4a[10]? (-add_sub4a) : add_sub4a; addsub4a_comp <= addsub4a_comp_w[9:0]; //add_sub4a[10]? (-add_sub4a) : add_sub4a;
end end
assign p1a_all = addsub1a_comp * memory1a[15:0]; assign p1a_all = addsub1a_comp * memory1a[15:0];
...@@ -504,7 +512,7 @@ wire sxregs; ...@@ -504,7 +512,7 @@ wire sxregs;
wire sxregs_d8; wire sxregs_d8;
reg enable_toggle; reg enable_toggle;
reg en_started; reg en_started;
wire disdv;
SRL16 i_endv (.Q(endv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(start)); // dly=14+1 SRL16 i_endv (.Q(endv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(start)); // dly=14+1
SRL16 i_disdv (.Q(disdv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(rd_cntr[5:0]==6'h3f)); // dly=14+1 SRL16 i_disdv (.Q(disdv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(rd_cntr[5:0]==6'h3f)); // dly=14+1
...@@ -621,6 +629,11 @@ always @ (posedge clk) ...@@ -621,6 +629,11 @@ always @ (posedge clk)
add_sub4b <= ({xb4_reg[15],xb4_reg[15:0]} - {xb3_reg[15],xb3_reg[15:0]}); add_sub4b <= ({xb4_reg[15],xb4_reg[15:0]} - {xb3_reg[15],xb3_reg[15:0]});
end end
// Adding these wires to get rid of the MSB that is always 0
wire [16:0] addsub1b_comp_w = add_sub1b[16]? (-add_sub1b) : add_sub1b;
wire [16:0] addsub2b_comp_w = add_sub2b[16]? (-add_sub2b) : add_sub2b;
wire [16:0] addsub3b_comp_w = add_sub3b[16]? (-add_sub3b) : add_sub3b;
wire [16:0] addsub4b_comp_w = add_sub4b[16]? (-add_sub4b) : add_sub4b;
always @ (posedge clk) begin always @ (posedge clk) begin
// save_sign1b <= add_sub1b[10]; // save_sign1b <= add_sub1b[10];
...@@ -635,21 +648,26 @@ always @ (posedge clk) begin ...@@ -635,21 +648,26 @@ always @ (posedge clk) begin
save_sign2b <= add_sub2b[16]; save_sign2b <= add_sub2b[16];
save_sign3b <= add_sub3b[16]; save_sign3b <= add_sub3b[16];
save_sign4b <= add_sub4b[16]; save_sign4b <= add_sub4b[16];
addsub1b_comp <= add_sub1b[16]? (-add_sub1b) : add_sub1b; addsub1b_comp <= addsub1b_comp_w[15:0]; // add_sub1b[16]? (-add_sub1b) : add_sub1b;
addsub2b_comp <= add_sub2b[16]? (-add_sub2b) : add_sub2b; addsub2b_comp <= addsub2b_comp_w[15:0]; // add_sub2b[16]? (-add_sub2b) : add_sub2b;
addsub3b_comp <= add_sub3b[16]? (-add_sub3b) : add_sub3b; addsub3b_comp <= addsub3b_comp_w[15:0]; // add_sub3b[16]? (-add_sub3b) : add_sub3b;
addsub4b_comp <= add_sub4b[16]? (-add_sub4b) : add_sub4b; addsub4b_comp <= addsub4b_comp_w[15:0]; // add_sub4b[16]? (-add_sub4b) : add_sub4b;
end end
// assign p1b_all = addsub1b_comp * memory1a[15:0]; // assign p1b_all = addsub1b_comp * memory1a[15:0];
// assign p2b_all = addsub2b_comp * memory2a[15:0]; // assign p2b_all = addsub2b_comp * memory2a[15:0];
// assign p3b_all = addsub3b_comp * memory3a[15:0]; // assign p3b_all = addsub3b_comp * memory3a[15:0];
// assign p4b_all = addsub4b_comp * memory4a[15:0]; // assign p4b_all = addsub4b_comp * memory4a[15:0];
assign p1b_all = addsub1b_comp[15:0] * memory1a[15:0]; ///AF2015:
assign p2b_all = addsub2b_comp[15:0] * memory2a[15:0]; // assign p1b_all = addsub1b_comp[15:0] * memory1a[15:0];
assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0]; // assign p2b_all = addsub2b_comp[15:0] * memory2a[15:0];
assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0]; // assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0];
// assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0];
assign p1b_all = addsub1b_comp * memory1a;
assign p2b_all = addsub2b_comp * memory2a;
assign p3b_all = addsub3b_comp * memory3a;
assign p4b_all = addsub4b_comp * memory4a;
always @ (posedge clk) always @ (posedge clk)
begin begin
......
control/camsync.v
View file @ d6e9be6b
...@@ -119,7 +119,7 @@ module camsync (sclk, // @negedge ...@@ -119,7 +119,7 @@ module camsync (sclk, // @negedge
reg [31:0] restart_cntr; // restart period counter reg [31:0] restart_cntr; // restart period counter
reg [1:0] restart_cntr_run; // restart counter running reg [1:0] restart_cntr_run; // restart counter running
wire restart; // restart out sync wire restart; // restart out sync
reg [8:0] out_pulse_cntr; ///AF: reg [8:0] out_pulse_cntr;
reg trigger_condition; // GPIO input trigger condition met reg trigger_condition; // GPIO input trigger condition met
reg trigger_condition_d; // GPIO input trigger condition met, delayed (for edge detection) reg trigger_condition_d; // GPIO input trigger condition met, delayed (for edge detection)
reg trigger_condition_filtered; // trigger condition filtered reg trigger_condition_filtered; // trigger condition filtered
...@@ -140,7 +140,7 @@ module camsync (sclk, // @negedge ...@@ -140,7 +140,7 @@ module camsync (sclk, // @negedge
wire pre_start_out_pulse; wire pre_start_out_pulse;
reg start_out_pulse; /// start generation of output pulse. In internal trigger mode uses delay counter, in external - no delay reg start_out_pulse; /// start generation of output pulse. In internal trigger mode uses delay counter, in external - no delay
reg pre_start; ///AF: reg pre_start;
reg [31:0] pre_period; reg [31:0] pre_period;
reg [ 7:0] bit_length='hff; /// Output pulse duration or bit duration in timestamp mode reg [ 7:0] bit_length='hff; /// Output pulse duration or bit duration in timestamp mode
/// input will be filtered with (bit_length>>2) duration /// input will be filtered with (bit_length>>2) duration
...@@ -228,7 +228,7 @@ module camsync (sclk, // @negedge ...@@ -228,7 +228,7 @@ module camsync (sclk, // @negedge
// if (wen[3]) repeat_period[31:0] <= did[31:0]; // if (wen[3]) repeat_period[31:0] <= did[31:0];
if (wen[3]) pre_period[31:0] <= did[31:0]; if (wen[3]) pre_period[31:0] <= did[31:0];
if (wen[3]) high_zero = did[31:8]==24'b0; if (wen[3]) high_zero <= did[31:8]==24'b0;
// start <= wen[3] && (did[31:0]!=32'h0); // start <= wen[3] && (did[31:0]!=32'h0);
......
control/clkios353.v
View file @ d6e9be6b
...@@ -45,7 +45,7 @@ module dcm333( ...@@ -45,7 +45,7 @@ module dcm333(
output xclk; output xclk;
output SDCLK, SDNCLK; output SDCLK, SDNCLK;
input [1:0] phsel; input [1:0] phsel;
input sdcl_fb; input sdcl_fb; // SuppressThisWarning Veditor UNUSED - was designed to use external pin sync (maybe still use it?)
input dcm_rst, dcm_incdec, dcm_en, dcm_clk; input dcm_rst, dcm_incdec, dcm_en, dcm_clk;
output dcm_done; output dcm_done;
......
control/cmd_sequencer.v
View file @ d6e9be6b
...@@ -160,7 +160,7 @@ FD_1 i_initialized ( .Q(initialized), .C(sclk), .D(por[1] && ( initialized || (r ...@@ -160,7 +160,7 @@ FD_1 i_initialized ( .Q(initialized), .C(sclk), .D(por[1] && ( initialized || (r
we_fifo_wp <= wen_d[1] || wpage0_inc; we_fifo_wp <= wen_d[1] || wpage0_inc;
if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0]; if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 7'h0:(fifo_wr_pointers_outw_r[5:0]+1); if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri
// command seq fifo (RAMB16_S9_S18) // command seq fifo (RAMB16_S9_S18)
......
control/dma_fifo353.v
View file @ d6e9be6b
...@@ -131,7 +131,7 @@ module dma_fifo_sync ( clk, // system clock, 120MHz? (currentle negedge used) ...@@ -131,7 +131,7 @@ module dma_fifo_sync ( clk, // system clock, 120MHz? (currentle negedge used)
burst_start_sync[1:0] <= {burst_start_sync[0],~first_four_r[2] & first_four_r[1]}; burst_start_sync[1:0] <= {burst_start_sync[0],~first_four_r[2] & first_four_r[1]};
first_four_r[2:0]={first_four_r[1:0],first_four}; first_four_r[2:0] <= {first_four_r[1:0],first_four};
empties[3:0] <= {4{!rst && (infifo[9:0]==10'h0) && !dreq && !dack_r[1]}} & {empties[2:0],1'b1}; empties[3:0] <= {4{!rst && (infifo[9:0]==10'h0) && !dreq && !dack_r[1]}} & {empties[2:0],1'b1};
......
control/i2c_writeonly.v
View file @ d6e9be6b
...@@ -201,8 +201,8 @@ module i2c_writeonly (sclk, // @negedge ...@@ -201,8 +201,8 @@ module i2c_writeonly (sclk, // @negedge
bytes_cmd <= wen_d[0] && is_ctl && di_1[11]; bytes_cmd <= wen_d[0] && is_ctl && di_1[11];
dly_cmd <= wen_d[0] && is_ctl && di_1[ 8]; dly_cmd <= wen_d[0] && is_ctl && di_1[ 8];
// setting control parameters // setting control parameters
if (bytes_cmd) i2c_bytes[1:0]=di_2[10:9]; if (bytes_cmd) i2c_bytes[1:0] <= di_2[10:9];
if (dly_cmd) i2c_dly[7:0] =di_2[ 7:0]; if (dly_cmd) i2c_dly[7:0] <= di_2[ 7:0];
if (reset_cmd || (run_cmd && !di_2[12])) i2c_enrun <= 1'b0; if (reset_cmd || (run_cmd && !di_2[12])) i2c_enrun <= 1'b0;
else if (run_cmd && di_2[12]) i2c_enrun <= 1'b1; else if (run_cmd && di_2[12]) i2c_enrun <= 1'b1;
// write pointer memory // write pointer memory
...@@ -220,7 +220,7 @@ module i2c_writeonly (sclk, // @negedge ...@@ -220,7 +220,7 @@ module i2c_writeonly (sclk, // @negedge
we_fifo_wp <= wen_d[1] || wpage0_inc; we_fifo_wp <= wen_d[1] || wpage0_inc;
if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0]; if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 7'h0:(fifo_wr_pointers_outw_r[5:0]+1); if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri
// command i2c fifo (RAMB16_S9_S18) // command i2c fifo (RAMB16_S9_S18)
......
control/interrupts_vector333.v
View file @ d6e9be6b
...@@ -55,7 +55,7 @@ module interrupts_vector(sclk, // @negedge ...@@ -55,7 +55,7 @@ module interrupts_vector(sclk, // @negedge
wire [15:0] irq_insa; wire [15:0] irq_insa;
reg [15:0] irq_insb; reg [15:0] irq_insb;
reg [15:0] irq_insc; //single cycle sync interrupt request. reg [15:0] irq_insc; //single cycle sync interrupt request.
wire [15:0] irq_rst; ///AF: wire [15:0] irq_rst;
reg rst_rqs, en_rqs, dis_rqs, pre_set_irqv, set_irqv; reg rst_rqs, en_rqs, dis_rqs, pre_set_irqv, set_irqv;
reg [ 3:0] irqv_a; // irq vectors table write address reg [ 3:0] irqv_a; // irq vectors table write address
reg [ 7:0] irqv_d; // irq vectors table write data reg [ 7:0] irqv_d; // irq vectors table write data
...@@ -190,7 +190,7 @@ module interrupts_vector(sclk, // @negedge ...@@ -190,7 +190,7 @@ module interrupts_vector(sclk, // @negedge
FD_1 i_irq_um_15 (.C(sclk), .D(~(rst_rq[15]) & (irq_insc[15] | irq_um[15])), .Q(irq_um[15])); FD_1 i_irq_um_15 (.C(sclk), .D(~(rst_rq[15]) & (irq_insc[15] | irq_um[15])), .Q(irq_um[15]));
myRAM16X8D_1 i_vecttab (.D(irqv_d[7:0]), .WE(set_irqv), .clk(sclk), .AW(irqv_a[3:0]), .AR(irqn_r[3:0]), .QR(irqv[7:0])); myRAM16X8D_1 i_vecttab (.D(irqv_d[7:0]), .WE(set_irqv), .clk(sclk), .AW(irqv_a[3:0]), .AR(irqn_r[3:0]), .QR(irqv[7:0]), .QW());
always @ (negedge sclk) begin always @ (negedge sclk) begin
if (pre_wen) did[15:0] <= di[15:0]; if (pre_wen) did[15:0] <= di[15:0];
...@@ -208,8 +208,8 @@ module interrupts_vector(sclk, // @negedge ...@@ -208,8 +208,8 @@ module interrupts_vector(sclk, // @negedge
set_irqv <= pre_set_irqv; set_irqv <= pre_set_irqv;
if (pre_set_irqv) irqv_a[3:0] <= did[11:8]; if (pre_set_irqv) irqv_a[3:0] <= did[11:8];
if (pre_set_irqv) irqv_d[7:0] <= did[ 7:0]; if (pre_set_irqv) irqv_d[7:0] <= did[ 7:0];
rst_rq[15:0] <= ({15{rst_rqs}} & did[15:0]) | rst_rq_inta[15:0]; rst_rq[15:0] <= ({16{rst_rqs}} & did[15:0]) | rst_rq_inta[15:0];
dis_rq[15:0] <= ({15{dis_rqs}} & did[15:0]); dis_rq[15:0] <= ({16{dis_rqs}} & did[15:0]);
// en_rq [15:0] <= ({15{ en_rqs}} & did[15:0]); // en_rq [15:0] <= ({15{ en_rqs}} & did[15:0]);
inta_s[5:0] <= {inta_s[4:0], inta}; inta_s[5:0] <= {inta_s[4:0], inta};
......
control/ioports353.v
View file @ d6e9be6b
...@@ -539,10 +539,15 @@ module dqs2 (c0,/*c90,*/c270, ...@@ -539,10 +539,15 @@ module dqs2 (c0,/*c90,*/c270,
input c0,/*c90,*/c270,t; input c0,/*c90,*/c270,t;
inout UDQS, LDQS; inout UDQS, LDQS;
output udqsr90,ldqsr90,udqsr270,ldqsr270; output udqsr90,ldqsr90,udqsr270,ldqsr270;
wire t0,t1,t2,tr; wire t0,t1,tr;
///AF: wire t2;
FD_1 #(.INIT(1'b1)) i_t0 (.C(c0),.D(t),.Q(t0)); FD_1 #(.INIT(1'b1)) i_t0 (.C(c0),.D(t),.Q(t0));
FD #(.INIT(1'b1)) i_t1 (.C(c0),.D(t0),.Q(t1)); FD #(.INIT(1'b1)) i_t1 (.C(c0),.D(t0),.Q(t1));
FD #(.INIT(1'b1)) i_t2 (.C(c270),.D(t0),.Q(t2)); ///AF: FD #(.INIT(1'b1)) i_t2 (.C(c270),.D(t0),.Q(t2));
assign tr= t1;
dqs2_0 i_dqsu(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({udqsr270,udqsr90}),.dq(UDQS));
dqs2_0 i_dqsl(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({ldqsr270,ldqsr90}),.dq(LDQS));
endmodule endmodule
module dqs2_0(c0,/*c90,*/c270,t,q,dq); module dqs2_0(c0,/*c90,*/c270,t,q,dq);
...@@ -563,7 +568,7 @@ module dqs2_0(c0,/*c90,*/c270,t,q,dq); ...@@ -563,7 +568,7 @@ module dqs2_0(c0,/*c90,*/c270,t,q,dq);
// as in IFDDRCPE.v // as in IFDDRCPE.v
FDCPE_1 #(.INIT(1'b1)) i_q0 (.C(c270), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0])); FDCPE_1 #(.INIT(1'b0)) i_q0 (.C(c270), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0]));
FDCPE i_q1 (.C(c270),.CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[1])); FDCPE i_q1 (.C(c270),.CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[1]));
// synthesis attribute IOB of i_q0 is "TRUE" // synthesis attribute IOB of i_q0 is "TRUE"
// synthesis attribute IOB of i_q1 is "TRUE" // synthesis attribute IOB of i_q1 is "TRUE"
...@@ -577,7 +582,7 @@ endmodule ...@@ -577,7 +582,7 @@ endmodule
module sddrdm(c0,/*c90,*/c270,d,dq); module sddrdm(c0,/*c90,*/c270,d,dq);
input c0,/*c90,*/c270; input c0,/*c90,*/c270;
input [1:0] d; input [1:0] d;
inout dq; inout dq; //SuppressThisWarning Veditor UNUSED
sddrdm0 i_dq (.c0(c0),/*.c90(c90),*/.c270(c270),.d(d),.dq(dq)); sddrdm0 i_dq (.c0(c0),/*.c90(c90),*/.c270(c270),.d(d),.dq(dq));
// s--ynthesis attribute KEEP_HIERARCHY of i_dq is "TRUE" // s--ynthesis attribute KEEP_HIERARCHY of i_dq is "TRUE"
endmodule endmodule
......
control/rtc353.v
View file @ d6e9be6b
...@@ -260,7 +260,7 @@ module timestamp353( mclk, // system clock (negedge) ...@@ -260,7 +260,7 @@ module timestamp353( mclk, // system clock (negedge)
else if (hacti && !hact_d) vact_pend <= 1'b0; else if (hacti && !hact_d) vact_pend <= 1'b0;
if (hacti && !hact_d) odd_line <= !vact_pend && !odd_line; if (hacti && !hact_d) odd_line <= !vact_pend && !odd_line;
// if (hacti && !hact_d) line[3:0] <= vact_pend?4'h1:{line[2:0],1'b0}; // if (hacti && !hact_d) line[3:0] <= vact_pend?4'h1:{line[2:0],1'b0};
if (hacti && !hact_d) line[2:0] <= vact_pend?4'h1:{line[1:0],1'b0}; if (hacti && !hact_d) line[2:0] <= vact_pend ? 3'h1 : {line[1:0],1'b0};
if (hacti && !hact_d) ts_line <= tsmode[1]? (vact_pend || line[0] ) : (!vact_pend && (line[1] || line[2])); if (hacti && !hact_d) ts_line <= tsmode[1]? (vact_pend || line[0] ) : (!vact_pend && (line[1] || line[2]));
...@@ -282,9 +282,9 @@ module timestamp353( mclk, // system clock (negedge) ...@@ -282,9 +282,9 @@ module timestamp353( mclk, // system clock (negedge)
// else ts_data[25:0]<= 16'h0; // else ts_data[25:0]<= 16'h0;
ts_active_r <= ts_active; ts_active_r <= ts_active;
ts_line_r <= ts_line; ts_line_r <= ts_line;
if (ts_active_r) ts_data[25:0]<= {ts_data[24:0],1'b0}; if (ts_active_r) ts_data[25:0] <= {ts_data[24:0],1'b0};
else if (ts_line_r) ts_data[25:0]<= odd_line?sec[31:6]:{sec[5:0],usec[19:0]}; else if (ts_line_r) ts_data[25:0] <= odd_line?sec[31:6]:{sec[5:0],usec[19:0]};
else ts_data[25:0]<= 16'h0; else ts_data[25:0] <= 26'h0;
end end
endmodule endmodule
......
extras/10364.v
View file @ d6e9be6b
...@@ -135,7 +135,7 @@ FDCE_1 i_enable_mot_clk (.C(clk),.CE(we_ctl && di_d[1]),.CLR(1'b0), ...@@ -135,7 +135,7 @@ FDCE_1 i_enable_mot_clk (.C(clk),.CE(we_ctl && di_d[1]),.CLR(1'b0),
// reset at simulation // reset at simulation
assign sequence_next[1:0]=sequence[1:0]+1; assign sequence_next[1:0]=sequence[1:0]+1;
assign sequence_next[3:2]=(sequence[1:0]==3'b11)?((sequence[3:2]==3'b11)?2'b01:(sequence[3:2]+1)):sequence[3:2]; assign sequence_next[3:2]=(sequence[1:0]==2'b11)?((sequence[3:2]==2'b11)?2'b01:(sequence[3:2]+1)):sequence[3:2];
FD i_sequence_0(.C(xclk),.D(sequence_next[0]), .Q(sequence[0])); FD i_sequence_0(.C(xclk),.D(sequence_next[0]), .Q(sequence[0]));
FD i_sequence_1(.C(xclk),.D(sequence_next[1]), .Q(sequence[1])); FD i_sequence_1(.C(xclk),.D(sequence_next[1]), .Q(sequence[1]));
FD i_sequence_2(.C(xclk),.D(sequence_next[2]), .Q(sequence[2])); FD i_sequence_2(.C(xclk),.D(sequence_next[2]), .Q(sequence[2]));
...@@ -342,6 +342,9 @@ endmodule ...@@ -342,6 +342,9 @@ endmodule
/// Combine old (freom register file) /new encoded periods, inc/dec pulses to prepare a 6-bit (partial) index for a RAM table. /// Combine old (freom register file) /new encoded periods, inc/dec pulses to prepare a 6-bit (partial) index for a RAM table.
/// Together with the position error (another 6 bits) the full 12-bit undex provides 1 4-bit PWM code from the RAM table /// Together with the position error (another 6 bits) the full 12-bit undex provides 1 4-bit PWM code from the RAM table
/// Updates direction immediately, period - if inc_dec or when new period > saved period (so it will be updated even if the motor is stopped) /// Updates direction immediately, period - if inc_dec or when new period > saved period (so it will be updated even if the motor is stopped)
/// AF2015: Replace eith a function?
module calc_speed (clk, // posedge, 80 MHz module calc_speed (clk, // posedge, 80 MHz
en_in, // enable (just for simulation), for real - let it on even when motors are off en_in, // enable (just for simulation), for real - let it on even when motors are off
process, // increment (with limit) period process, // increment (with limit) period
...@@ -355,11 +358,11 @@ module calc_speed (clk, // posedge, 80 MHz ...@@ -355,11 +358,11 @@ module calc_speed (clk, // posedge, 80 MHz
enc_period_this // [4:0] encoded period for the register file/ table index enc_period_this // [4:0] encoded period for the register file/ table index
); );
parameter IGNORE_EN=1; parameter IGNORE_EN=1;
input clk; // posedge, 80MHz input clk; // posedge, 80MHz // SuppressThisWarning Veditor UNUSED
input en_in; // enable, 0 resets period counter - simulation only input en_in; // enable, 0 resets period counter - simulation only
input process; // increment (with limit) period input process; // increment (with limit) period // SuppressThisWarning Veditor UNUSED
input inc_dec; // encoder pulse detected input inc_dec; // encoder pulse detected
input inc; // encoder position increment input inc; // encoder position increment // SuppressThisWarning Veditor UNUSED
input dec; // encoder position decrement input dec; // encoder position decrement
input [4:0] enc_period_curr; // encoded current period (still running if !inc_dec) input [4:0] enc_period_curr; // encoded current period (still running if !inc_dec)
input dir_last; // last stored direction (from register file) input dir_last; // last stored direction (from register file)
...@@ -560,14 +563,14 @@ module motor_pwm( clk, // posedge, 80MHz ...@@ -560,14 +563,14 @@ module motor_pwm( clk, // posedge, 80MHz
output [2:0] new_pwm; // [2:0] output [2:0] new_pwm; // [2:0]
output [1:0] mot; // [1:0] - data to be copied to the motor outputs output [1:0] mot; // [1:0] - data to be copied to the motor outputs
reg [9:0] pwm_cycle_count; reg [9:0] pwm_cycle_count; /// AF2015: Seems to be a bug - 2 MSBs are never used (only 8 LSB)
reg pwm_cycle_next; reg pwm_cycle_next;
reg [3:0] pwm_delay_count; reg [3:0] pwm_delay_count; /// AF2015: Seems to be a bug - 1 MSB is never used (only 3 LSB)
reg pwm_delay_end; reg pwm_delay_end;
reg [2:0] pwm_phase; reg [2:0] pwm_phase;
wire [2:0] spreaded_phase; wire [2:0] spreaded_phase;
wire pwn_on; wire pwn_on; // SuppressThisWarning Veditor UNUSED
wire pwn_off; wire pwn_off; // SuppressThisWarning Veditor UNUSED
wire [2:0] new_pwm; wire [2:0] new_pwm;
wire stop_cmd; wire stop_cmd;
wire [3:0] pwm_diff; wire [3:0] pwm_diff;
...@@ -575,7 +578,7 @@ module motor_pwm( clk, // posedge, 80MHz ...@@ -575,7 +578,7 @@ module motor_pwm( clk, // posedge, 80MHz
assign spreaded_phase[2:0]= pwm_phase[2:0]+spread[2:0]; assign spreaded_phase[2:0]= pwm_phase[2:0]+spread[2:0];
assign pwn_on= pwm_cycle_next && (spreaded_phase == 0) && (pwm_code != 0); assign pwn_on= pwm_cycle_next && (spreaded_phase == 0) && (pwm_code != 0);
assign pwn_off=pwm_cycle_next && (spreaded_phase == pwm_code); assign pwn_off=pwm_cycle_next && (spreaded_phase == pwm_code[2:0]);
assign stop_cmd= !en || (pwm_code==8) ; assign stop_cmd= !en || (pwm_code==8) ;
assign pwm_diff[3:0]={1'b0,pwm_code[2:0]}-{1'b0,spreaded_phase[2:0]}; assign pwm_diff[3:0]={1'b0,pwm_code[2:0]}-{1'b0,spreaded_phase[2:0]};
...@@ -584,10 +587,14 @@ module motor_pwm( clk, // posedge, 80MHz ...@@ -584,10 +587,14 @@ module motor_pwm( clk, // posedge, 80MHz
assign new_pwm[2]=!en || (pwm_cycle_next? (new_pwm[1:0]!=cur_pwm[1:0]):(cur_pwm[2]&& !pwm_delay_end)); assign new_pwm[2]=!en || (pwm_cycle_next? (new_pwm[1:0]!=cur_pwm[1:0]):(cur_pwm[2]&& !pwm_delay_end));
assign mot[1:0]=(stop_cmd || new_pwm[2])? 2'b0:(new_pwm[1]?{new_pwm[0],!new_pwm[0]}:2'b11); assign mot[1:0]=(stop_cmd || new_pwm[2])? 2'b0:(new_pwm[1]?{new_pwm[0],!new_pwm[0]}:2'b11);
always @ (posedge clk) if (pre_first) begin // change these registers once per cycle of all motors always @ (posedge clk) if (pre_first) begin // change these registers once per cycle of all motors
pwm_cycle_count<= (!en || (pwm_cycle_count==0))?pwm_cycle:(pwm_cycle_count-1);
/// AF2015: pwm_cycle_count<= (!en || (pwm_cycle_count==0)) ? pwm_cycle:(pwm_cycle_count-1);
pwm_cycle_count<= (!en || (pwm_cycle_count==0)) ? {2'b0,pwm_cycle}:(pwm_cycle_count-1);
pwm_cycle_next<= en && (pwm_cycle_count==0); pwm_cycle_next<= en && (pwm_cycle_count==0);
// pwm_delay_count<= (!en || (pwm_delay_count==0))?0:(pwm_cycle_next?pwm_delay: (pwm_delay_count-1));
pwm_delay_count<= (!en || pwm_cycle_next)?pwm_delay:((pwm_delay_count==0)?0: (pwm_delay_count-1)); /// AF2015: pwm_delay_count<= (!en || pwm_cycle_next)?pwm_delay:((pwm_delay_count==0)?0: (pwm_delay_count-1));
pwm_delay_count<= (!en || pwm_cycle_next)?{1'b0,pwm_delay}:((pwm_delay_count==0)? 4'b0: (pwm_delay_count-1));
pwm_delay_end<= en && (pwm_delay_count==1); pwm_delay_end<= en && (pwm_delay_count==1);
pwm_phase<= (!en)? 0: (pwm_phase + pwm_cycle_next); // divide by 8 pwm_phase<= (!en)? 0: (pwm_phase + pwm_cycle_next); // divide by 8
end end
......
extras/imu_logger.v
View file @ d6e9be6b
...@@ -311,7 +311,7 @@ imu_timestamps i_imu_timestamps ( ...@@ -311,7 +311,7 @@ imu_timestamps i_imu_timestamps (
.ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored .ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
.ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high .ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
.dout(timestamps_rdata[15:0]));// output data .dout(timestamps_rdata[15:0]));// output data
wire [0:0] debug_state_unused; wire [0:0] debug_state_unused; // SuppressThisWarning Veditor UNUSED
rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal) rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles .bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles
.ser_di(ser_di), // rs232 (ttl) serial data in .ser_di(ser_di), // rs232 (ttl) serial data in
...@@ -415,7 +415,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge ...@@ -415,7 +415,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge
reg [3:1] chn1hot; // channels 1-hot - granted and ready, priority applied reg [3:1] chn1hot; // channels 1-hot - granted and ready, priority applied
reg rq_not_zero; // at least one channel is ready for processing (same time as chn1hot[3:0]) reg rq_not_zero; // at least one channel is ready for processing (same time as chn1hot[3:0])
reg [1:0] channel; reg [1:0] channel;
reg start; ///AF: reg start;
reg busy; reg busy;
wire wstart; wire wstart;
reg ts_en; reg ts_en;
...@@ -462,7 +462,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge ...@@ -462,7 +462,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge
channels_ready[2] & ~|channels_ready[1:0], channels_ready[2] & ~|channels_ready[1:0],
channels_ready[1] & ~channels_ready[0]}; channels_ready[1] & ~channels_ready[0]};
start <= wstart; ///AF: start <= wstart;
if ((seq_cntr[4:0]=='h1e) || rst) busy <= 1'b0; if ((seq_cntr[4:0]=='h1e) || rst) busy <= 1'b0;
else if (rq_not_zero) busy <= 1'b1; else if (rq_not_zero) busy <= 1'b1;
...@@ -765,10 +765,12 @@ module imu_spi ( sclk, // system clock, negedge ...@@ -765,10 +765,12 @@ module imu_spi ( sclk, // system clock, negedge
stall_dur[7:0] <= stall_dur_mclk[7:0]; stall_dur[7:0] <= stall_dur_mclk[7:0];
bit_duration_zero <= (bit_duration[7:0]==8'h0); bit_duration_zero <= (bit_duration[7:0]==8'h0);
clk_div[1:0]=en?(clk_div[1:0]+1):2'b0; clk_div[1:0] <= en?(clk_div[1:0]+1):2'b0;
clk_en[3:0] <= {clk_en[2:0],clk_div[1:0]==2'h3}; clk_en[3:0] <= {clk_en[2:0],clk_div[1:0]==2'h3};
if (bit_duration_zero || (bit_duration_cntr[7:0]==8'h0)) bit_duration_cntr[7:0]<=bit_duration[7:0]; if (bit_duration_zero || (bit_duration_cntr[7:0]==8'h0)) bit_duration_cntr[7:0]<=bit_duration[7:0];
else bit_duration_cntr[7:0] <= bit_duration_cntr[7:0]-1; else bit_duration_cntr[7:0] <= bit_duration_cntr[7:0]-1;
clk_en[3:0] <= {clk_en[2:0],bit_duration_cntr[7:0]==8'h3}; // change 9'h3 to enforce frequency limit clk_en[3:0] <= {clk_en[2:0],bit_duration_cntr[7:0]==8'h3}; // change 9'h3 to enforce frequency limit
end end
...@@ -795,7 +797,7 @@ module imu_spi ( sclk, // system clock, negedge ...@@ -795,7 +797,7 @@ module imu_spi ( sclk, // system clock, negedge
else if (end_spi) seq_counter[9:0] <= 10'h001; else if (end_spi) seq_counter[9:0] <= 10'h001;
else if (clk_en[3] && (seq_state[1:0]!=2'h0) && !stall) seq_counter[9:0] <= seq_counter[9:0] - 1; else if (clk_en[3] && (seq_state[1:0]!=2'h0) && !stall) seq_counter[9:0] <= seq_counter[9:0] - 1;
set_mosi_prepare <= clk_en[2] && first_prepare; set_mosi_prepare <= clk_en[2] && first_prepare;
set_mosi_spi <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && (seq_counter[9:5]!=6'h0) && !stall; // last word use zero set_mosi_spi <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && (seq_counter[9:5] != 5'h0) && !stall; // last word use zero
// no stall before the first word // no stall before the first word
if (!en) skip_stall <= 1'b0; if (!en) skip_stall <= 1'b0;
...@@ -1109,7 +1111,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal) ...@@ -1109,7 +1111,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal)
reg wait_just_pause; reg wait_just_pause;
wire wstart; wire wstart;
wire [4:0] debug; wire [4:0] debug;
reg [4:0] debug0; // {was_ts_stb, was_start, was_error, was_ser_di_1, was_ser_di_0} - once after reset reg [4:0] debug0; // {was_ts_stb, was_start, was_error, was_ser_di_1, was_ser_di_0} - once after reset // SuppressThisWarning Veditor UNUSED
assign reset_wait_pause= (restart[1] && !restart[0]) || (wait_pause && !wait_start && !ser_di); assign reset_wait_pause= (restart[1] && !restart[0]) || (wait_pause && !wait_start && !ser_di);
assign error=!ser_filt_di && last_half_bit && bit_half_end && receiving_byte; assign error=!ser_filt_di && last_half_bit && bit_half_end && receiving_byte;
assign sample_bit=shift_en && bit_half_end && !bit_cntr[0]; assign sample_bit=shift_en && bit_half_end && !bit_cntr[0];
...@@ -1161,7 +1163,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal) ...@@ -1161,7 +1163,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal)
if (ser_rst) debug0[4:0] <=5'b0; if (ser_rst) debug0[4:0] <=5'b0;
else debug0[4:0] <= debug | {ts_stb,start,error,ser_di_d,~ser_di_d}; else debug0[4:0] <= debug | {ts_stb,start,error,ser_di_d[0],~ser_di_d[0]};
end end
endmodule endmodule
...@@ -1571,7 +1573,7 @@ module imu_timestamps ( ...@@ -1571,7 +1573,7 @@ module imu_timestamps (
rq_sclk2[1] & ~rq_sclk2[0], rq_sclk2[1] & ~rq_sclk2[0],
rq_sclk2[0]}; rq_sclk2[0]};
pri_sclk_d[3:0] <= pri_sclk[3:0]; pri_sclk_d[3:0] <= pri_sclk[3:0];
proc[9:0] <= {proc[9:0], wstart}; proc[9:0] <= {proc[8:0], wstart};
if (proc[0]) wa[3:2] <= {|pri_sclk_d[3:2], pri_sclk_d[3] | pri_sclk_d[1]}; if (proc[0]) wa[3:2] <= {|pri_sclk_d[3:2], pri_sclk_d[3] | pri_sclk_d[1]};
if (proc[0]) sec_latched[31:0] <= sec[31:0]; if (proc[0]) sec_latched[31:0] <= sec[31:0];
if (proc[0]) usec_latched[19:0] <= usec[19:0]; if (proc[0]) usec_latched[19:0] <= usec[19:0];
......
extras/motors_tb.v
View file @ d6e9be6b
...@@ -7,17 +7,15 @@ module testbench(); ...@@ -7,17 +7,15 @@ module testbench();
parameter CLK2WA= 1; parameter CLK2WA= 1;
parameter WA2WD= 1; parameter WA2WD= 1;
parameter aaaa=0; ///AF: parameter aaaa=0;
parameter aaaa=1; ///AF: parameter aaaa=1;
reg sclk,xclk; reg sclk,xclk;
reg [15:0] wd; reg [15:0] wd;
reg wa; reg wa;
reg we; reg we;
wire [15:0] rd; wire [31:0] rd; // SuppressThisWarning Veditor UNUSED
// reg [1:0] encod1;
// reg [1:0] encod2;
// reg [1:0] encod3;
wire [1:0] encod1; wire [1:0] encod1;
wire [1:0] encod2; wire [1:0] encod2;
wire [1:0] encod3; wire [1:0] encod3;
...@@ -71,7 +69,7 @@ motor i_motor3 (.clk(xclk), ...@@ -71,7 +69,7 @@ motor i_motor3 (.clk(xclk),
initial begin initial begin
$dumpfile("motors.lxt"); $dumpfile("motors.lxt");
$dumpvars(0,testbench.i_three_motor_driver); $dumpvars(0,testbench.i_three_motor_driver); // SuppressThisWarning Veditor VDT_BUG
/* /*
$dumpvars(0,testbench.i_three_motor_driver.addr); $dumpvars(0,testbench.i_three_motor_driver.addr);
$dumpvars(0,testbench.i_three_motor_driver.reg_addr); $dumpvars(0,testbench.i_three_motor_driver.reg_addr);
...@@ -95,7 +93,7 @@ motor i_motor3 (.clk(xclk), ...@@ -95,7 +93,7 @@ motor i_motor3 (.clk(xclk),
$dumpvars(0,testbench.i_three_motor_driver.i_motor_pwm); $dumpvars(0,testbench.i_three_motor_driver.i_motor_pwm);
*/ */
$dumpvars(0,testbench.rd); $dumpvars(0,testbench.rd);
$dumpvars(0,testbench.i_motor1); $dumpvars(0,testbench.i_motor1); // SuppressThisWarning Veditor VDT_BUG - it is resolved
$dumpvars(0,testbench.i_motor2.position); $dumpvars(0,testbench.i_motor2.position);
$dumpvars(0,testbench.i_motor2.speed); $dumpvars(0,testbench.i_motor2.speed);
$dumpvars(0,testbench.i_motor3.position); $dumpvars(0,testbench.i_motor3.position);
...@@ -194,7 +192,7 @@ $finish; ...@@ -194,7 +192,7 @@ $finish;
task program_table; task program_table;
reg [31:0] data[0:511]; reg [31:0] data[0:511]; // SuppressThisWarning Veditor VDT_BUG - assigned in system task
integer i; integer i;
begin begin
$readmemh("motor.dat",data); $readmemh("motor.dat",data);
...@@ -216,12 +214,12 @@ module motor (clk, ...@@ -216,12 +214,12 @@ module motor (clk,
enc); enc);
parameter SAMPLE_PERIOD=100; // ns parameter SAMPLE_PERIOD=100; // ns
parameter VMAX=1000.0; /// pulses/sec parameter VMAX=1000.0; /// pulses/sec
parameter EMF= 0.5; /// part of the voltage that is caused by rotation (remaining goes to current -> force->acceleration). Not yet used parameter EMF= 0.5; /// part of the voltage that is caused by rotation (remaining goes to current -> force->acceleration). Not yet used // SuppressThisWarning Veditor UNUSED
// parameter ACCEL=10.0; /// number of VMAX/sec if full power is applied, speed==0 // parameter ACCEL=10.0; /// number of VMAX/sec if full power is applied, speed==0
parameter ACCEL=300.0; /// number of VMAX/sec if full power is applied, speed==0 parameter ACCEL=300.0; /// number of VMAX/sec if full power is applied, speed==0
// no simulation of friction yet // no simulation of friction yet
input clk; input clk; // SuppressThisWarning Veditor UNUSED
input en; input en; // SuppressThisWarning Veditor UNUSED
input [1:0] pwr; input [1:0] pwr;
output [1:0] enc; output [1:0] enc;
...@@ -229,8 +227,8 @@ module motor (clk, ...@@ -229,8 +227,8 @@ module motor (clk,
real position, position0; real position, position0;
real speed, speed0; real speed, speed0;
// time t,t0; // time t,t0;
integer itime; ///AF: integer itime;
real rtime; ///AF: real rtime;
reg [1:0] enc; reg [1:0] enc;
reg [1:0] enc_bin; reg [1:0] enc_bin;
real t,t0, dt, e,f; real t,t0, dt, e,f;
...@@ -249,10 +247,10 @@ module motor (clk, ...@@ -249,10 +247,10 @@ module motor (clk,
t=$time; t=$time;
dt=(t-t0)/1000000000; // in seconds dt=(t-t0)/1000000000; // in seconds
case (pwr) case (pwr)
0: f<=(speed>0)?-1.0:1.0; 0: f = (speed>0)?-1.0:1.0;
1: f<=1.0; 1: f = 1.0;
2: f<=-1.0; 2: f = -1.0;
3: f<=0.0; 3: f = 0.0;
endcase endcase
e=f-speed/VMAX; e=f-speed/VMAX;
speed=speed0+ACCEL*VMAX*e*dt; speed=speed0+ACCEL*VMAX*e*dt;
...@@ -261,7 +259,7 @@ module motor (clk, ...@@ -261,7 +259,7 @@ module motor (clk,
#1; #1;
// itime=sim_time; // itime=sim_time;
// rtime=sim_time; // rtime=sim_time;
enc[1:0] <= {enc_bin[1],enc_bin[1] ^ enc_bin[0]}; enc[1:0] = {enc_bin[1],enc_bin[1] ^ enc_bin[0]};
t0=t; t0=t;
speed0=speed; speed0=speed;
position0=position; position0=position;
......
general/macros353.v
View file @ d6e9be6b
...@@ -31,7 +31,11 @@ module MSRL16 (Q, A, CLK, D); ...@@ -31,7 +31,11 @@ module MSRL16 (Q, A, CLK, D);
output Q; output Q;
input [3:0] A; input [3:0] A;
input CLK, D; input CLK, D;
SRL16 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D)); `ifdef SIMULATION
SRL16_MOD #(.INVERT(1'b0)) i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`else
SRL16 i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`endif
endmodule endmodule
...@@ -39,7 +43,11 @@ module MSRL16_1 (Q, A, CLK, D); ...@@ -39,7 +43,11 @@ module MSRL16_1 (Q, A, CLK, D);
output Q; output Q;
input [3:0] A; input [3:0] A;
input CLK, D; input CLK, D;
SRL16_1 i_q(.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D)); `ifdef SIMULATION
SRL16_MOD #(.INVERT(1'b1)) i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`else
SRL16_1 i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`endif
endmodule endmodule
module myRAM_WxD_D(D,WE,clk,AW,AR,QW,QR); module myRAM_WxD_D(D,WE,clk,AW,AR,QW,QR);
...@@ -73,3 +81,43 @@ parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1; ...@@ -73,3 +81,43 @@ parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
assign QW= ram[AW]; assign QW= ram[AW];
assign QR= ram[AR]; assign QR= ram[AR];
endmodule endmodule
// Fixing Xilinx SLR16_x
module SRL16_MOD #(
parameter INIT = 16'h0000,
parameter INVERT = 0 // *_1 - invert
) (
output Q,
input A0,
input A1,
input A2,
input A3,
input CLK,
input D);
reg [15:0] data;
wire clk_;
wire [3:0] a = {A3, A2, A1, A0};
assign Q = (data == 16'h0) ? 1'b0 :
((data == 16'hffff) ? 1'b1 : data[a]);
assign clk_ = INVERT? (~CLK) : CLK;
initial
begin
assign data = INIT;
while (clk_ === 1'b1 || clk_ === 1'bX)
#10;
deassign data;
end
always @(posedge clk_)
begin
{data[15:0]} <= #100 {data[14:0], D};
end
endmodule
imu_sim2_include.vh 0 → 100644
View file @ d6e9be6b
/*******************************************************************************
* Include file: imu_sim2_include.vh
* Date:2015-07-26
* Author: Andrey Filippov
* Description: Moved here all simulation for IMU logger
*
* Copyright (c) 2015 Elphel, Inc .
* imu_sim2_include.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* imu_sim_include2.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`ifdef TEST_IMU
cpu_wr(X313_WA_IOPINS, X313_WA_IOPINS_EN_IMU_OUT); // 'hc0000000;
/*
reg we_config_imu; // bits 1:0, 2 - enable slot[1:0]
reg we_config_gps; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_rst; // bit 16, 17 - enable - reset modules
*/
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
// cpu_wr(X313_WA_IMU_DATA, 'h3e695); // configure channels and reset // gps timestamp from 1sec input, positive
// cpu_wr(X313_WA_IMU_DATA, 'h3e6b5); // configure channels and reset // gps timestamp from 1sec input, negative
// cpu_wr(X313_WA_IMU_DATA, 'h3e6d5); // configure channels and reset // gps timestamp after pause
// cpu_wr(X313_WA_IMU_DATA, 'h3e6f5); // configure channels and reset // gps timestamp at "$" start
cpu_wr(X313_WA_IMU_DATA, 'h43e6f5); // configure channels and reset // gps timestamp at "$" start, reset configure_debug
cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration)
cpu_wr(X313_WA_IMU_DATA, 'h8007); // reset rs232 by 1 in MSB
cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration)
cpu_wr(X313_WA_IMU_DATA, 'h0007); // serial speed 8 cycles (period = 32 CLK0 cycles)
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h20000); // remove reset
// encode 4 sentences
/*
$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
*/
cpu_wr(X313_WA_IMU_CTRL, 'h20); // format write
// just ($GP)RMC, GGA, GSA and VTG
cpu_wr(X313_WA_IMU_DATA, 'h6); //
cpu_wr(X313_WA_IMU_DATA, 'hf); //
cpu_wr(X313_WA_IMU_DATA, 'he); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h9); //
cpu_wr(X313_WA_IMU_DATA, 'h7); //
cpu_wr(X313_WA_IMU_DATA, 'h6); //
cpu_wr(X313_WA_IMU_DATA, 'hb); //
cpu_wr(X313_WA_IMU_DATA, 'h1); //
cpu_wr(X313_WA_IMU_DATA, 'hc); //
cpu_wr(X313_WA_IMU_DATA, 'hf); //
cpu_wr(X313_WA_IMU_DATA, 'h9); //
cpu_wr(X313_WA_IMU_DATA, 'h8); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h30); // first format
//$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
//0101010 000 : 'hb 'h2a 'h04 'h0
// cpu_wr(X313_WA_IMU_DATA, 'h0b); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h0a); // testing - made 1 shorter than actual
cpu_wr(X313_WA_IMU_DATA, 'h2a); //
cpu_wr(X313_WA_IMU_DATA, 'h04); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h34); // second format
//$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
//0010 1000 0101 0 : 'h0e 'h14 'h0a 'h0
cpu_wr(X313_WA_IMU_DATA, 'h0e); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h14); //
cpu_wr(X313_WA_IMU_DATA, 'h0a); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h38); // third format
//$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
//01000000 00000000 00 : 'h11 'h01 'h00 'h0
cpu_wr(X313_WA_IMU_DATA, 'h11); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h01); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h3c); // fourth format
//$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
//00101010 1 : 'h08 'haa 'h00 'h0
cpu_wr(X313_WA_IMU_DATA, 'h08); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'haa); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_CTRL, 4); // select register number 4
cpu_wr(X313_WA_IMU_DATA, 'h10); // x gyro low
cpu_wr(X313_WA_IMU_DATA, 'h12); // x gyro high
cpu_wr(X313_WA_IMU_DATA, 'h14); //
cpu_wr(X313_WA_IMU_DATA, 'h16); //
cpu_wr(X313_WA_IMU_DATA, 'h18); //
cpu_wr(X313_WA_IMU_DATA, 'h1a); //
cpu_wr(X313_WA_IMU_DATA, 'h1c); // x accel low
cpu_wr(X313_WA_IMU_DATA, 'h1e); //
cpu_wr(X313_WA_IMU_DATA, 'h20); //
cpu_wr(X313_WA_IMU_DATA, 'h22); //
cpu_wr(X313_WA_IMU_DATA, 'h24); //
cpu_wr(X313_WA_IMU_DATA, 'h26); // z accel high
cpu_wr(X313_WA_IMU_DATA, 'h40); // x delta ang low
cpu_wr(X313_WA_IMU_DATA, 'h42); // x delta ang high
cpu_wr(X313_WA_IMU_DATA, 'h44); //
cpu_wr(X313_WA_IMU_DATA, 'h46); //
cpu_wr(X313_WA_IMU_DATA, 'h48); //
cpu_wr(X313_WA_IMU_DATA, 'h4a); //
cpu_wr(X313_WA_IMU_DATA, 'h4c); // x delta vel low
cpu_wr(X313_WA_IMU_DATA, 'h4e); //
cpu_wr(X313_WA_IMU_DATA, 'h50); //
cpu_wr(X313_WA_IMU_DATA, 'h52); //
cpu_wr(X313_WA_IMU_DATA, 'h54); //
cpu_wr(X313_WA_IMU_DATA, 'h56); // z delta vel high
cpu_wr(X313_WA_IMU_DATA, 'h0e); // temperature
cpu_wr(X313_WA_IMU_DATA, 'h70); // time m/s
cpu_wr(X313_WA_IMU_DATA, 'h72); // time d/h
cpu_wr(X313_WA_IMU_DATA, 'h74); // time y/m
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, 0); // reset IMU
cpu_wr(X313_WA_IMU_DATA, 0); // reset bit counter
#1000;
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION); // set bit counter (clock frequency divider)
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_PERIOD); // set period
// set "odometer" message
cpu_wr(X313_WA_IMU_CTRL, 'h40); // select start of message
cpu_wr(X313_WA_IMU_DATA, 'h01234567); // Message first 4 bytes
cpu_wr(X313_WA_IMU_DATA, 'h12345678); //next
cpu_wr(X313_WA_IMU_DATA, 'h23456789); //next
cpu_wr(X313_WA_IMU_DATA, 'h3456789a); //next
cpu_wr(X313_WA_IMU_DATA, 'h456789ab); //next
cpu_wr(X313_WA_IMU_DATA, 'h56789abc); //next
cpu_wr(X313_WA_IMU_DATA, 'h6789abcd); //next
cpu_wr(X313_WA_IMU_DATA, 'h789abcde); //next
cpu_wr(X313_WA_IMU_DATA, 'h89abcdef); //next
cpu_wr(X313_WA_IMU_DATA, 'h9abcdef0); //next
cpu_wr(X313_WA_IMU_DATA, 'habcdef01); //next
cpu_wr(X313_WA_IMU_DATA, 'hbcdef012); //next
cpu_wr(X313_WA_IMU_DATA, 'hcdef0123); //next
cpu_wr(X313_WA_IMU_DATA, 'hdef01234); //next
// extra 8 bytes - will not be logged
cpu_wr(X313_WA_IMU_DATA, 'hef012345); //next
cpu_wr(X313_WA_IMU_DATA, 'hf0123456); //next
// cpu_wr(1,32'h00000); // disable and reset dma
// cpu_wr(1,32'h20000); // enable DMA channel 1
cpu_wr(1,32'h00024); // disable and reset dma (both channels)
cpu_wr(1,32'h00028); // enable DMA channel 1
// cpu_wr(X313_WA_IMU_DATA, 1); // set period
/*
parameter X313_WA_IMU_DATA= 'h7e;
parameter X313_WA_IMU_CTRL= 'h7f;
parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready
*/
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
`endif
\ No newline at end of file
imu_sim_include.vh 0 → 100644
View file @ d6e9be6b
/*******************************************************************************
* Include file: imu_sim_include.vh
* Date:2015-07-26
* Author: Andrey Filippov
* Description: Moved here all simulation for IMU logger
*
* Copyright (c) 2015 Elphel, Inc .
* imu_sim_include.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* imu_sim_include.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
#250000;
dma_en(0,1);
`ifdef TEST_IMU
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA = 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
`endif
#480000;
//#480000;
$finish;
`ifdef TEST_IMU
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
`endif
$finish;
//#250000;
// dma_en(0,1);
//#480000;
`ifdef TEST_IMU
dma_en(0,1);
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA = 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
`endif
#480000;
$finish;
`ifdef TEST_IMU
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
`endif
$finish;
//#250000;
// dma_en(0,1);
//#480000;
#200000;
$finish;
\ No newline at end of file
imu_sim_init_include.vh 0 → 100644
View file @ d6e9be6b
/*******************************************************************************
* Include file: imu_sim_init_include.vh
* Date:2015-07-26
* Author: Andrey Filippov
* Description: Moved here all simulation for IMU logger
*
* Copyright (c) 2015 Elphel, Inc .
* imu_sim_init_include.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* imu_sim_init_include.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`ifdef TEST_IMU
//wire [11:0] EXT; // bidirectional
wire IMU_SCL=EXT[0];
wire IMU_SDA=EXT[1];
wire IMU_MOSI=EXT[2];
wire IMU_MISO=EXT[3]; //SuppressThisWarning Veditor UNUSED
reg IMU_EN;
wire IMU_ACTIVE;
wire IMU_NMOSI=!IMU_MOSI;
wire [5:1] IMU_TAPS;
reg IMU_LATE_ACKN;
reg IMU_SCLK;
reg IMU_MOSI_REVA;
reg IMU_103695REVA;
wire IMU_MOSI_OUT;
wire IMU_SCLK_OUT;
assign IMU_MOSI_OUT=IMU_103695REVA?IMU_MOSI_REVA:IMU_MOSI;
assign IMU_SCLK_OUT=IMU_103695REVA?(IMU_SCLK):IMU_SCL;
always @ (posedge IMU_SDA) begin
IMU_EN<=IMU_MOSI;
end
wire IMU_CS=IMU_103695REVA?!IMU_ACTIVE:!(IMU_EN &&IMU_SDA);
reg IMU_MOSI_D;
always @ (posedge IMU_SCLK_OUT) begin
// IMU_MOSI_D<=IMU_MOSI;
IMU_MOSI_D<=IMU_MOSI_OUT;
end
reg [15:0] IMU_LOOPBACK;
always @ (negedge IMU_SCLK_OUT) begin
if (!IMU_CS) IMU_LOOPBACK[15:0]<={IMU_LOOPBACK[14:0],IMU_MOSI_D};
end
assign EXT[3]=IMU_CS?IMU_DATA_READY:IMU_LOOPBACK[15];
PULLUP i_IMU_SDA (.O(IMU_SDA));
PULLUP i_IMU_SCL (.O(IMU_SCL));
initial begin
SERIAL_DATA_FD=$fopen("gps_data.dat","r");
end
always begin
#(IMU_READY_PERIOD-IMU_NREADY_DURATION) IMU_DATA_READY=1'b0;
#(IMU_NREADY_DURATION) IMU_DATA_READY=1'b1;
end
assign EXT[4]=SERIAL_BIT;
assign EXT[5]=GPS1SEC;
assign EXT[6]=ODOMETER_PULSE;
oneshot i_oneshot (.trigger(IMU_NMOSI),
.out(IMU_ACTIVE));
dly5taps i_dly5taps (.dly_in(IMU_NMOSI),
.dly_out(IMU_TAPS[5:1]));
always @ (negedge IMU_ACTIVE or posedge IMU_TAPS[5]) if (!IMU_ACTIVE) IMU_LATE_ACKN<= 1'b0; else IMU_LATE_ACKN<= 1'b1;
always @ (negedge IMU_LATE_ACKN or posedge IMU_TAPS[4]) if (!IMU_LATE_ACKN) IMU_SCLK<= 1'b1; else IMU_SCLK<= ~IMU_SCLK;
always @ (negedge IMU_SCLK) IMU_MOSI_REVA<= IMU_NMOSI;
`endif
\ No newline at end of file
imu_sim_tasks_include.vh 0 → 100644
View file @ d6e9be6b
/*******************************************************************************
* Include file: imu_sim_tasks_include.vh
* Date:2015-07-26
* Author: Andrey Filippov
* Description: Moved here all simulation tasks for IMU logger
*
* Copyright (c) 2015 Elphel, Inc .
* imu_sim_tasks_include.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* imu_sim_tasks_include.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`ifdef TEST_IMU
task send_serial_bit;
input [7:0] data_byte;
reg [7:0] d;
begin
d <= data_byte;
wait (CLK0); wait (~CLK0);
// SERIAL_BIT should be 1 here
// Send start bit
SERIAL_BIT <= 1'b0;
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
// Send 8 data bits, LSB first
repeat (8) begin
SERIAL_BIT <= d[0];
#1 d[7:0] <= {1'b0,d[7:1]};
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end
// Send stop bit
SERIAL_BIT <= 1'b1;
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end
endtask
task send_serial_pause;
begin
wait (CLK0); wait (~CLK0);
SERIAL_BIT <= 1'b1;
repeat (16) begin
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end
end
endtask
// SERIAL_DATA_FD=$fopen("gps_data.dat","r");
task send_serial_line;
integer char;
begin
char=0;
while (!$feof (SERIAL_DATA_FD) && (char != 'h0a)) begin
char=$fgetc(SERIAL_DATA_FD);
send_serial_bit(char);
end
end
endtask
`endif
\ No newline at end of file
memctrl353/descrproc353.v
View file @ d6e9be6b
...@@ -455,11 +455,13 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2)) ...@@ -455,11 +455,13 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
wire [4:0] padlen; wire [4:0] padlen;
assign padlen=((mode && (descr_stat[8:4]==5'h1f))?(descr_stat[13:9]+1'b1):descr_stat[13:9])+1; assign padlen=((mode && (descr_stat[8:4]==5'h1f))?(descr_stat[13:9]+1'b1):descr_stat[13:9])+1;
reg [15:0] linAddr; /// AF2015: was reg [15:0] linAddr;
reg [16:0] linAddr;
// wire [15:0] linAddr; //replacing with latches to ease timing // wire [15:0] linAddr; //replacing with latches to ease timing
wire [15:0] linAddr_input; ///AAF2015: wire [15:0] linAddr_input;
wire [18:0] linAddr_input; // to match multipler result, 2 MSBs are still discarded
wire [4:0] descr_stat_inc=descr_stat[8:4]+1; wire [4:0] descr_stat_inc=descr_stat[8:4]+1;
assign linAddr_input[15:0] = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; assign linAddr_input = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]};
always @ (negedge clk) if (stepsEn[1]) begin // address should be 1 always @ (negedge clk) if (stepsEn[1]) begin // address should be 1
...@@ -469,7 +471,8 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2)) ...@@ -469,7 +471,8 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10 seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat_inc):5'b0}); ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat_inc):5'b0});
sa[7:3] <= mode?descr_dyn[4:0]:5'b0; sa[7:3] <= mode?descr_dyn[4:0]:5'b0;
linAddr[15:0] <= linAddr_input[15:0]; ///AAF2015: linAddr <= linAddr_input[12:0];
linAddr <= linAddr_input[16:0];
nxtTL <= nxtTLw; nxtTL <= nxtTLw;
tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0) tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0)
...@@ -526,7 +529,8 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2)) ...@@ -526,7 +529,8 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
{descr_stat[3:0],8'b0,mode? {descr_stat[3:0],8'b0,mode?
descr_dyn[9:5]: descr_dyn[9:5]:
descr_dyn[4:0]}: descr_dyn[4:0]}:
{linAddr[15:0]})); /// AF2015: was {linAddr[16:0]}));
{linAddr[16:0]}));
end end
//photofinish hack //photofinish hack
always @ (negedge clk) if (stepsEn[1]) begin always @ (negedge clk) if (stepsEn[1]) begin
......
memctrl353/mcontr353.v
View file @ d6e9be6b
...@@ -359,13 +359,13 @@ module mcontr( ...@@ -359,13 +359,13 @@ module mcontr(
bufCntr256 i_bufCntr0 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[0]), .init(ch_prefirstdrun), .bank(nBuf[1:0]), bufCntr256 i_bufCntr0 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[0]), .init(ch_prefirstdrun), .bank(nBuf[1:0]),
.drun_rd(1'b0), .drun_wr(ch_drun_wr), .dlast(ch_dlast), .drun_rd(1'b0), .drun_wr(ch_drun_wr), .dlast(ch_dlast),
.a(bmad0[8:0]), .en(ch0en), .done(dnch[0])); .a(bmad0[8:0]), .en(ch0en), .done(dnch[0]),.we());
bufCntr256 i_bufCntr1 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[1]), .init(ch_prefirstdrun), .bank(nBuf[1:0]), bufCntr256 i_bufCntr1 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[1]), .init(ch_prefirstdrun), .bank(nBuf[1:0]),
.drun_rd(ch_drun_rd), .drun_wr(1'b0), .dlast(ch_dlast), .drun_rd(ch_drun_rd), .drun_wr(1'b0), .dlast(ch_dlast),
.a(bmad1[8:0]), .we(ch1we), .done(dnch[1])); .a(bmad1[8:0]), .we(ch1we), .done(dnch[1]), .en());
bufCntr256 i_bufCntr2 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[2]), .init(ch_prefirstdrun), .bank(nBuf[1:0]), bufCntr256 i_bufCntr2 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[2]), .init(ch_prefirstdrun), .bank(nBuf[1:0]),
.drun_rd(ch_drun_rd), .drun_wr(1'b0), .dlast(ch_dlast), .drun_rd(ch_drun_rd), .drun_wr(1'b0), .dlast(ch_dlast),
.a(bmad2[8:0]), .we(ch2we), .done(dnch[2])); .a(bmad2[8:0]), .we(ch2we), .done(dnch[2]), .en());
bufCntr256 i_bufCntr3 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[3]), .init(ch_prefirstdrun), .bank(nBuf[1:0]), bufCntr256 i_bufCntr3 (.clk(clk0), .rst(!enSDRAM), .cs(curChanLate[3]), .init(ch_prefirstdrun), .bank(nBuf[1:0]),
.drun_rd(ch_drun_rd), .drun_wr(ch_drun_wr), .dlast(ch_dlast), .drun_rd(ch_drun_rd), .drun_wr(ch_drun_wr), .dlast(ch_dlast),
.a(bmad3[8:0]), .en (ch3en), .we(ch3owe), .done(dnch[3]) .a(bmad3[8:0]), .en (ch3en), .we(ch3owe), .done(dnch[3])
...@@ -451,7 +451,9 @@ end ...@@ -451,7 +451,9 @@ end
.done(dnch[0]), // data transfer over .done(dnch[0]), // data transfer over
.rq(chnReq[0]), // request (level, sync to iclk) .rq(chnReq[0]), // request (level, sync to iclk)
.rqInit(chnReqInit[0]), // request to Init channel (level, sync to iclk) .rqInit(chnReqInit[0]), // request to Init channel (level, sync to iclk)
.rdy(ch0rdy)); // external ready output .rdy(ch0rdy), // external ready output
.rdy_async(), // output
.wrempty()); // output
channelRequest i_channelRequest1 (.rst(!enSDRAM), // probably for simulation only... channelRequest i_channelRequest1 (.rst(!enSDRAM), // probably for simulation only...
.init(chReqInit[1]), // 1 cycle long, sync to iclk .init(chReqInit[1]), // 1 cycle long, sync to iclk
...@@ -464,7 +466,10 @@ end ...@@ -464,7 +466,10 @@ end
.done(dnch[1]), // data transfer over .done(dnch[1]), // data transfer over
.rq(chnReq[1]), // request (level, sync to iclk) .rq(chnReq[1]), // request (level, sync to iclk)
.rqInit(chnReqInit[1]), // request to Init channel (level, sync to iclk) .rqInit(chnReqInit[1]), // request to Init channel (level, sync to iclk)
.rdy(ch1rdy)); // external ready output .rdy(ch1rdy), // external ready output
.rdy_async(), // output
.wrempty()); // output
channelRequest i_channelRequest2 (.rst(!enSDRAM), // probably for simulation only... channelRequest i_channelRequest2 (.rst(!enSDRAM), // probably for simulation only...
.init(chReqInit[2]), // 1 cycle long, sync to iclk .init(chReqInit[2]), // 1 cycle long, sync to iclk
...@@ -477,7 +482,9 @@ end ...@@ -477,7 +482,9 @@ end
.done(dnch[2]), // data transfer over .done(dnch[2]), // data transfer over
.rq(chnReq[2]), // request (level, sync to iclk) .rq(chnReq[2]), // request (level, sync to iclk)
.rqInit(chnReqInit[2]), // request to Init channel (level, sync to iclk) .rqInit(chnReqInit[2]), // request to Init channel (level, sync to iclk)
.rdy(ch2rdy)); // external ready output .rdy(ch2rdy), // external ready output
.rdy_async(), // output
.wrempty()); // output
channelRequest_1 i_channelRequest3 (.rst(!enSDRAM), // probably for simulation only... channelRequest_1 i_channelRequest3 (.rst(!enSDRAM), // probably for simulation only...
.init(chReqInit[3]), // 1 cycle long, sync to iclk. For now - do nothing in dcc mode .init(chReqInit[3]), // 1 cycle long, sync to iclk. For now - do nothing in dcc mode
...@@ -680,7 +687,7 @@ module channelRequest (rst, // only for simulation? ...@@ -680,7 +687,7 @@ module channelRequest (rst, // only for simulation?
assign ready_off= !cntrsValid || (ecnt[2:0] == rcnt[2:0]); assign ready_off= !cntrsValid || (ecnt[2:0] == rcnt[2:0]);
always @ (posedge eclk or posedge rst) always @ (posedge eclk or posedge rst)
if (rst) ecnt <= 2'b0; if (rst) ecnt <= 3'b0;
else if (start) ecnt[2:0] <= next_ecnt; else if (start) ecnt[2:0] <= next_ecnt;
// reduce latency of rdy - valid next cycle after start // reduce latency of rdy - valid next cycle after start
...@@ -768,7 +775,7 @@ module channelRequest_1 (rst, // only for simulation? ...@@ -768,7 +775,7 @@ module channelRequest_1 (rst, // only for simulation?
assign ready_off= !cntrsValid || (ecnt[2:0] == rcnt[2:0]); assign ready_off= !cntrsValid || (ecnt[2:0] == rcnt[2:0]);
always @ (negedge eclk or posedge rst) always @ (negedge eclk or posedge rst)
if (rst) ecnt <= 2'b0; if (rst) ecnt <= 3'b0;
else if (start) ecnt[2:0] <= next_ecnt; else if (start) ecnt[2:0] <= next_ecnt;
// reduce latency of rdy - valid next cycle after start // reduce latency of rdy - valid next cycle after start
......
memctrl353/sdseq353.v
View file @ d6e9be6b
...@@ -185,8 +185,8 @@ module sdseq (clk0, // global clock 75-100MHz (hope to get to 120MHz with Sparta ...@@ -185,8 +185,8 @@ module sdseq (clk0, // global clock 75-100MHz (hope to get to 120MHz with Sparta
prenext_wr <= drun_wr && pre_next_old; prenext_wr <= drun_wr && pre_next_old;
next <= prenext_refr || prenext_wr || (!drun_wr && pre_next_old); // add m0 and refr here too next <= prenext_refr || prenext_wr || (!drun_wr && pre_next_old); // add m0 and refr here too
decLeft <= (prenext_m1s || prenext_m1d || prenext_m0); // add m0 and refr here too decLeft <= (prenext_m1s || prenext_m1d || prenext_m0); // add m0 and refr here too
if (first) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]); if (first) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
///AF2015 - revert: if (first || rst) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
else if (decLeft) left[4:0] <= left[4:0] -1; else if (decLeft) left[4:0] <= left[4:0] -1;
end end
......
sensor/lens_flat.v
View file @ d6e9be6b
...@@ -87,7 +87,7 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -87,7 +87,7 @@ module lens_flat (sclk, /// system clock @negedge
reg [20:0] BY; /// By reg [20:0] BY; /// By
reg [18:0] C; /// C reg [18:0] C; /// C
reg [16:0] scales[0:3]; // per-color coefficients reg [16:0] scales[0:3]; // per-color coefficients
reg [16:0] scales_r; ///AF: reg [16:0] scales_r;
reg [15:0] fatzero_in; /// zero level to subtract before multiplication reg [15:0] fatzero_in; /// zero level to subtract before multiplication
reg [15:0] fatzero_out; /// zero level to add after multiplication reg [15:0] fatzero_out; /// zero level to add after multiplication
reg [ 3:0] post_scale; /// shift product after first multiplier - maybe needed when using decimation reg [ 3:0] post_scale; /// shift product after first multiplier - maybe needed when using decimation
...@@ -95,7 +95,7 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -95,7 +95,7 @@ module lens_flat (sclk, /// system clock @negedge
wire [18:0] FY; /// F(0,y) wire [18:0] FY; /// F(0,y)
wire [23:0] ERR_Y; /// running error for the first column wire [23:0] ERR_Y; /// running error for the first column
wire [18:0] FXY; /// F(x,y) wire [18:0] FXY; /// F(x,y)
reg [18:0] FXY_sat; ///AF: reg [18:0] FXY_sat;
reg [ 4:0] lens_corr_out; /// lens correction out valid (first clock from column0 ) reg [ 4:0] lens_corr_out; /// lens correction out valid (first clock from column0 )
/// copied form sensorpix353.v /// copied form sensorpix353.v
reg bayer_nset; reg bayer_nset;
...@@ -158,7 +158,7 @@ module lens_flat (sclk, /// system clock @negedge ...@@ -158,7 +158,7 @@ module lens_flat (sclk, /// system clock @negedge
3'h7:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:26]) ? 18'h1ffff:mult_first_res[26: 9]; 3'h7:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:26]) ? 18'h1ffff:mult_first_res[26: 9];
endcase endcase
if (lens_corr_out[4]) pixdo[15:0]=pre_pixdo_with_zero[20]? 16'h0: /// negative - use 0 if (lens_corr_out[4]) pixdo[15:0] <= pre_pixdo_with_zero[20]? 16'h0: /// negative - use 0
((|pre_pixdo_with_zero[19:16])?16'hffff: ///>0xffff - limit by 0xffff ((|pre_pixdo_with_zero[19:16])?16'hffff: ///>0xffff - limit by 0xffff
pre_pixdo_with_zero[15:0]); pre_pixdo_with_zero[15:0]);
end end
...@@ -324,6 +324,7 @@ module lens_flat_line( ...@@ -324,6 +324,7 @@ module lens_flat_line(
if (first_d) F[F_WIDTH-1:0] <= F1[ F_WIDTH-1:0]; if (first_d) F[F_WIDTH-1:0] <= F1[ F_WIDTH-1:0];
else if (next_d) F[F_WIDTH-1:0] <= F[F_WIDTH-1:0]+{{(F_WIDTH-(DF_WIDTH)){dF[(DF_WIDTH)-1]}},dF[(DF_WIDTH)-1:0]}; else if (next_d) F[F_WIDTH-1:0] <= F[F_WIDTH-1:0]+{{(F_WIDTH-(DF_WIDTH)){dF[(DF_WIDTH)-1]}},dF[(DF_WIDTH)-1:0]};
if (first_d) A2X[F_SHIFT+1:1] <= {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]}; if (first_d) A2X[F_SHIFT+1:1] <= {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]};
else if (next) A2X[F_SHIFT+1:1] <= A2X[F_SHIFT+1:1] + {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]}; else if (next) A2X[F_SHIFT+1:1] <= A2X[F_SHIFT+1:1] + {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]};
end end
......
sensor/sensor12bits.v
View file @ d6e9be6b
...@@ -17,8 +17,8 @@ input MCLK, // Master clock ...@@ -17,8 +17,8 @@ input MCLK, // Master clock
ARO, // Array read Out. ARO, // Array read Out.
ARST, // Array Reset. Active low ARST, // Array Reset. Active low
OE, // output enable active low OE, // output enable active low
SCL; // I2C clock SCL; // I2C clock // SuppressThisWarning Veditor: Not yet implemented
inout SDA; // I2C data inout SDA; // I2C data // SuppressThisWarning Veditor: Not yet implemented
input OFST; // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode. input OFST; // I2C address ofset by 2: for simulation 0 - still mode, 1 - video mode.
output [11:0] D; // data output output [11:0] D; // data output
...@@ -33,7 +33,7 @@ parameter ncols = 66; //58; //56; // 129; //128; //1288; ...@@ -33,7 +33,7 @@ parameter ncols = 66; //58; //56; // 129; //128; //1288;
parameter nrows = 18; // 16; // 1032; parameter nrows = 18; // 16; // 1032;
parameter nrowb = 1; // number of "blank rows" from vact to 1-st hact parameter nrowb = 1; // number of "blank rows" from vact to 1-st hact
parameter nrowa = 1; // number of "blank rows" from last hact to end of vact parameter nrowa = 1; // number of "blank rows" from last hact to end of vact
parameter nAV = 24; //240; // clocks from ARO to VACT (actually from en_dclkd) parameter nAV = 24; //240; // clocks from ARO to VACT (actually from en_dclkd) // SuppressThisWarning Veditor UNUSED
parameter nbpf = 20; //16; // bpf length parameter nbpf = 20; //16; // bpf length
parameter ngp1 = 8; // bpf to hact parameter ngp1 = 8; // bpf to hact
parameter nVLO = 1; // VACT=0 in video mode (clocks) parameter nVLO = 1; // VACT=0 in video mode (clocks)
...@@ -64,7 +64,7 @@ parameter t_HACT= ncols; // 1288 ...@@ -64,7 +64,7 @@ parameter t_HACT= ncols; // 1288
parameter t_afterHACT=lline-nbpf-ngp1-ncols; // 352 parameter t_afterHACT=lline-nbpf-ngp1-ncols; // 352
parameter t_lastline= nrowa*lline+1; // 1664 parameter t_lastline= nrowa*lline+1; // 1664
reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels // SuppressThisWarning Veditor VDT_BUG - assigned in system task
// $readmemh("sensor.dat",sensor_data); // $readmemh("sensor.dat",sensor_data);
......
sensor/sensorpads353.v
View file @ d6e9be6b
...@@ -86,7 +86,7 @@ module sensorpads (/// interface to DCM ...@@ -86,7 +86,7 @@ module sensorpads (/// interface to DCM
output pclk2x; output pclk2x;
input vact; input vact;
input hact; //output in fillfactory mode input hact; //output in fillfactory mode
inout bpf; // output in fillfactory mode inout bpf; // output in fillfactory mode // SuppressThisWarning Veditor - not used as output
inout [11:0] pxd; //actually only 2 LSBs are inouts inout [11:0] pxd; //actually only 2 LSBs are inouts
inout mrst; inout mrst;
output arst; output arst;
......
x353.v
View file @ d6e9be6b
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
`define debug_dma_count `define debug_dma_count
`define debug_compressor `define debug_compressor
`define debug_mcontr_reset `define debug_mcontr_reset
// `define DEBUG_IMU
module x353(PXD,DCLK,BPF,VACT,HACT,MRST,ARO,ARST,SCL0,SDA0,CNVSYNC,CNVCLK, SENSPGM, module x353(PXD,DCLK,BPF,VACT,HACT,MRST,ARO,ARST,SCL0,SDA0,CNVSYNC,CNVCLK, SENSPGM,
DUMMYVFEF, ALWAYS0, DUMMYVFEF, ALWAYS0,
EXT, EXT,
...@@ -237,8 +238,8 @@ wire [31:0] debug_mcontr_reset_data; ...@@ -237,8 +238,8 @@ wire [31:0] debug_mcontr_reset_data;
wire ARST; wire ARST;
wire CNVSYNC; wire CNVSYNC;
wire CNVCLK; wire CNVCLK;
wire XRST; ///AF: wire XRST;
wire AUXCLK; ///AF: wire AUXCLK;
wire SDCLK; wire SDCLK;
wire DREQ0,DREQ1; wire DREQ0,DREQ1;
wire IRQ; wire IRQ;
...@@ -248,8 +249,8 @@ wire [31:0] debug_mcontr_reset_data; ...@@ -248,8 +249,8 @@ wire [31:0] debug_mcontr_reset_data;
// internal wires // internal wires
wire iclk3; wire iclk3;
wire dccout; // enable output of DC and HF components - not used anymore wire dccout; // enable output of DC and HF components - not used anymore //SuppressThisWarning Veditor UNUSED
wire dcc_enabled; wire dcc_enabled; //SuppressThisWarning Veditor UNUSED
wire dcc_rdy=0; // Ready to read 128 DC coefficients in dcc mode. Actually they will be availabla a little later after being copied to wire dcc_rdy=0; // Ready to read 128 DC coefficients in dcc mode. Actually they will be availabla a little later after being copied to
// 8x32 output buffer // 8x32 output buffer
...@@ -264,13 +265,13 @@ wire iclk3; ...@@ -264,13 +265,13 @@ wire iclk3;
wire [31:0] iod; // 32-bit data to be sent to CPU wire [31:0] iod; // 32-bit data to be sent to CPU
wire [31:0] idi; // 32-bit data from CPU wire [31:0] idi; // 32-bit data from CPU
wire [31:0] dcr; // 32-bit control register ///AF: wire [31:0] dcr; // 32-bit control register
wire [ 7:0] as; // internal address bus - sync to sclk0 wire [ 7:0] as; // internal address bus - sync to sclk0
wire [ 7:0] am; // internal address bus - multiplexed between input (for reads) and sycnc (for writes) - should not read too soon after write wire [ 7:0] am; // internal address bus - multiplexed between input (for reads) and sycnc (for writes) - should not read too soon after write
wire [ 7:0] ia; // internal address bus - before latches wire [ 7:0] ia; // internal address bus - before latches
wire sclk0; // 120MHz (same as CLK0) - SDRAM/compressor controller global clock wire sclk0; // 120MHz (same as CLK0) - SDRAM/compressor controller global clock
wire sclk180; // 120MHz (same as CLK0) - phase shifted 180 degrees (maybe not needed) wire sclk180; // 120MHz (same as CLK0) - phase shifted 180 degrees (maybe not needed) //SuppressThisWarning Veditor UNUSED
wire sclk270; // 120MHz (same as CLK0) - phase shifted 270 degrees wire sclk270; // 120MHz (same as CLK0) - phase shifted 270 degrees
wire pclk; // sensor pixel clock wire pclk; // sensor pixel clock
wire xclk; // 60MHz (=CLK0/2) - JPEG compressor clock (input stages) wire xclk; // 60MHz (=CLK0/2) - JPEG compressor clock (input stages)
...@@ -286,7 +287,7 @@ wire iclk3; ...@@ -286,7 +287,7 @@ wire iclk3;
// allow one per trigger in triggered mode. Minimal period set to 129 pixel clocks // allow one per trigger in triggered mode. Minimal period set to 129 pixel clocks
wire [15:0] ipxd; wire [15:0] ipxd;
wire sens_we; wire sens_we;
wire [15:0] sens_wdl; ///AF: wire [15:0] sens_wdl;
wire sens_wpage; wire sens_wpage;
wire [ 9:0] fpn_a; wire [ 9:0] fpn_a;
wire [15:0] fpn_d; wire [15:0] fpn_d;
...@@ -338,7 +339,7 @@ wire iclk3; ...@@ -338,7 +339,7 @@ wire iclk3;
wire idreq1; wire idreq1;
wire idack1; wire idack1;
wire da_ctl_24l, da_ctl_8h; // WE to control 32-bit register (1 loc) *********** obsolete ************** wire da_ctl_24l, da_ctl_8h; // WE to control 32-bit register (1 loc) *********** obsolete ************** //SuppressThisWarning Veditor UNUSED
wire da_dmamode; // select writing to dma_cntr/dma_raw (1 loc) wire da_dmamode; // select writing to dma_cntr/dma_raw (1 loc)
wire da_sensormode; // select writing to sensorpix (1 loc) wire da_sensormode; // select writing to sensorpix (1 loc)
wire da_virttrig; // write virtual trigger threshold wire da_virttrig; // write virtual trigger threshold
...@@ -404,7 +405,7 @@ wire iclk3; ...@@ -404,7 +405,7 @@ wire iclk3;
wire [ 9:0] sens_a; // [7:0] channel 0 address (MSB - block #) wire [ 9:0] sens_a; // [7:0] channel 0 address (MSB - block #)
wire [15:0] sens_d; // [15:0] channel 0 data in wire [15:0] sens_d; // [15:0] channel 0 data in
wire trigger_single_pclk; // start of trigger wire trigger_single_pclk; // start of trigger //SuppressThisWarning Veditor UNUSED
wire [31:0] bdo; // 32-bit data from SDRAM channel3 wire [31:0] bdo; // 32-bit data from SDRAM channel3
wire [31:0] dsdo; // 32-bit data from SDRAM descriptor memory wire [31:0] dsdo; // 32-bit data from SDRAM descriptor memory
...@@ -413,7 +414,9 @@ wire iclk3; ...@@ -413,7 +414,9 @@ wire iclk3;
wire [31:0] hist_do; // histogram data out, actully only [17:0]; wire [31:0] hist_do; // histogram data out, actully only [17:0];
wire sr_sda0, sr_scl0, sr_sda1, sr_scl1,sr_memrdy,sr_ch0rdy,sr_ch1rdy,sr_ch2rdy,sr_wrempty; wire sr_sda0, sr_scl0;
///AF: wire sr_sda1, sr_scl1;
wire sr_memrdy,sr_ch0rdy,sr_ch1rdy,sr_ch2rdy,sr_wrempty;
wire [3:0] sr_nextFrame; //[3:0] wire [3:0] sr_nextFrame; //[3:0]
wire [3:0] chInitOnehot; // decoded channel init pulses, 2 cycles behind chInit wire [3:0] chInitOnehot; // decoded channel init pulses, 2 cycles behind chInit
...@@ -431,9 +434,11 @@ wire iclk3; ...@@ -431,9 +434,11 @@ wire iclk3;
// does not inclusde flushing // does not inclusde flushing
wire compressor_done_pulse; // does not need to be reset, single cycle (sclk) wire compressor_done_pulse; // does not need to be reset, single cycle (sclk)
wire dma_empty,dma_empty0,dma_empty1; // dma output buffer empty and dma is enabled (pessimistic - with delay) wire dma_empty; // dma output buffer empty and dma is enabled (pessimistic - with delay)
///AF: wire dma_empty0,dma_empty1; // dma output buffer empty and dma is enabled (pessimistic - with delay)
wire virt_trig, virt_sel; wire virt_trig;
wire virt_sel; //SuppressThisWarning Veditor UNUSED
wire ch2_en_rd_buff; wire ch2_en_rd_buff;
...@@ -457,10 +462,10 @@ wire iclk3; ...@@ -457,10 +462,10 @@ wire iclk3;
wire twr_gamma; // write enable to "gamma" table (@negedge clk - addr and data valid this cycle and one before) wire twr_gamma; // write enable to "gamma" table (@negedge clk - addr and data valid this cycle and one before)
wire twr_focus; // write enable to "focus" table (coefficients to multiply DCT results before accumulating squares) wire twr_focus; // write enable to "focus" table (coefficients to multiply DCT results before accumulating squares)
wire statistics_dv; // image statistics word valid (sync to clk) wire statistics_dv; // image statistics word valid (sync to clk) //SuppressThisWarning Veditor UNUSED
wire [15:0] statistics_do; // 16-bit image statistics data to write wire [15:0] statistics_do; // 16-bit image statistics data to write //SuppressThisWarning Veditor UNUSED
wire line_run; wire line_run;
wire frame_run; wire frame_run; // SuppressThisWarning Veditor UNUSED
// synthesis attribute keep of rd_regs is true; // synthesis attribute keep of rd_regs is true;
...@@ -468,12 +473,12 @@ wire iclk3; ...@@ -468,12 +473,12 @@ wire iclk3;
wire stuffer_dv; wire stuffer_dv;
wire [3:0] test_dma_rcntr; ///AF: wire [3:0] test_dma_rcntr;
wire [3:0] test_dma_wcntr; wire [3:0] test_dma_wcntr; // SuppressThisWarning Veditor UNUSED
wire [3:0] test_fifo; wire [3:0] test_fifo; // SuppressThisWarning Veditor UNUSED
wire [3:0] test_dma1_rcntr; ///AF: wire [3:0] test_dma1_rcntr;
wire [7:0] test_dma1_wcntr; wire [7:0] test_dma1_wcntr; // SuppressThisWarning Veditor UNUSED
wire [7:0] test_fifo1; wire [7:0] test_fifo1;
...@@ -520,37 +525,38 @@ wire [7:0] dcm_status; ...@@ -520,37 +525,38 @@ wire [7:0] dcm_status;
wire sens_dcm_locked; wire sens_dcm_locked;
wire sens_dcm_done; wire sens_dcm_done;
wire [7:0] sens_dcm_status; wire [7:0] sens_dcm_status;
wire [1:0] sens_ph_err; wire [1:0] sens_ph_err = 0; // currently not assigned (removed module)
wire ioe;// internal (not global) version of OE (for DMA) wire ioe;// internal (not global) version of OE (for DMA)
wire [1:0] phsel; // additional phase select for SDRAM clock wire [1:0] phsel; // additional phase select for SDRAM clock
wire pclk2x; // twice frequency of the pclk, global wire pclk2x; // twice frequency of the pclk, global
wire [1:0] sensordat_pherr; // sync to posedge pclk, PXD[2] differs with 1/4 early, 1/4 late wire [1:0] sensordat_pherr; // sync to posedge pclk, PXD[2] differs with 1/4 early, 1/4 late //SuppressThisWarning Veditor UNUSED
wire sensor_trigger; // signal to start CMOS sensor in sync mode wire sensor_trigger; // signal to start CMOS sensor in sync mode
wire confirmFrame2Compressor; // pulse to start reading a new frame to buffer for compressor (generated at start of each frame by the compressor) wire confirmFrame2Compressor; // pulse to start reading a new frame to buffer for compressor (generated at start of each frame by the compressor)
// mcontr will stop to read to channel FIFO at the end of frame, wait for confirmation // mcontr will stop to read to channel FIFO at the end of frame, wait for confirmation
`ifdef debug_compressor `ifdef debug_compressor
wire [31:0] printk_compressor; wire [31:0] printk_compressor; //SuppressThisWarning Veditor UNUSED
`endif `endif
//ia //ia
`ifdef debug_stuffer `ifdef debug_stuffer
wire [7:0] testwire; wire [7:0] testwire;
//wire [31:0] printk;
wire [3:0] tst_stuf_etrax; wire [3:0] tst_stuf_etrax;
reg [3:0] tst_cmd_cntr; reg [3:0] tst_cmd_cntr;
reg tst_rdy_after_eot; reg tst_rdy_after_eot;
// ,.test1( test_fifo[3:0]) ///AF: wire dma0_enabled; // just for debug
// ,.test2( test_dma_wcntr[3:0]) ///AF: wire dma1_enabled; // just for debug
wire dma0_enabled; // just for debug
wire dma1_enabled; // just for debug
`endif `endif
`ifdef debug_dma_count `ifdef debug_dma_count
wire [31:0] printk; wire [31:0] printk;
`endif `endif
// Needed anyway:
wire dma0_enabled; // just for debug
wire dma1_enabled; // just for debug
/* /*
//xfer_over_irq //xfer_over_irq
reg [3:0] test_11; reg [3:0] test_11;
...@@ -562,10 +568,24 @@ wire [3:0] nextBlocksEn; // When combined with SDRAM data ready, may be used ...@@ -562,10 +568,24 @@ wire [3:0] nextBlocksEn; // When combined with SDRAM data ready, may be used
wire [3:0] restart; // reinitialize mcontr channels (normally after frame sync, if enabled) wire [3:0] restart; // reinitialize mcontr channels (normally after frame sync, if enabled)
// debug IMU // Wires missing in the original 353 design
wire imu_enabled_mclk; wire sdwe_p; // WE command bit to SDRAM (1 cycle ahead)
wire imu_run_mclk; wire sdras_p; // CAS command bit to SDRAM (1 cycle ahead)
wire [31:0] imu_period; wire sdcas_p; // CAS command bit to SDRAM
wire sd_dqsrd; // enable read from DQS i/o-s for phase adjustments (latency 2 from the SDRAM RD command)
wire trig_irq; // single-cycle (pclk) pulse at external interrupt
wire da_init_ch3; // write to init cnhannel 3 (will reset address r/w)
wire da_next_ch3; // advance to the next channel3 page, reset address
wire stch2; // start channel 2 transfer
`ifdef DEBUG_IMU// debug IMU
wire imu_enabled_mclk;
wire imu_run_mclk;
wire [31:0] imu_period;
`endif
...@@ -699,7 +719,6 @@ wire [31:0] imu_period; ...@@ -699,7 +719,6 @@ wire [31:0] imu_period;
// temporary change behaviour of dqs2 to fix pinout problem - will influence adjustment goal // temporary change behaviour of dqs2 to fix pinout problem - will influence adjustment goal
dqs2 i_sddqs(.c0(sclk0),/*.c90(sclk90),*/.c270(sclk270), dqs2 i_sddqs(.c0(sclk0),/*.c90(sclk90),*/.c270(sclk270),
// dqs2 i_sddqs(.c0(sclk0),.c0comb(sclk270),.c90(sclk90),.c270(sclk270),
.t (sddqt), // 1/2 cycle before cmd "write" sent out to the SDRAM, sync to sclk180 .t (sddqt), // 1/2 cycle before cmd "write" sent out to the SDRAM, sync to sclk180
.UDQS (UDQS), // UDQS I/O pin .UDQS (UDQS), // UDQS I/O pin
.LDQS (LDQS), // LDQS I/O pin .LDQS (LDQS), // LDQS I/O pin
...@@ -707,7 +726,6 @@ wire [31:0] imu_period; ...@@ -707,7 +726,6 @@ wire [31:0] imu_period;
.ldqsr90 (ldqsr90), // data from SDRAM interface pin LDQS strobed at rising sclk90 .ldqsr90 (ldqsr90), // data from SDRAM interface pin LDQS strobed at rising sclk90
.udqsr270(udqsr270), // data from SDRAM interface pin UDQS strobed at rising sclk270 .udqsr270(udqsr270), // data from SDRAM interface pin UDQS strobed at rising sclk270
.ldqsr270(ldqsr270) // data from SDRAM interface pin UDQS strobed at rising sclk270 .ldqsr270(ldqsr270) // data from SDRAM interface pin UDQS strobed at rising sclk270
// ,.qtmp(qtmp[3:0]) // temporary
); );
...@@ -973,43 +991,15 @@ BUFGMUX i_pclk (.O(pclk), .I0(pclki), .I1(sens_clk), .S(|cb_pclksrc[1:0])); ...@@ -973,43 +991,15 @@ BUFGMUX i_pclk (.O(pclk), .I0(pclki), .I1(sens_clk), .S(|cb_pclksrc[1:0]));
//cb_pxd14 //cb_pxd14
assign ihact=iihact; assign ihact=iihact;
/*
sensor_phase i_sensor_phase(.pre_wcmd(da_dcm), // decoded address - enables wclk
.wd(idi[7:4]), // CPU write data [3:0]
// 0 - nop, just reset status data
// 1 - increase phase shift
// 2 - decrease phase shift
// 3 - reset phase shift to default (preprogrammed in FPGA configuration)
// c - reset phase90
// 4 - incr pahse90
// 8 - decrease phase90
//
.sensordat_pherr(sensordat_pherr[1:0]), // phase error detected on PXD[2] (should be different)
.ph_err(sens_ph_err[1:0]), // [1:0] 0 - no data since last change (wclk*wcmd)
// 1 - clock is too late
// 2 - clock is too early
// 3 - OK (some measurements show too late, some - too early)
.sclk0(sclk0), // global clock, (negedge - commands)
.pclk(pclk), // global pixel clock (posedge) - from CLK1
.pixclko(idclk), // pixel clock out (phase shifted from global pclk
.dcm_done( sens_dcm_done),
.locked(sens_dcm_locked), // dcm locked
.status(sens_dcm_status[7:0]), // dcm status (bit 1 - dcm clkin stopped)
.pclk2x(pclk2x) // pclk multiplied by 2
);
*/
//da_sensortrig_lines //da_sensortrig_lines
reg [9:0] ch0_blocks_in_line; ///AF: reg [9:0] ch0_blocks_in_line;
reg mode16bits; ///AF: reg mode16bits;
reg [13:3] pre_hact_length; ///AF: reg [13:3] pre_hact_length;
reg [13:0] hact_length; reg [13:0] hact_length;
always @(negedge sclk0) if (da_sensortrig_lines && (idi[15:14]==2'h1)) begin always @(negedge sclk0) if (da_sensortrig_lines && (idi[15:14]==2'h1)) begin
hact_length[13:0] <= idi[13:0]; hact_length[13:0] <= idi[13:0];
end end
// .en_vacts(!cb_sensor_trigger || sensor_trigger ), // disable processing second vact after the trigger in triggered mode
reg en_vacts_free=1'b1; // register to allow only one vacts after trigger in triggered mode. Allows first vacts after mode is set reg en_vacts_free=1'b1; // register to allow only one vacts after trigger in triggered mode. Allows first vacts after mode is set
always @ (posedge pclk) begin always @ (posedge pclk) begin
if (!cb_sensor_trigger) en_vacts_free<= 1'b1; if (!cb_sensor_trigger) en_vacts_free<= 1'b1;
...@@ -1428,7 +1418,8 @@ cmd_sequencer i_cmd_sequencer ...@@ -1428,7 +1418,8 @@ cmd_sequencer i_cmd_sequencer
.seq_a(sequencer_a[7:0]), // address from the sequencer .seq_a(sequencer_a[7:0]), // address from the sequencer
.seq_d(sequencer_d[23:0]), // data from the sequencer .seq_d(sequencer_d[23:0]), // data from the sequencer
.frame_no(sequencer_frame_no[2:0])); // [2:0] current frame modulo 8 .frame_no(sequencer_frame_no[2:0])); // [2:0] current frame modulo 8
wire [7:4] test_fifo_dummy; //SuppressThisWarning Veditor UNUSED
wire [7:4] test_dma_wcntr_dummy; //SuppressThisWarning Veditor UNUSED
dma_fifo_sync i_dma_fifo0 ( .clk(sclk0), // system clock, 120MHz? (currentle negedge used) dma_fifo_sync i_dma_fifo0 ( .clk(sclk0), // system clock, 120MHz? (currentle negedge used)
.pre_wen(da_dmamode), // decoded addresses (valid @ negedge clk) .pre_wen(da_dmamode), // decoded addresses (valid @ negedge clk)
// .wd({idi[3],idi[1]}), // only 2 bits are used - {pio_mode,dma_enable} 1 cycle delay // .wd({idi[3],idi[1]}), // only 2 bits are used - {pio_mode,dma_enable} 1 cycle delay
...@@ -1443,8 +1434,8 @@ cmd_sequencer i_cmd_sequencer ...@@ -1443,8 +1434,8 @@ cmd_sequencer i_cmd_sequencer
.di({stuffer_do[7:0],stuffer_do[15:8]}), // 16-bit data to write .di({stuffer_do[7:0],stuffer_do[15:8]}), // 16-bit data to write
.enabled(dma0_enabled), .enabled(dma0_enabled),
.real_empty(dma_empty) .real_empty(dma_empty)
,.test1( test_fifo[3:0]) ,.test1( {test_fifo_dummy[7:4], test_fifo[3:0]})
,.test2( test_dma_wcntr[3:0]) ,.test2( {test_dma_wcntr_dummy[7:4], test_dma_wcntr[3:0]})
); // pessimistic, with several clk delay ); // pessimistic, with several clk delay
/* /*
...@@ -1521,7 +1512,7 @@ end ...@@ -1521,7 +1512,7 @@ end
if (debug_mcontr_compressor_eot) debug_mcontr_count_end <= {sr_ch2rdy, compressor_done_input, confirmFrame2Compressor, debug_mcontr_count}; if (debug_mcontr_compressor_eot) debug_mcontr_count_end <= {sr_ch2rdy, compressor_done_input, confirmFrame2Compressor, debug_mcontr_count};
end end
reg [11:0] debug_interrupt_counts; reg [11:0] debug_interrupt_counts; //SuppressThisWarning Veditor UNUSED
reg [ 3:0] debug_interrupt_frames=0; reg [ 3:0] debug_interrupt_frames=0;
reg [ 3:0] debug_interrupt_starts=0; reg [ 3:0] debug_interrupt_starts=0;
reg [ 3:0] debug_interrupt_dones=0; reg [ 3:0] debug_interrupt_dones=0;
...@@ -1538,7 +1529,7 @@ end ...@@ -1538,7 +1529,7 @@ end
end end
`endif `endif
wire [2:0] compressor_test_state; // {is_compressing,cmprs_repeat,cmprs_en} wire [2:0] compressor_test_state; // {is_compressing,cmprs_repeat,cmprs_en} //SuppressThisWarning Veditor UNUSED
compressor i_compressor( .clk(xclk), // compressor pixel clock (80MHz?) compressor i_compressor( .clk(xclk), // compressor pixel clock (80MHz?)
.clk2x(sclk0), // twice compressor pixel clock (120MHz) - for huffman/stuffer), memory clock, input data clock (negedge) .clk2x(sclk0), // twice compressor pixel clock (120MHz) - for huffman/stuffer), memory clock, input data clock (negedge)
.cwe(da_compressor), // we to compressor from CPU .cwe(da_compressor), // we to compressor from CPU
...@@ -1719,9 +1710,11 @@ end ...@@ -1719,9 +1710,11 @@ end
// dummy module instances // dummy module instances
wire iclk2; (* keep *)
wire iclk2; // SuppressThisWarning Veditor UNUSED
IBUF i_iclk2 (.I(CLK2), .O(iclk2)); IBUF i_iclk2 (.I(CLK2), .O(iclk2));
wire iclk4; (* keep *)
wire iclk4; // SuppressThisWarning Veditor UNUSED
IBUF i_iclk4 (.I(CLK4), .O(iclk4)); IBUF i_iclk4 (.I(CLK4), .O(iclk4));
IBUF i_iclk3 (.I(CLK3), .O(iclk3)); IBUF i_iclk3 (.I(CLK3), .O(iclk3));
...@@ -1729,8 +1722,8 @@ wire iclk4; ...@@ -1729,8 +1722,8 @@ wire iclk4;
// 3 legacy wires // 3 legacy wires
assign itrig=io_pins[5]; assign itrig=io_pins[5];
assign sr_sda1=io_pins[1]; ///AF: assign sr_sda1=io_pins[1];
assign sr_scl1=io_pins[0]; ///AF: assign sr_scl1=io_pins[0];
IOBUF i_iopins0 (.I(io_do[ 0]), .T(io_t[ 0]), .O(io_pins[ 0]), .IO(EXT[ 0])); IOBUF i_iopins0 (.I(io_do[ 0]), .T(io_t[ 0]), .O(io_pins[ 0]), .IO(EXT[ 0]));
IOBUF i_iopins1 (.I(io_do[ 1]), .T(io_t[ 1]), .O(io_pins[ 1]), .IO(EXT[ 1])); IOBUF i_iopins1 (.I(io_do[ 1]), .T(io_t[ 1]), .O(io_pins[ 1]), .IO(EXT[ 1]));
......
x353.xcf
View file @ d6e9be6b
...@@ -201,14 +201,14 @@ TIMESPEC "TS_CLK1" = PERIOD "CLK1" 10.4 ns HIGH 50 %; #96MHz ...@@ -201,14 +201,14 @@ TIMESPEC "TS_CLK1" = PERIOD "CLK1" 10.4 ns HIGH 50 %; #96MHz
#TIMESPEC "TS_CLK1" = PERIOD "CLK1" 18.4 ns HIGH 50 %; #TEMPORARY TO FIND A PROBLEM #TIMESPEC "TS_CLK1" = PERIOD "CLK1" 18.4 ns HIGH 50 %; #TEMPORARY TO FIND A PROBLEM
TIMEGRP "CPU_ADDR" = pads("A<*>"); TIMEGRP "CPU_ADDR" = PADS("A<*>");
TIMEGRP "CPU_ADDRCE" = "CPU_ADDR" pads("CE*"); TIMEGRP "CPU_ADDRCE" = "CPU_ADDR" PADS("CE*");
TIMEGRP "CPU_DATA" = pads("D<*>"); TIMEGRP "CPU_DATA" = PADS("D<*>");
TIMEGRP "WE" = pads("WE"); TIMEGRP "WE" = PADS("WE");
TIMEGRP "OE" = pads("OE"); TIMEGRP "OE" = PADS("OE");
TIMEGRP "DACK_PAD"= pads("DACK*"); TIMEGRP "DACK_PAD"= PADS("DACK*");
TIMEGRP "DREQ_PAD"= pads("DREQ*"); TIMEGRP "DREQ_PAD"= PADS("DREQ*");
TIMEGRP "ALLPADS"= pads("*"); TIMEGRP "ALLPADS"= PADS("*");
NET "idack0" TPTHRU = "IDACK0_TP"; NET "idack0" TPTHRU = "IDACK0_TP";
NET "idack1" TPTHRU = "IDACK1_TP"; NET "idack1" TPTHRU = "IDACK1_TP";
...@@ -217,8 +217,8 @@ NET "idack1" TPTHRU = "IDACK1_TP"; ...@@ -217,8 +217,8 @@ NET "idack1" TPTHRU = "IDACK1_TP";
#TIMESPEC "TS_DACK_DREQ0" = FROM "DACK_PAD" THRU "IDACK0_TP" THRU "IDREQ0_TP" TO "DREQ_PAD" 9.5 ns; #TIMESPEC "TS_DACK_DREQ0" = FROM "DACK_PAD" THRU "IDACK0_TP" THRU "IDREQ0_TP" TO "DREQ_PAD" 9.5 ns;
#TIMESPEC "TS_DACK_DREQ1" = FROM "DACK_PAD" THRU "IDACK1_TP" THRU "IDREQ1_TP" TO "DREQ_PAD" 9.5 ns; #TIMESPEC "TS_DACK_DREQ1" = FROM "DACK_PAD" THRU "IDACK1_TP" THRU "IDREQ1_TP" TO "DREQ_PAD" 9.5 ns;
NET "*/cwr" TNM_NET = "TNM_CWR"; NET "*/cwr" TNM_NET = "TNM_CWR";
TIMEGRP "TG_CWRDEST" = "TNM_CWR" except latches ("*"); # RAMS, FFS TIMEGRP "TG_CWRDEST" = "TNM_CWR" except LATCHES ("*"); # RAMS, FFS
###MARK1# TIMEGRP "TG_LATCHES_A" = latches ("i_sysinterface/i_a*"); ###MARK1# TIMEGRP "TG_LATCHES_A" = LATCHES ("i_sysinterface/i_a*");
NET "DACK*" TNM_NET = "DACK"; NET "DACK*" TNM_NET = "DACK";
NET "SDA0*" TNM_NET = "SDA0"; NET "SDA0*" TNM_NET = "SDA0";
NET "sclk0" TNM_NET = "TNM_CLK0"; NET "sclk0" TNM_NET = "TNM_CLK0";
...@@ -242,8 +242,8 @@ NET "i_sensorpads/i_sensor_phase/mode_14bits_sync" TIG; ...@@ -242,8 +242,8 @@ NET "i_sensorpads/i_sensor_phase/mode_14bits_sync" TIG;
NET "hact_length*" TIG; NET "hact_length*" TIG;
NET "cb_*" TIG; NET "cb_*" TIG;
TIMEGRP "TG_CLK1" = pads("CLK1"); TIMEGRP "TG_CLK1" = PADS("CLK1");
TIMEGRP "TG_DCLK" = pads("DCLK"); TIMEGRP "TG_DCLK" = PADS("DCLK");
#TIMESPEC "TS_SENSORCLOCK" = FROM "TG_CLK1" TO "TG_DCLK" 14.0 ns; #TIMESPEC "TS_SENSORCLOCK" = FROM "TG_CLK1" TO "TG_DCLK" 14.0 ns;
...@@ -268,65 +268,65 @@ TIMESPEC "TS_DACK0" = FROM "DACK" TO "ALLPADS" 17 ns; ...@@ -268,65 +268,65 @@ TIMESPEC "TS_DACK0" = FROM "DACK" TO "ALLPADS" 17 ns;
TIMEGRP "TG_ALL_SYNC"= FFS RAMS MULTS; TIMEGRP "TG_ALL_SYNC"= FFS RAMS MULTS;
TIMEGRP "TG_DOUBLECYCS2"= ffs("i_mcontr/i_descrproc/seq_par*") TIMEGRP "TG_DOUBLECYCS2"= FFS("i_mcontr/i_descrproc/seq_par*")
ffs("i_mcontr/i_descrproc/sa*") FFS("i_mcontr/i_descrproc/sa*")
ffs("i_mcontr/i_descrproc/nxtTL*") FFS("i_mcontr/i_descrproc/nxtTL*")
ffs("i_mcontr/i_descrproc/tile*") FFS("i_mcontr/i_descrproc/tile*")
ffs("i_mcontr/i_descrproc/mode*") FFS("i_mcontr/i_descrproc/mode*")
ffs("i_mcontr/i_descrproc/WnR*") FFS("i_mcontr/i_descrproc/WnR*")
ffs("i_mcontr/i_descrproc/depend*") FFS("i_mcontr/i_descrproc/depend*")
ffs("i_mcontr/i_descrproc/nextFrame*") FFS("i_mcontr/i_descrproc/nextFrame*")
ffs("i_mcontr/i_descrproc/suspXfer*") FFS("i_mcontr/i_descrproc/suspXfer*")
ffs("i_mcontr/i_descrproc/lineNumSource*") FFS("i_mcontr/i_descrproc/lineNumSource*")
ffs("i_mcontr/i_descrproc/lineNumDest*") FFS("i_mcontr/i_descrproc/lineNumDest*")
ffs("i_mcontr/i_descrproc/prevStripSource*") FFS("i_mcontr/i_descrproc/prevStripSource*")
ffs("i_mcontr/i_descrproc/last_lines_reg*") FFS("i_mcontr/i_descrproc/last_lines_reg*")
ffs("i_mcontr/i_descrproc/first_tile_reg*") FFS("i_mcontr/i_descrproc/first_tile_reg*")
ffs("i_mcontr/i_descrproc/first_tile_dest*") FFS("i_mcontr/i_descrproc/first_tile_dest*")
ffs("i_mcontr/i_descrproc/nxtTFr*") FFS("i_mcontr/i_descrproc/nxtTFr*")
ffs("i_mcontr/i_descrproc/srcAtStart*") FFS("i_mcontr/i_descrproc/srcAtStart*")
mults("i_mcontr/i_descrproc/linAddr*"); MULTS("i_mcontr/i_descrproc/linAddr*");
TIMESPEC "TS_DOUBLECYCS2" = FROM "TG_DOUBLECYCS2" TO "TG_ALL_SYNC" "TS_CLK0" * 2; TIMESPEC "TS_DOUBLECYCS2" = FROM "TG_DOUBLECYCS2" TO "TG_ALL_SYNC" "TS_CLK0" * 2;
TIMEGRP "TG_FAST_SRC3"= ffs("*stepsE*") ffs("*stepsI*") ffs("*stepsDwe*"); TIMEGRP "TG_FAST_SRC3"= FFS("*stepsE*") FFS("*stepsI*") FFS("*stepsDwe*");
TIMEGRP "TG_SLOW_SRC3" = TG_ALL_SYNC EXCEPT "TG_FAST_SRC3"; TIMEGRP "TG_SLOW_SRC3" = TG_ALL_SYNC EXCEPT "TG_FAST_SRC3";
TIMEGRP "TG_DOUBLEDEST3"= ffs("i_mcontr/i_descrproc/seq_par*") TIMEGRP "TG_DOUBLEDEST3"= FFS("i_mcontr/i_descrproc/seq_par*")
ffs("i_mcontr/i_descrproc/sa*") FFS("i_mcontr/i_descrproc/sa*")
ffs("i_mcontr/i_descrproc/nxtTL*") FFS("i_mcontr/i_descrproc/nxtTL*")
ffs("i_mcontr/i_descrproc/tile*") FFS("i_mcontr/i_descrproc/tile*")
ffs("i_mcontr/i_descrproc/mode*") FFS("i_mcontr/i_descrproc/mode*")
ffs("i_mcontr/i_descrproc/WnR*") FFS("i_mcontr/i_descrproc/WnR*")
ffs("i_mcontr/i_descrproc/depend*") FFS("i_mcontr/i_descrproc/depend*")
ffs("i_mcontr/i_descrproc/nextFrame*") FFS("i_mcontr/i_descrproc/nextFrame*")
ffs("i_mcontr/i_descrproc/nextBlocksEn*") FFS("i_mcontr/i_descrproc/nextBlocksEn*")
ffs("i_mcontr/i_descrproc/suspXfer*") FFS("i_mcontr/i_descrproc/suspXfer*")
ffs("i_mcontr/i_descrproc/lineNumSource*") FFS("i_mcontr/i_descrproc/lineNumSource*")
ffs("i_mcontr/i_descrproc/lineNumDest*") FFS("i_mcontr/i_descrproc/lineNumDest*")
ffs("i_mcontr/i_descrproc/prevStripSource*") FFS("i_mcontr/i_descrproc/prevStripSource*")
ffs("i_mcontr/i_descrproc/rovr*") FFS("i_mcontr/i_descrproc/rovr*")
ffs("i_mcontr/i_descrproc/last_lines_reg*") FFS("i_mcontr/i_descrproc/last_lines_reg*")
ffs("i_mcontr/i_descrproc/first_tile_reg*") FFS("i_mcontr/i_descrproc/first_tile_reg*")
ffs("i_mcontr/i_descrproc/first_tile_dest*") FFS("i_mcontr/i_descrproc/first_tile_dest*")
ffs("i_mcontr/i_descrproc/nxtTFr*") FFS("i_mcontr/i_descrproc/nxtTFr*")
ffs("i_mcontr/i_descrproc/nxtTF_p*") FFS("i_mcontr/i_descrproc/nxtTF_p*")
ffs("i_mcontr/i_descrproc/srcAtStart*") FFS("i_mcontr/i_descrproc/srcAtStart*")
mults("i_mcontr/i_descrproc/linAddr*"); MULTS("i_mcontr/i_descrproc/linAddr*");
TIMESPEC "TS_DOUBLECYCS3" = FROM "TG_SLOW_SRC3" TO "TG_DOUBLEDEST3" "TS_CLK0" * 2; TIMESPEC "TS_DOUBLECYCS3" = FROM "TG_SLOW_SRC3" TO "TG_DOUBLEDEST3" "TS_CLK0" * 2;
## Next - redundant? ## Next - redundant?
##TIMESPEC "TS_DOUBLECYCS4" = FROM FFS("*i_chArbit/chNum*") TO "TG_DOUBLEDEST3" TS_CLK0*2; ##TIMESPEC "TS_DOUBLECYCS4" = FROM FFS("*i_chArbit/chNum*") TO "TG_DOUBLEDEST3" TS_CLK0*2;
TIMEGRP "TG_HUFFRAMS"= rams ("*i_huffman*") ; TIMEGRP "TG_HUFFRAMS"= RAMS ("*i_huffman*") ;
#FIXME: Constraint <TIMEGRP "TG_HUFFFFS" ... does not match any design objects. #FIXME: Constraint <TIMEGRP "TG_HUFFFFS" ... does not match any design objects.
TIMEGRP "TG_HUFFFFS"= ffs ("*i_huffman*") TIMEGRP "TG_HUFFFFS"= FFS ("*i_huffman*")
ffs ("*i_stuffer*") ; FFS ("*i_stuffer*") ;
TIMEGRP "TG_HUFFLATCHES"= latches ("*i_huffman*") ; TIMEGRP "TG_HUFFLATCHES"= LATCHES ("*i_huffman*") ;
# some registers in Huffman module are isolated from others through latches too - never used? # some registers in Huffman module are isolated from others through latches too - never used?
##TIMEGRP "TG_HUFFFFS_ISOLOUT" = ffs ("*i_huff_fifo/load_q"); ##TIMEGRP "TG_HUFFFFS_ISOLOUT" = FFS ("*i_huff_fifo/load_q");
TIMEGRP "TG_STUFFER_WAS_READY_EARLY" = latches ("i_compressor/i_huffman/i_stuffer_was_rdy_early") ; TIMEGRP "TG_STUFFER_WAS_READY_EARLY" = LATCHES ("i_compressor/i_huffman/i_stuffer_was_rdy_early") ;
TIMEGRP "TG_HUFF_FIFO_LOAD_Q" = ffs ("i_compressor/i_huffman/i_huff_fifo/load_q") ; TIMEGRP "TG_HUFF_FIFO_LOAD_Q" = FFS ("i_compressor/i_huffman/i_huff_fifo/load_q") ;
TIMEGRP "TG_COMPRESSOR"= ffs ("*i_compressor*") ; TIMEGRP "TG_COMPRESSOR"= FFS ("*i_compressor*") ;
### THe two below constraints are not needed, they are covered by "TS_HUFFLATCHES" and "TS_HUFFLATCHESI" ### THe two below constraints are not needed, they are covered by "TS_HUFFLATCHES" and "TS_HUFFLATCHESI"
## TIMESPEC "TS_HUFF_FIFO_LOAD_Q"= FROM "TG_STUFFER_WAS_READY_EARLY" TO "TG_HUFFFFS" "TS_CLK0" * 0.625; ## TIMESPEC "TS_HUFF_FIFO_LOAD_Q"= FROM "TG_STUFFER_WAS_READY_EARLY" TO "TG_HUFFFFS" "TS_CLK0" * 0.625;
## TIMESPEC "TS_STUFFER_WAS_READY_EARLY"= FROM "TG_HUFFFFS" TO "TG_STUFFER_WAS_READY_EARLY" "TS_CLK0" * 0.7; ## TIMESPEC "TS_STUFFER_WAS_READY_EARLY"= FROM "TG_HUFFFFS" TO "TG_STUFFER_WAS_READY_EARLY" "TS_CLK0" * 0.7;
...@@ -376,8 +376,8 @@ TIMESPEC "TS_PCLK_PCLK2X" = FROM "TNM_PCLK" TO "TNM_PCLK2X" TIG; ...@@ -376,8 +376,8 @@ TIMESPEC "TS_PCLK_PCLK2X" = FROM "TNM_PCLK" TO "TNM_PCLK2X" TIG;
TIMEGRP "TG_HIST_DOUBLE_DEST"= ffs("*hist_post*"); TIMEGRP "TG_HIST_DOUBLE_DEST"= FFS("*hist_post*");
TIMEGRP "TG_HIST_DOUBLE_SRC "= ffs("*hist_pre*"); TIMEGRP "TG_HIST_DOUBLE_SRC "= FFS("*hist_pre*");
TIMESPEC "TS_HIST_DOUBLECYC1" = FROM FFS("*hist_pre*") TO FFS("*hist_post*") "TS_CLK1" ; TIMESPEC "TS_HIST_DOUBLECYC1" = FROM FFS("*hist_pre*") TO FFS("*hist_post*") "TS_CLK1" ;
...@@ -388,10 +388,10 @@ INST "i_histogram/size_height_*" TIG; ...@@ -388,10 +388,10 @@ INST "i_histogram/size_height_*" TIG;
INST "i_histogram/minus_pos_left_*" TIG; INST "i_histogram/minus_pos_left_*" TIG;
INST "i_histogram/pos_left_is_zero*" TIG; INST "i_histogram/pos_left_is_zero*" TIG;
TIMEGRP "TG_HIST_DOUBLE2_SRC"= ffs("i_histogram/pix_cntr*"); TIMEGRP "TG_HIST_DOUBLE2_SRC"= FFS("i_histogram/pix_cntr*");
TIMEGRP "TG_HIST_DOUBLE2_DST"= ffs("i_histogram/pix_cntr*") TIMEGRP "TG_HIST_DOUBLE2_DST"= FFS("i_histogram/pix_cntr*")
ffs("i_histogram/line_started*") FFS("i_histogram/line_started*")
ffs("i_histogram/line_ended*") ; FFS("i_histogram/line_ended*") ;
TIMESPEC "TS_HIST_DOUBLECYC2" = FROM "TG_HIST_DOUBLE2_SRC" TO "TG_HIST_DOUBLE2_DST" "TS_CLK1" ; TIMESPEC "TS_HIST_DOUBLECYC2" = FROM "TG_HIST_DOUBLE2_SRC" TO "TG_HIST_DOUBLE2_DST" "TS_CLK1" ;
......
x353_1.sav
View file @ d6e9be6b
<<<<<<< x353_1.sav [*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Mon Jul 27 06:55:08 2015
[*]
[dumpfile] "/home/andrey/git/x353/simulation/x353_1-20150727004619246.lxt"
[dumpfile_mtime] "Mon Jul 27 06:47:53 2015"
[dumpfile_size] 49089165
[savefile] "/home/andrey/git/x353/x353_1.sav"
[timestart] 0 [timestart] 0
[size] 1844 1178 [size] 1823 1173
[pos] 1910 0 [pos] 1917 0
*-27.431326 555456250 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-25.064463 110293750 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
=======
[timestart] 214700000
[size] 1844 1170
[pos] 1910 0
*-24.692209 307364625 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
>>>>>>> 1.14
[treeopen] testbench353. [treeopen] testbench353.
[treeopen] testbench353.i_x353. [treeopen] testbench353.i_x353.
<<<<<<< x353_1.sav [treeopen] testbench353.i_x353.i_mcontr.
[treeopen] testbench353.i_x353.i_camsync.
[treeopen] testbench353.i_x353.i_compressor.
=======
[treeopen] testbench353.i_x353.i_imu_logger.
>>>>>>> 1.14
[treeopen] testbench353.i_x353.i_mcontr.i_descrproc.
[treeopen] testbench353.i_x353.i_sensorpads.i_sensor_phase. [treeopen] testbench353.i_x353.i_sensorpads.i_sensor_phase.
<<<<<<< x353_1.sav
[treeopen] testbench353.i_x353.i_sysinterface.i_we. [treeopen] testbench353.i_x353.i_sysinterface.i_we.
[sst_width] 335
[signals_width] 294
[sst_expanded] 1
[sst_vpaned_height] 430
@820
testbench353.TEST_TITLE[639:0]
@200
-
@800200 @800200
======= -sdram
[treeopen] testbench353.i_x353.i_sysinterface.i_we. @22
testbench353.i_x353.SDA[14:0]
@28
testbench353.i_x353.SDCAS[0]
testbench353.i_x353.SDCLKE[0]
testbench353.i_x353.SDCLK[0]
testbench353.i_x353.SDCLK_FB[0]
@22
testbench353.i_x353.SDD[15:0]
@28
testbench353.i_x353.SDLDM[0]
testbench353.i_x353.SDNCLK[0]
testbench353.i_x353.SDNCLK_FB[0]
testbench353.i_x353.SDRAS[0]
testbench353.i_x353.SDUDM[0]
testbench353.i_x353.SDWE[0]
@1000200
-sdram
@c00200 @c00200
>>>>>>> 1.14 >1
-system -system
@28 @28
testbench353.i_sensor12bits.ARO >1
testbench353.i_x353.CLK1 testbench353.i_sensor12bits.ARO[0]
testbench353.VACT >1
testbench353.i_x353.vacts_every testbench353.i_x353.CLK1[0]
testbench353.i_x353.vacts_long >1
testbench353.HACT testbench353.VACT[0]
@22 >1
testbench353.i_x353.vacts_every[0]
>1
testbench353.i_x353.vacts_long[0]
>1
testbench353.HACT[0]
@22
>1
testbench353.PXD[11:0] testbench353.PXD[11:0]
@28 @28
testbench353.DREQ >1
testbench353.DACK testbench353.DREQ[0]
>1
testbench353.DACK[0]
@22 @22
>1
testbench353.DMA_DI[31:0] testbench353.DMA_DI[31:0]
>1
testbench353.CPU_DI[31:0] testbench353.CPU_DI[31:0]
>1
testbench353.CPU_DO[31:0] testbench353.CPU_DO[31:0]
@28 @28
>1
testbench353.i_x353.cb_bayer_phase[1:0] testbench353.i_x353.cb_bayer_phase[1:0]
<<<<<<< x353_1.sav >1
testbench353.i_x353.DREQ0 testbench353.i_x353.DREQ0[0]
testbench353.i_x353.DACK0 >1
testbench353.i_x353.DREQ1 testbench353.i_x353.DACK0[0]
testbench353.i_x353.DACK1 >1
@22 testbench353.i_x353.DREQ1[0]
>1
testbench353.i_x353.DACK1[0]
@22
>1
testbench353.DMA_DI_1[31:0] testbench353.DMA_DI_1[31:0]
@28 @28
testbench353.i_x353.vacts >1
@23 testbench353.i_x353.vacts[0]
@22
>1
testbench353.i_x353.i2c_frame_no[2:0] testbench353.i_x353.i2c_frame_no[2:0]
@28 @28
testbench353.i_x353.i_irq_smart.is_compressing >1
testbench353.i_x353.i_irq_smart.wait_frame_sync testbench353.i_x353.i_irq_smart.is_compressing[0]
testbench353.IRQ >1
testbench353.i_x353.compressor_eot testbench353.i_x353.i_irq_smart.wait_frame_sync[0]
testbench353.i_x353.compressor_done_compress >1
testbench353.i_x353.compressor_done_input testbench353.IRQ[0]
testbench353.i_x353.compressor_done_pulse >1
testbench353.i_x353.compressor_started testbench353.i_x353.compressor_eot[0]
@22 >1
testbench353.i_x353.compressor_done_compress[0]
>1
testbench353.i_x353.compressor_done_input[0]
>1
testbench353.i_x353.compressor_done_pulse[0]
>1
testbench353.i_x353.compressor_started[0]
@22
>1
testbench353.i_x353.i_compressor.imgptr[23:0] testbench353.i_x353.i_compressor.imgptr[23:0]
@28 @28
testbench353.i_x353.i_irq_smart.compressor_done >1
testbench353.i_x353.i_irq_smart.compressor_fifo_done testbench353.i_x353.i_irq_smart.compressor_done[0]
testbench353.i_x353.i_irq_smart.delaying_done_irq >1
testbench353.i_x353.i_irq_smart.compressor_fifo_done[0]
>1
testbench353.i_x353.i_irq_smart.delaying_done_irq[0]
@22 @22
>1
testbench353.i_x353.i_irq_smart.di[15:0] testbench353.i_x353.i_irq_smart.di[15:0]
@28 @28
testbench353.i_x353.i_irq_smart.done_request >1
testbench353.i_x353.i_irq_smart.end_postpone_fs testbench353.i_x353.i_irq_smart.done_request[0]
testbench353.i_x353.i_irq_smart.fifo_empty >1
testbench353.i_x353.i_irq_smart.finished testbench353.i_x353.i_irq_smart.end_postpone_fs[0]
testbench353.i_x353.i_irq_smart.frame_sync >1
testbench353.i_x353.i_irq_smart.fs_postponed testbench353.i_x353.i_irq_smart.fifo_empty[0]
testbench353.i_x353.i_irq_smart.irq >1
testbench353.i_x353.i_irq_smart.is_compressing testbench353.i_x353.i_irq_smart.finished[0]
testbench353.i_x353.i_compressor.eot >1
testbench353.i_x353.i_compressor.i_huffman.last_block testbench353.i_x353.i_irq_smart.frame_sync[0]
testbench353.i_x353.i_compressor.i_huffman.gotLastBlock >1
testbench353.i_x353.i_compressor.color_first testbench353.i_x353.i_irq_smart.fs_postponed[0]
testbench353.i_x353.i_compressor.color_last >1
testbench353.i_x353.i_compressor.i_encoderDCAC.lasti testbench353.i_x353.i_irq_smart.irq[0]
testbench353.i_x353.i_compressor.i_encoderDCAC.lasto >1
testbench353.i_x353.i_irq_smart.is_finishing testbench353.i_x353.i_irq_smart.is_compressing[0]
testbench353.i_x353.i_irq_smart.rst >1
testbench353.i_x353.i_irq_smart.wait_fifo testbench353.i_x353.i_compressor.eot[0]
testbench353.i_x353.i_irq_smart.wait_frame_sync >1
testbench353.i_x353.i_irq_smart.was_finishing testbench353.i_x353.i_compressor.i_huffman.last_block[0]
testbench353.i_x353.i_irq_smart.will_delay_done_irq >1
testbench353.i_x353.i_irq_smart.will_postpone_fs testbench353.i_x353.i_compressor.i_huffman.gotLastBlock[0]
testbench353.i_x353.i_camsync.restart >1
testbench353.i_x353.i_compressor.compressor_started testbench353.i_x353.i_compressor.color_first[0]
testbench353.i_x353.i_compressor.stuffer_done >1
testbench353.i_x353.i_compressor.i_stuffer.flush testbench353.i_x353.i_compressor.color_last[0]
testbench353.i_x353.i_compressor.i_stuffer.flush_end >1
testbench353.i_x353.i_compressor.i_stuffer.flush_end_delayed testbench353.i_x353.i_compressor.i_encoderDCAC.lasti[0]
testbench353.i_x353.i_compressor.i_stuffer.flush_now >1
testbench353.i_x353.i_compressor.i_stuffer.flushing testbench353.i_x353.i_compressor.i_encoderDCAC.lasto[0]
@1000200 >1
======= testbench353.i_x353.i_irq_smart.is_finishing[0]
testbench353.i_x353.DREQ0 >1
testbench353.i_x353.DACK0 testbench353.i_x353.i_irq_smart.rst[0]
testbench353.i_x353.DREQ1 >1
testbench353.i_x353.DACK1 testbench353.i_x353.i_irq_smart.wait_fifo[0]
@22 >1
testbench353.DMA_DI_1[31:0] testbench353.i_x353.i_irq_smart.wait_frame_sync[0]
@1401200 >1
>>>>>>> 1.14 testbench353.i_x353.i_irq_smart.was_finishing[0]
-system >1
@c00022 testbench353.i_x353.i_irq_smart.will_delay_done_irq[0]
testbench353.i_x353.D[31:0] >1
<<<<<<< x353_1.sav testbench353.i_x353.i_irq_smart.will_postpone_fs[0]
@28 >1
(0)testbench353.i_x353.D[31:0] testbench353.i_x353.i_camsync.restart[0]
(1)testbench353.i_x353.D[31:0] >1
(2)testbench353.i_x353.D[31:0] testbench353.i_x353.i_compressor.compressor_started[0]
(3)testbench353.i_x353.D[31:0] >1
(4)testbench353.i_x353.D[31:0] testbench353.i_x353.i_compressor.stuffer_done[0]
(5)testbench353.i_x353.D[31:0] >1
(6)testbench353.i_x353.D[31:0] testbench353.i_x353.i_compressor.i_stuffer.flush[0]
(7)testbench353.i_x353.D[31:0] >1
(8)testbench353.i_x353.D[31:0] testbench353.i_x353.i_compressor.i_stuffer.flush_end[0]
(9)testbench353.i_x353.D[31:0] >1
(10)testbench353.i_x353.D[31:0] testbench353.i_x353.i_compressor.i_stuffer.flush_end_delayed[0]
(11)testbench353.i_x353.D[31:0] >1
(12)testbench353.i_x353.D[31:0] testbench353.i_x353.i_compressor.i_stuffer.flush_now[0]
(13)testbench353.i_x353.D[31:0] >1
(14)testbench353.i_x353.D[31:0] testbench353.i_x353.i_compressor.i_stuffer.flushing[0]
(15)testbench353.i_x353.D[31:0] @1401200
(16)testbench353.i_x353.D[31:0] >1
(17)testbench353.i_x353.D[31:0] -DREQ0[0]
(18)testbench353.i_x353.D[31:0]
(19)testbench353.i_x353.D[31:0]
(20)testbench353.i_x353.D[31:0]
(21)testbench353.i_x353.D[31:0]
(22)testbench353.i_x353.D[31:0]
(23)testbench353.i_x353.D[31:0]
(24)testbench353.i_x353.D[31:0]
(25)testbench353.i_x353.D[31:0]
(26)testbench353.i_x353.D[31:0]
(27)testbench353.i_x353.D[31:0]
(28)testbench353.i_x353.D[31:0]
(29)testbench353.i_x353.D[31:0]
(30)testbench353.i_x353.D[31:0]
(31)testbench353.i_x353.D[31:0]
@1401200
-group_end
@800200
=======
@28
(0)testbench353.i_x353.D[31:0]
(1)testbench353.i_x353.D[31:0]
(2)testbench353.i_x353.D[31:0]
(3)testbench353.i_x353.D[31:0]
(4)testbench353.i_x353.D[31:0]
(5)testbench353.i_x353.D[31:0]
(6)testbench353.i_x353.D[31:0]
(7)testbench353.i_x353.D[31:0]
(8)testbench353.i_x353.D[31:0]
(9)testbench353.i_x353.D[31:0]
(10)testbench353.i_x353.D[31:0]
(11)testbench353.i_x353.D[31:0]
(12)testbench353.i_x353.D[31:0]
(13)testbench353.i_x353.D[31:0]
(14)testbench353.i_x353.D[31:0]
(15)testbench353.i_x353.D[31:0]
(16)testbench353.i_x353.D[31:0]
(17)testbench353.i_x353.D[31:0]
(18)testbench353.i_x353.D[31:0]
(19)testbench353.i_x353.D[31:0]
(20)testbench353.i_x353.D[31:0]
(21)testbench353.i_x353.D[31:0]
(22)testbench353.i_x353.D[31:0]
(23)testbench353.i_x353.D[31:0]
(24)testbench353.i_x353.D[31:0]
(25)testbench353.i_x353.D[31:0]
(26)testbench353.i_x353.D[31:0]
(27)testbench353.i_x353.D[31:0]
(28)testbench353.i_x353.D[31:0]
(29)testbench353.i_x353.D[31:0]
(30)testbench353.i_x353.D[31:0]
(31)testbench353.i_x353.D[31:0]
@1401200
-group_end
@c00200 @c00200
>>>>>>> 1.14 >0
-color_conversion -mcontr
@22 @28
testbench353.i_x353.i_compressor.i_color_proc.nblocks[17:0] testbench353.i_x353.UDQS[0]
@28 testbench353.i_x353.LDQS[0]
testbench353.i_x353.i_compressor.i_color_proc.noMoreData @200
testbench353.i_x353.i_compressor.i_color_proc.go >1
@22 -DREQ1[0]
testbench353.i_x353.i_compressor.i_color_proc.bcntr[17:0] >1
@28 -DACK1[0]
testbench353.i_x353.i_compressor.i_color_proc.ccv_start_en @22
testbench353.i_x353.i_compressor.i_color_proc.sdram_rdy >1
testbench353.i_x353.i_compressor.i_color_proc.all_ready testbench353.DMA_DI_1[31:0]
@22
testbench353.i_x353.i_compressor.i_color_proc.seq_cntr[8:0]
@28
testbench353.i_x353.i_compressor.i_color_proc.pre_first_pixel
testbench353.i_x353.i_compressor.i_color_proc.first_pixel
testbench353.i_x353.i_compressor.i_color_proc.last0
testbench353.i_x353.i_compressor.i_color_proc.last
@22
testbench353.i_x353.i_compressor.cmprs_mode[3:0]
testbench353.i_x353.i_compressor.component_color
@28
testbench353.i_x353.i_compressor.component_first
testbench353.i_x353.i_compressor.component_lastinmb
@800022
testbench353.i_x353.i_compressor.component_num[2:0]
@28
(0)testbench353.i_x353.i_compressor.component_num[2:0]
(1)testbench353.i_x353.i_compressor.component_num[2:0]
(2)testbench353.i_x353.i_compressor.component_num[2:0]
@1001200
-group_end
@22
testbench353.i_x353.i_compressor.converter_type[2:0]
testbench353.i_x353.i_compressor.color_tn[2:0]
@28
testbench353.i_x353.i_compressor.i_color_proc.clk
@22
testbench353.i_x353.i_compressor.color_d[9:0]
testbench353.i_x353.i_compressor.color_avr[8:0]
@28
testbench353.i_x353.i_compressor.color_dv
@22
testbench353.i_x353.i_compressor.i_color_proc.converter_type_r[2:0]
testbench353.i_x353.i_compressor.i_color_proc.c_in[8:0]
testbench353.i_x353.i_compressor.i_color_proc.c_out[8:0]
@28
testbench353.i_x353.i_compressor.i_color_proc.cwe
testbench353.i_x353.i_compressor.i_color_proc.buf_sel
testbench353.i_x353.i_compressor.i_color_proc.ccv_out_start
testbench353.i_x353.i_compressor.i_color_proc.ccv_start_en
testbench353.i_x353.i_compressor.i_color_proc.go
@22
testbench353.i_x353.i_compressor.i_color_proc.do[9:0]
@28
testbench353.i_x353.i_compressor.i_color_proc.ds
testbench353.i_x353.i_compressor.i_color_proc.dv
@1000200
-color_conversion
@c00200
-channel0
@28
testbench353.i_x353.i_sensorpix.hact
@c00022
testbench353.i_x353.i_sensorpix.pxd[15:0]
@28
(0)testbench353.i_x353.i_sensorpix.pxd[15:0]
(1)testbench353.i_x353.i_sensorpix.pxd[15:0]
(2)testbench353.i_x353.i_sensorpix.pxd[15:0]
(3)testbench353.i_x353.i_sensorpix.pxd[15:0]
(4)testbench353.i_x353.i_sensorpix.pxd[15:0]
(5)testbench353.i_x353.i_sensorpix.pxd[15:0]
(6)testbench353.i_x353.i_sensorpix.pxd[15:0]
(7)testbench353.i_x353.i_sensorpix.pxd[15:0]
(8)testbench353.i_x353.i_sensorpix.pxd[15:0]
(9)testbench353.i_x353.i_sensorpix.pxd[15:0]
(10)testbench353.i_x353.i_sensorpix.pxd[15:0]
(11)testbench353.i_x353.i_sensorpix.pxd[15:0]
(12)testbench353.i_x353.i_sensorpix.pxd[15:0]
(13)testbench353.i_x353.i_sensorpix.pxd[15:0]
(14)testbench353.i_x353.i_sensorpix.pxd[15:0]
(15)testbench353.i_x353.i_sensorpix.pxd[15:0]
@1401200
-group_end
@28 @28
testbench353.i_x353.i_sensorpix.hact_out >0
testbench353.i_x353.i_sensorpix.dwe testbench353.i_x353.i_mcontr.WnR[0]
@22 @22
testbench353.i_x353.i_sensorpix.do[15:0] testbench353.i_x353.i_mcontr.am[3:0]
testbench353.i_x353.i_mcontr.as[3:0]
testbench353.i_x353.i_mcontr.bmad0[8:0]
testbench353.i_x353.i_mcontr.bmad1[8:0]
testbench353.i_x353.i_mcontr.bmad2[8:0]
testbench353.i_x353.i_mcontr.bmad3[8:0]
testbench353.i_x353.i_mcontr.bonded[3:0]
testbench353.i_x353.i_mcontr.ch0a[9:0] testbench353.i_x353.i_mcontr.ch0a[9:0]
@28 @28
testbench353.i_x353.i_mcontr.ch0clk testbench353.i_x353.i_mcontr.ch0clk[0]
@22 @22
testbench353.i_x353.i_mcontr.ch0di[15:0] testbench353.i_x353.i_mcontr.ch0di[15:0]
@28 @28
testbench353.i_x353.i_mcontr.ch0en testbench353.i_x353.i_mcontr.ch0en[0]
@22 @22
testbench353.i_x353.i_mcontr.ch0rd[31:0] testbench353.i_x353.i_mcontr.ch0rd[31:0]
@28 @28
testbench353.i_x353.i_mcontr.ch0rdy testbench353.i_x353.i_mcontr.ch0rdy[0]
testbench353.i_x353.i_mcontr.ch0we[0]
@22 @22
testbench353.i_mt46v16m16fg.Dq[15:0] testbench353.i_x353.i_mcontr.ch1a[9:0]
@28 @28
testbench353.i_mt46v16m16fg.Cas_n testbench353.i_x353.i_mcontr.ch1clk[0]
testbench353.i_mt46v16m16fg.We_n
testbench353.i_mt46v16m16fg.Clk
@22 @22
testbench353.i_x353.i_mcontr.ch0a[9:0] testbench353.i_x353.i_mcontr.ch1do[15:0]
@28 @28
testbench353.i_x353.i_mcontr.ch0we testbench353.i_x353.i_mcontr.ch1rdy[0]
testbench353.i_x353.i_mcontr.ch1we[0]
@22 @22
testbench353.i_x353.i_mcontr.ch0di[15:0] testbench353.i_x353.i_mcontr.ch2a[10:0]
@28
testbench353.i_x353.i_mcontr.readNextFrame0
testbench353.i_x353.i_mcontr.stch0
testbench353.i_x353.i_sensorpix.wpage
testbench353.i_x353.i_sensorpix.incbwa
@1401200
-channel0
@c00200
-aaa
@28 @28
testbench353.i_x353.i_sensorpads.clk testbench353.i_x353.i_mcontr.ch2clk[0]
testbench353.i_x353.i_sensorpads.hact
testbench353.i_x353.i_sensorpads.vact
testbench353.i_x353.i_sensorpads.ihact
testbench353.i_x353.i_sensorpads.vacts
@22 @22
testbench353.i_x353.i_sensorpads.pxd[11:0] testbench353.i_x353.i_mcontr.ch2do[7:0]
testbench353.i_x353.i_sensorpads.ipxd[15:0]
@1401200
-aaa
@c00200
-quantizer
-sensor_phase
@22
testbench353.i_x353.i_sensorpads.i_sensor_phase.svact_filter_cntr[7:0]
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.en_svact_sync
testbench353.i_x353.i_sensorpads.i_sensor_phase.pre_svact
testbench353.i_x353.i_sensorpads.i_sensor_phase.pre_svact_d
testbench353.i_x353.i_sensorpads.i_sensor_phase.svact
@800022
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_q0_d[3:0]
@28
(3)testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_q0_d[3:0]
@1001200
-group_end
@800028
testbench353.i_x353.i_sensorpads.i_sensor_phase.shact_zero[1:0]
@28
(0)testbench353.i_x353.i_sensorpads.i_sensor_phase.shact_zero[1:0]
@1001200
-group_end
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_selected_2_cycles
testbench353.i_x353.i_sensorpads.i_sensor_phase.pre_shact
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_regen
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_regen_isync
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_regen_sync
testbench353.i_x353.i_sensorpads.clk_sel
testbench353.i_x353.i_sensorpads.i_sensor_phase.iclk
testbench353.i_x353.i_sensorpads.i_sensor_phase.wcmd
testbench353.i_x353.i_sensorpads.i_sensor_phase.dcm_en
testbench353.i_x353.i_sensorpads.i_sensor_phase.dcm_rst
testbench353.i_x353.i_sensorpads.i_sensor_phase.sync_alt
testbench353.i_x353.BPF
testbench353.i_sensor12bits.DCLK
testbench353.i_x353.i_sensorpads.i_sensor_phase.wcmd
@22
testbench353.i_x353.idi[31:0]
testbench353.i_x353.i_sensorpads.i_sensor_phase.cmd[5:0]
testbench353.i_x353.PXD[9:0]
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.HACT
testbench353.i_x353.i_sensorpads.i_sensor_phase.VACT
testbench353.i_x353.i_sensorpads.i_sensor_phase.mode_12bits
testbench353.i_x353.i_sensorpads.i_sensor_phase.mode_14bits
testbench353.i_x353.i_sensorpads.i_sensor_phase.mode_alt
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_vd
testbench353.i_x353.i_sensorpads.i_sensor_phase.gclk_idata
testbench353.i_x353.i_sensorpads.i_sensor_phase.en_idata
testbench353.i_x353.i_sensorpads.i_sensor_phase.sclk
testbench353.i_x353.i_sensorpads.i_sensor_phase.vact_vd
testbench353.i_x353.i_sensorpads.i_sensor_phase.phase_hact_sel_sync[2:0]
testbench353.i_x353.i_sensorpads.i_sensor_phase.phase_hact_sel[2:0]
testbench353.i_x353.i_sensorpads.i_sensor_phase.vact_selected_2_cycles
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_selected
testbench353.i_x353.i_sensorpads.i_sensor_phase.shact
testbench353.i_x353.i_sensorpads.i_sensor_phase.svact
@22
testbench353.i_x353.i_sensorpads.i_sensor_phase.sdo[13:0]
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.sim_rst
testbench353.i_x353.i_sensorpads.i_sensor_phase.reset_fifo_in_cntr
@22
testbench353.i_x353.i_sensorpads.i_sensor_phase.idi14[13:0]
testbench353.i_x353.i_sensorpads.i_sensor_phase.fifo_data_in_addr[3:0]
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_selected_2_cycles
@22
testbench353.i_x353.i_sensorpads.i_sensor_phase.fifo_hact_in_addr[3:0]
testbench353.i_x353.i_sensorpads.i_sensor_phase.fifo_data_in_addr_saved[3:0]
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.dcm_done
testbench353.i_x353.i_sensorpads.i_sensor_phase.reset_out_fifo
@22
testbench353.i_x353.i_sensorpads.i_sensor_phase.fifo_out_addr[3:0]
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.dcm_rst_cmd
@800028
testbench353.i_x353.i_sensorpads.i_sensor_phase.dcm_in_locked[1:0]
@28
(0)testbench353.i_x353.i_sensorpads.i_sensor_phase.dcm_in_locked[1:0]
@1001200
-group_end
@22
testbench353.i_x353.i_sensorpads.i_sensor_phase.dcm_locked_cntr[3:0]
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.dcm_fifo_locked
testbench353.i_x353.i_sensorpads.i_sensor_phase.locked
testbench353.i_x353.i_sensorpads.i_sensor_phase.pre_shact
@22
testbench353.i_x353.i_sensorpads.i_sensor_phase.pre_sdo[13:0]
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.reset_fifo_in_cntr
@22
testbench353.i_x353.i_sensorpads.hact_length[13:0]
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_count[13:0]
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.hact_count_zero
@1401200
-sensor_phase
@c00200
-hist
@800022
testbench353.i_x353.i_histogram.dvld2x[3:0]
@28
(0)testbench353.i_x353.i_histogram.dvld2x[3:0]
(1)testbench353.i_x353.i_histogram.dvld2x[3:0]
(2)testbench353.i_x353.i_histogram.dvld2x[3:0]
(3)testbench353.i_x353.i_histogram.dvld2x[3:0]
@22
testbench353.i_x353.i_histogram.minus_pos_left[13:1]
@28
testbench353.i_x353.i_histogram.pos_left_is_zero
@22
testbench353.i_x353.i_histogram.pos_left[13:1]
testbench353.i_x353.i_histogram.size_width[13:1]
testbench353.i_x353.i_histogram.pix_cntr[13:1]
@1001200
-group_end
@c00028
testbench353.i_x353.i_histogram.line_run_s[2:0]
@28
(0)testbench353.i_x353.i_histogram.line_run_s[2:0]
(1)testbench353.i_x353.i_histogram.line_run_s[2:0]
(2)testbench353.i_x353.i_histogram.line_run_s[2:0]
@1401200
-group_end
@28
testbench353.i_x353.i_histogram.line_start
testbench353.i_x353.i_histogram.line_start_posl_zero
testbench353.i_x353.i_histogram.line_started
testbench353.i_x353.i_histogram.line_ended
testbench353.i_x353.i_histogram.window_on
@800022
testbench353.i_x353.i_histogram.hist_seq[5:0]
@28
(0)testbench353.i_x353.i_histogram.hist_seq[5:0]
(1)testbench353.i_x353.i_histogram.hist_seq[5:0]
(2)testbench353.i_x353.i_histogram.hist_seq[5:0]
(3)testbench353.i_x353.i_histogram.hist_seq[5:0]
(4)testbench353.i_x353.i_histogram.hist_seq[5:0]
(5)testbench353.i_x353.i_histogram.hist_seq[5:0]
@1001200
-group_end
@28
testbench353.i_x353.i_histogram.line_end
testbench353.i_x353.i_sensortrig.ff_count_eq0
testbench353.i_x353.i_sensortrig.vacts_in
testbench353.i_x353.i_sensortrig.state3
testbench353.i_x353.i_sensortrig.xfer_over
testbench353.i_x353.i_sensortrig.done
@22
testbench353.i_x353.i_sensortrig.nlines[13:0]
testbench353.i_x353.i_sensortrig.lines_left[13:0]
@28
testbench353.i_x353.line_run
@22
testbench353.i_x353.ipxd_ts[15:0]
@800028
testbench353.i_x353.sr_sensortrig[2:0]
@28
(0)testbench353.i_x353.sr_sensortrig[2:0]
(1)testbench353.i_x353.sr_sensortrig[2:0]
(2)testbench353.i_x353.sr_sensortrig[2:0]
testbench353.i_x353.line_run
@1001200
-group_end
@28
testbench353.i_x353.da_hist_next
testbench353.i_x353.i_histogram.frame_start
testbench353.i_x353.i_histogram.frame_started
testbench353.i_x353.i_histogram.hist_bank
testbench353.i_x353.i_histogram.di_vld
@22
testbench353.i_x353.i_histogram.di[15:0]
@28
testbench353.i_x353.i_histogram.window_on
testbench353.i_x353.i_sensortrig.vacts_in
testbench353.i_x353.i_sensortrig.vacts_out
testbench353.i_x353.i_histogram.init_hist
testbench353.i_x353.i_histogram.init_hist_d
testbench353.i_x353.i_histogram.frame_run
@800028
testbench353.i_x353.i_histogram.frame_run_s[2:0]
@28
(0)testbench353.i_x353.i_histogram.frame_run_s[2:0]
(1)testbench353.i_x353.i_histogram.frame_run_s[2:0]
(2)testbench353.i_x353.i_histogram.frame_run_s[2:0]
@1001200
-group_end
@28
testbench353.i_x353.i_histogram.pclk2x
testbench353.i_x353.frame_run
testbench353.i_x353.i_sensortrig.state2
testbench353.i_x353.i_sensortrig.xfer_over
testbench353.i_x353.i_sensortrig.xfer_over_irq
testbench353.i_x353.i_sensortrig.pclk
@1401200
-hist
@c00200
-stuffer_was_ready_early
@28
testbench353.i_x353.i_compressor.i_huffman.en2x
testbench353.i_x353.i_compressor.i_stuffer.rdy_rega
testbench353.i_x353.i_compressor.i_stuffer.rdy_regb
testbench353.i_x353.i_compressor.i_stuffer.rdy_regc
testbench353.i_x353.i_compressor.i_stuffer.rdy_regd
testbench353.i_x353.i_compressor.i_huffman.rdy
testbench353.i_x353.i_compressor.i_huffman.stuffer_was_rdy
testbench353.i_x353.i_compressor.i_huffman.i_huff_fifo.dav
testbench353.i_x353.i_compressor.i_huffman.i_huff_fifo.want_read
testbench353.i_x353.i_compressor.i_huffman.i_huff_fifo.re_r
testbench353.i_x353.i_compressor.i_huffman.tables_re
testbench353.i_x353.i_compressor.i_huffman.i_huff_fifo.load_q
testbench353.i_x353.i_compressor.i_huffman.i_huff_fifo.clk
@1401200
-stuffer_was_ready_early
@c00200
-compressor
@c00022
testbench353.i_x353.i_mcontr.i_descrproc.dest_bond_en[3:0]
@28 @28
(0)testbench353.i_x353.i_mcontr.i_descrproc.dest_bond_en[3:0] testbench353.i_x353.i_mcontr.ch2rdy[0]
(1)testbench353.i_x353.i_mcontr.i_descrproc.dest_bond_en[3:0] testbench353.i_x353.i_mcontr.ch2we[0]
(2)testbench353.i_x353.i_mcontr.i_descrproc.dest_bond_en[3:0] testbench353.i_x353.i_mcontr.ch3en[0]
(3)testbench353.i_x353.i_mcontr.i_descrproc.dest_bond_en[3:0]
@1401200
-group_end
@c00022
testbench353.i_x353.i_mcontr.i_descrproc.bonded[3:0]
@28
(0)testbench353.i_x353.i_mcontr.i_descrproc.bonded[3:0]
(1)testbench353.i_x353.i_mcontr.i_descrproc.bonded[3:0]
(2)testbench353.i_x353.i_mcontr.i_descrproc.bonded[3:0]
(3)testbench353.i_x353.i_mcontr.i_descrproc.bonded[3:0]
@1401200
-group_end
@28
testbench353.i_x353.i_compressor.bonded
testbench353.i_x353.i_compressor.i_compr_ifc.rcs[1:0]
@22
testbench353.i_x353.i_compressor.i_compr_ifc.ntiles[17:0]
testbench353.i_x353.i_compressor.i_color_proc.bcntr[17:0]
testbench353.i_x353.i_compressor.i_color_proc.nblocks[17:0]
@28
testbench353.i_x353.HACT
testbench353.i_x353.i_compressor.chInitOnehot2
testbench353.i_x353.i_compressor.cmprs_en
testbench353.i_x353.i_compressor.inc_sdrama
testbench353.i_x353.i_compressor.pxrdy
testbench353.i_x353.i_compressor.nxtpage
testbench353.i_x353.i_compressor.eot
testbench353.i_x353.i_compressor.confirmFrame2Compressor
testbench353.i_x353.i_compressor.compressor_starting[1:0]
testbench353.i_x353.i_compressor.compressor_started
testbench353.i_x353.i_compressor.pre_go_single
testbench353.i_x353.i_compressor.go_single
testbench353.i_x353.i_compressor.go_rq
testbench353.i_x353.i_compressor.vacts_long
testbench353.i_x353.i_compressor.vlong
testbench353.i_x353.i_compressor.is_compressing
testbench353.i_x353.i_compressor.is_compressing_d
testbench353.i_x353.i_mcontr.readNextFrame2
testbench353.i_x353.i_compressor.i_color_proc.bcntrIsZero
@22
testbench353.i_x353.i_compressor.i_stuffer.imgsz32[19:0]
testbench353.i_x353.i_compressor.i_stuffer.imgptr[23:0]
@28
testbench353.i_x353.i_compressor.i_stuffer.inc_imgsz32
testbench353.i_x353.i_compressor.i_stuffer.inc_size_count2316
testbench353.i_x353.i_compressor.flush
testbench353.i_x353.i_compressor.done_compress
testbench353.i_x353.i_compressor.clk
testbench353.i_x353.i_compressor.stuffer_done
testbench353.i_x353.i_compressor.i_compr_ifc.cmprs_en_s
@22
testbench353.i_x353.i_compressor.i_compr_ifc.cmprs_en_timeout[6:0]
@28
testbench353.i_x353.i_compressor.i_compr_ifc.cmprs_en_finish
testbench353.i_x353.i_compressor.i_compr_ifc.cmprs_en_long
testbench353.i_x353.i_compressor.i_compr_ifc.force_flush1
testbench353.i_x353.i_compressor.i_compr_ifc.force_flush
testbench353.i_x353.i_compressor.i_stuffer.flushing
testbench353.i_x353.i_compressor.i_stuffer.en
testbench353.i_x353.i_compressor.i_stuffer.flush_end
@22
testbench353.i_x353.i_compressor.i_stuffer.stage2_bits[4:0]
@28
testbench353.i_x353.i_compressor.i_stuffer.rdy
testbench353.i_x353.i_compressor.i_stuffer.stb
testbench353.i_x353.i_compressor.i_stuffer.stage1_full
testbench353.i_x353.i_compressor.stuffer_done
testbench353.i_x353.i_compressor.i_stuffer.size_out[2:0]
testbench353.i_x353.i_compressor.i_stuffer.flush_end
testbench353.i_x353.i_compressor.i_stuffer.start_sizeout
testbench353.i_x353.i_compressor.i_stuffer.done
@22
testbench353.i_x353.i_compressor.i_stuffer.etrax_dma[3:0]
@28
testbench353.i_x353.i_compressor.i_stuffer.time_out
testbench353.i_x353.i_compressor.i_stuffer.trailer
testbench353.i_x353.i_compressor.i_stuffer.start_time_out
testbench353.i_x353.i_compressor.abort_compress
@1401200
-group_end
@c00200
-irq_smart
@28
testbench353.i_x353.i_irq_smart.frame_sync
testbench353.i_x353.i_irq_smart.irq
testbench353.i_x353.i_irq_smart.fifo_empty
testbench353.i_x353.i_irq_smart.is_compressing
testbench353.i_x353.i_irq_smart.compressor_done
testbench353.i_x353.i_irq_smart.is_finishing
testbench353.i_x353.i_irq_smart.delaying_done_irq
testbench353.i_x353.i_irq_smart.fs_postponed
testbench353.i_x353.i_irq_smart.frame_sync
testbench353.i_x353.i_irq_smart.compressor_done
testbench353.i_x353.i_irq_smart.compressor_fifo_done
testbench353.i_x353.i_irq_smart.done_request
testbench353.i_x353.i_irq_smart.rst
testbench353.i_x353.i_irq_smart.sclk
testbench353.i_x353.i_irq_smart.wait_fifo
testbench353.i_x353.i_irq_smart.wait_frame_sync
@1401200
-irq_smart
@c00200
-noMoreData
@22 @22
testbench353.i_x353.i_compressor.ntiles[17:0] testbench353.i_x353.i_mcontr.ch3maddr[6:0]
testbench353.i_x353.i_compressor.i_color_proc.nblocks[17:0]
testbench353.i_x353.i_compressor.i_color_proc.bcntr[17:0]
@28 @28
testbench353.i_x353.i_compressor.i_color_proc.bcntrIsZero testbench353.i_x353.i_mcontr.ch3owe[0]
testbench353.i_x353.i_compressor.i_color_proc.eot testbench353.i_x353.i_mcontr.ch3page[1:0]
testbench353.i_x353.i_mcontr.readNextFrame2
@c00022
testbench353.i_x353.i_mcontr.i_descrproc.nextBlocksEn[3:0]
@28
(0)testbench353.i_x353.i_mcontr.i_descrproc.nextBlocksEn[3:0]
(1)testbench353.i_x353.i_mcontr.i_descrproc.nextBlocksEn[3:0]
(2)testbench353.i_x353.i_mcontr.i_descrproc.nextBlocksEn[3:0]
(3)testbench353.i_x353.i_mcontr.i_descrproc.nextBlocksEn[3:0]
@1401200
-group_end
@22 @22
testbench353.i_x353.i_mcontr.i_descrproc.tileX[9:0] testbench353.i_x353.i_mcontr.ch3rd[31:0]
testbench353.i_x353.i_mcontr.i_descrproc.tileY[13:0] testbench353.i_x353.i_mcontr.chInitOnehot[3:0]
testbench353.SDD[15:0]
@28
testbench353.i_x353.i_compressor.i_color_proc.memWasInit
testbench353.i_x353.i_compressor.go_rq
testbench353.i_x353.i_compressor.not_vlong1_or_not_bonded
testbench353.i_x353.i_compressor.is_compressing
testbench353.i_x353.i_compressor.i_color_proc.eof_rq
testbench353.i_x353.i_compressor.noMoreData
testbench353.i_x353.i_compressor.eot_real
testbench353.i_x353.i_compressor.eot
testbench353.i_x353.i_compressor.go_single
testbench353.i_x353.i_compressor.i_color_proc.go
testbench353.i_x353.i_compressor.i_color_proc.sdram_next
testbench353.i_x353.i_compressor.confirm
testbench353.i_x353.i_compressor.i_color_proc.sdram_rdy
testbench353.i_x353.i_compressor.inc_sdrama
testbench353.i_x353.i_compressor.clk
testbench353.i_x353.cb_break_frames
testbench353.i_x353.i_compressor.i_color_proc.noMoreData
testbench353.i_x353.i_compressor.nextBlocksEn
testbench353.i_x353.i_compressor.nextBlocksEnS[1:0]
testbench353.i_x353.i_compressor.confirm_en
testbench353.i_x353.i_compressor.confirm
testbench353.i_x353.i_compressor.pxrdy
testbench353.i_x353.i_compressor.i_color_proc.tim2next
@1401200
-noMoreData
@c00200
-vacts_filter
@28
testbench353.i_x353.i_sensorpads.i_sensor_phase.reset_fifo_in_cntr
@800022
testbench353.i_sensor12bits.state[3:0]
@28
(0)testbench353.i_sensor12bits.state[3:0]
(1)testbench353.i_sensor12bits.state[3:0]
(2)testbench353.i_sensor12bits.state[3:0]
(3)testbench353.i_sensor12bits.state[3:0]
@1001200
-group_end
@28
testbench353.i_sensor12bits.stopped
testbench353.i_sensor12bits.stoppedd
testbench353.i_sensor12bits.ARO
testbench353.i_x353.VACT
testbench353.i_x353.i_sensortrig.vacts_dly_on
testbench353.i_x353.i_sensortrig.nxt_lf
testbench353.i_x353.i_sensortrig.nxt_line
@22
testbench353.i_x353.i_sensortrig.cmd[3:0]
testbench353.i_x353.i_sensortrig.vact_dly[13:0]
@28
testbench353.i_x353.i_sensortrig.framesync_dly
testbench353.i_x353.i_sensorpads.vacts
testbench353.i_x353.cb_sensor_trigger
testbench353.i_x353.i_sensorpads.i_sensor_phase.en_svact
testbench353.i_x353.i_sensorpads.i_sensor_phase.pre_svact_outfifo
testbench353.i_x353.i_sensorpads.i_sensor_phase.pre_svact
testbench353.i_x353.i_sensorpads.i_sensor_phase.pre_svact_d
testbench353.i_x353.i_sensorpads.i_sensor_phase.svact
@22
testbench353.i_x353.i_camsync.wen[3:0]
@28
testbench353.i_x353.i_camsync.start
testbench353.i_x353.i_camsync.trigger1
testbench353.i_x353.i_camsync.trigger
testbench353.i_x353.i_camsync.input_use_intern
testbench353.i_x353.i_camsync.trigger_condition
@22
testbench353.i_x353.i_camsync.repeat_period[31:0]
testbench353.i_x353.i_camsync.restart_cntr[31:0]
@28
testbench353.i_x353.sensor_trigger
testbench353.i_x353.ARO
testbench353.i_x353.vacts
testbench353.i_x353.vacts_every
testbench353.i_x353.i_sensortrig.vacts_in
testbench353.i_x353.i_sensortrig.pre_vacts_out
testbench353.i_x353.i_sensortrig.pre_vacts_out_d
testbench353.i_x353.i_sensortrig.vacts_dly_on
testbench353.i_x353.i_sensortrig.vacts_out
testbench353.i_x353.vacts_long
testbench353.i_x353.i_sensorpads.i_sensor_phase.en_svact
@22
testbench353.i_x353.i_sensorpads.i_sensor_phase.svact_filter_cntr[7:0]
@28
testbench353.i_x353.i_camsync.outsync
@22
testbench353.i_x353.io_da[11:0]
testbench353.i_x353.io_da_en[11:0]
@800022
testbench353.i_x353.EXT[11:0]
@28
(0)testbench353.i_x353.EXT[11:0]
(1)testbench353.i_x353.EXT[11:0]
(2)testbench353.i_x353.EXT[11:0]
(3)testbench353.i_x353.EXT[11:0]
(4)testbench353.i_x353.EXT[11:0]
(5)testbench353.i_x353.EXT[11:0]
(6)testbench353.i_x353.EXT[11:0]
(7)testbench353.i_x353.EXT[11:0]
(8)testbench353.i_x353.EXT[11:0]
(9)testbench353.i_x353.EXT[11:0]
(10)testbench353.i_x353.EXT[11:0]
(11)testbench353.i_x353.EXT[11:0]
@1001200
-group_end
@1401200
-vacts_filter
@c00200
-compressor-memory
@28
testbench353.BLOCK_HACT
testbench353.i_x353.HACT
testbench353.i_x353.i_compressor.cmprs_start
testbench353.i_x353.vacts
testbench353.i_x353.i_compressor.vacts_long
testbench353.i_x353.i_compressor.not_vlong1_or_not_bonded
testbench353.i_x353.i_compressor.confirmFrame2Compressor
testbench353.i_x353.i_compressor.go_rq
testbench353.i_x353.i_compressor.restart_memory
testbench353.i_x353.i_compressor.noMoreData
testbench353.i_x353.i_compressor.nextBlocksEn
testbench353.i_x353.i_compressor.go_single
testbench353.i_x353.i_compressor.is_compressing
@22
testbench353.i_x353.i_compressor.i_color_proc.bcntr[17:0]
@28
testbench353.i_x353.i_compressor.i_color_proc.bcntrIsZero
testbench353.i_x353.i_compressor.i_color_proc.transfer_ended
testbench353.i_x353.i_compressor.i_stuffer.flush_end
@c00028
testbench353.i_x353.i_compressor.i_stuffer.size_out[2:0]
@28
(0)testbench353.i_x353.i_compressor.i_stuffer.size_out[2:0]
(1)testbench353.i_x353.i_compressor.i_stuffer.size_out[2:0]
(2)testbench353.i_x353.i_compressor.i_stuffer.size_out[2:0]
@1401200
-group_end
@28
testbench353.i_x353.i_compressor.i_stuffer.flush_end_delayed
testbench353.i_x353.i_compressor.i_stuffer.pre_flush_end_delayed
testbench353.i_x353.compressor_done_pulse
testbench353.i_x353.i_compressor.i_stuffer.done
testbench353.i_x353.compressor_started
@22
testbench353.i_x353.debug_mcontr_reset_data[31:0]
testbench353.i_x353.debug_mcontr_count[12:0]
testbench353.i_x353.debug_mcontr_count_start[15:0]
testbench353.i_x353.debug_mcontr_count_end[15:0]
@c00022
testbench353.i_x353.i_mcontr.i_descrproc.restart[3:0]
@28 @28
(0)testbench353.i_x353.i_mcontr.i_descrproc.restart[3:0] testbench353.i_x353.i_mcontr.chInit[0]
(1)testbench353.i_x353.i_mcontr.i_descrproc.restart[3:0] testbench353.i_x353.i_mcontr.chNum[1:0]
(2)testbench353.i_x353.i_mcontr.i_descrproc.restart[3:0]
(3)testbench353.i_x353.i_mcontr.i_descrproc.restart[3:0]
testbench353.i_x353.i_compressor.i_color_proc.memWasInit
testbench353.i_x353.i_compressor.chInitOnehot2
testbench353.i_x353.cb_reset_mcontr
@1401200
-group_end
@22
testbench353.i_x353.i_cmd_sequencer.frame_no[2:0]
@28
testbench353.i_x353.VACT
testbench353.i_x353.HACT
testbench353.i_x353.i_compressor.eot
testbench353.i_x353.i_compressor.done_compress_pulse
testbench353.i_x353.i_irq_smart.irq
@22
testbench353.i_x353.imgptr[23:0]
testbench353.i_x353.imgptr[23:0]
testbench353.i_x353.i_compressor.ntiles[17:0]
@28
testbench353.i_x353.i_compressor.i_color_proc.eof_rq
testbench353.i_x353.i_mcontr.i_descrproc.clk
testbench353.i_x353.i_mcontr.i_descrproc.last_lines_reg
testbench353.i_x353.i_mcontr.i_descrproc.last_lines_source
testbench353.i_x353.i_mcontr.i_descrproc.stepsIe
testbench353.i_x353.i_mcontr.i_descrproc.stepsEn012
testbench353.i_x353.i_mcontr.i_descrproc.rNum[1:0]
testbench353.i_x353.i_compressor.cmprs_repeat
testbench353.i_x353.i_compressor.i_color_proc.tim2next
testbench353.i_x353.i_compressor.pxrdy
testbench353.i_x353.i_compressor.i_color_proc.tim2next
testbench353.i_x353.i_compressor.done_compress
testbench353.i_x353.i_compressor.done_input
testbench353.i_x353.i_compressor.eot_real
@22 @22
testbench353.i_x353.i_mcontr.i_descrproc.tileX[9:0]
testbench353.i_x353.i_mcontr.i_descrproc.tileY[13:0]
@28
testbench353.i_x353.i_mcontr.i_descrproc.restart_en
testbench353.i_x353.i_compressor.i_color_proc.inc_sdrama
testbench353.i_x353.i_compressor.nxtpage
testbench353.i_x353.cb_break_frames
testbench353.i_x353.cb_reset_mcontr
testbench353.i_x353.cb_hact_regen
testbench353.i_x353.cb_use_sensor_clk
@c00022
testbench353.i_x353.chInitOnehot[3:0]
@28
(0)testbench353.i_x353.chInitOnehot[3:0]
(1)testbench353.i_x353.chInitOnehot[3:0]
(2)testbench353.i_x353.chInitOnehot[3:0]
(3)testbench353.i_x353.chInitOnehot[3:0]
@1401200
-group_end
@28
testbench353.i_x353.i_compressor.chInitOnehot2
@c00022
testbench353.i_x353.i_mcontr.chReqInit[3:0] testbench353.i_x353.i_mcontr.chReqInit[3:0]
@28 @28
(0)testbench353.i_x353.i_mcontr.chReqInit[3:0] testbench353.i_x353.i_mcontr.chSt1[0]
(1)testbench353.i_x353.i_mcontr.chReqInit[3:0] testbench353.i_x353.i_mcontr.chSt2[0]
(2)testbench353.i_x353.i_mcontr.chReqInit[3:0] testbench353.i_x353.i_mcontr.ch_dlast[0]
(3)testbench353.i_x353.i_mcontr.chReqInit[3:0] testbench353.i_x353.i_mcontr.ch_drun_rd[0]
testbench353.i_x353.i_mcontr.i_descrproc.rqInitS testbench353.i_x353.i_mcontr.ch_drun_wr[0]
testbench353.i_x353.i_mcontr.i_descrproc.chInitNum[1:0] testbench353.i_x353.i_mcontr.ch_prefirstdrun[0]
@22
testbench353.i_x353.i_mcontr.i_descrproc.extRestartRq[3:0]
@28
testbench353.i_x353.i_compressor.restart_memory
@1401200
-group_end
@28
testbench353.i_x353.i_compressor.i_color_proc.clk
@22
testbench353.i_x353.debug_mcontr_count[12:0]
@28
testbench353.i_x353.compressor_started
testbench353.i_x353.compressor_done_input
testbench353.i_x353.sr_ch2rdy
@22
testbench353.i_x353.i_compressor.i_color_proc.seq_cntr[8:0]
@28
testbench353.i_x353.i_mcontr.i_descrproc.setLineNumSource
@22
testbench353.i_x353.i_mcontr.i_descrproc.lineNumSource[13:0]
testbench353.i_x353.i_mcontr.i_descrproc.tileX[9:0]
testbench353.i_x353.i_mcontr.i_descrproc.rnTilesY[13:0]
testbench353.i_x353.i_mcontr.i_descrproc.descr_dyn[21:0]
@28
testbench353.i_x353.i_mcontr.i_descrproc.stepsEn012
testbench353.i_x353.i_mcontr.i_descrproc.srcAtStart
testbench353.i_x353.i_mcontr.i_descrproc.nxtTFw
testbench353.i_x353.i_mcontr.i_descrproc.nxtTFr
testbench353.i_x353.i_mcontr.i_descrproc.nxtTL
@22
testbench353.i_x353.i_mcontr.i_descrproc.tileY[13:0]
@28
testbench353.i_x353.i_mcontr.i_descrproc.setLineNumDest
@22
testbench353.i_x353.i_mcontr.i_descrproc.lineNumDest[13:0]
testbench353.i_x353.i_mcontr.i_descrproc.prevStripSource[13:4]
@28
testbench353.i_x353.i_mcontr.i_descrproc.lastLineDest
@22
testbench353.i_x353.i_mcontr.i_descrproc.descr_stat[17:0]
@28
testbench353.i_x353.i_mcontr.i_descrproc.last_lines_source
testbench353.i_x353.i_mcontr.i_descrproc.notEnoughData
testbench353.i_x353.i_mcontr.i_descrproc.updSuspXfer
testbench353.i_x353.i_mcontr.stch2
@c00028
testbench353.i_x353.i_mcontr.i_descrproc.nxtTF_p[2:0]
@28
(0)testbench353.i_x353.i_mcontr.i_descrproc.nxtTF_p[2:0]
(1)testbench353.i_x353.i_mcontr.i_descrproc.nxtTF_p[2:0]
(2)testbench353.i_x353.i_mcontr.i_descrproc.nxtTF_p[2:0]
@1401200
-group_end
@c00022
testbench353.i_x353.i_mcontr.i_descrproc.stepsEn[3:0]
@28
(0)testbench353.i_x353.i_mcontr.i_descrproc.stepsEn[3:0]
(1)testbench353.i_x353.i_mcontr.i_descrproc.stepsEn[3:0]
(2)testbench353.i_x353.i_mcontr.i_descrproc.stepsEn[3:0]
(3)testbench353.i_x353.i_mcontr.i_descrproc.stepsEn[3:0]
@1401200
-group_end
@28
testbench353.i_x353.i_mcontr.i_descrproc.first_tile
testbench353.i_x353.i_mcontr.i_descrproc.first_tile_dest
@22
testbench353.i_x353.i_mcontr.i_descrproc.descr_dyn[21:0]
testbench353.i_x353.i_mcontr.i_descrproc.tileY[13:0]
@1401200
-compressor-memory
@c00200
-camsync
@28
testbench353.i_x353.i_camsync.start
testbench353.i_x353.i_camsync.start_dly
testbench353.i_x353.i_camsync.dly_cntr_run
testbench353.i_x353.ARO
@22
testbench353.i_x353.psec[31:0]
testbench353.i_x353.pusec[19:0]
testbench353.i_x353.i_camsync.ts_rcv_usec[19:0]
testbench353.i_x353.i_compressor.i_stuffer.usec_r[19:0]
@28
testbench353.i_x353.i_compressor.go_single
testbench353.i_x353.i_compressor.compressor_started
testbench353.i_x353.i_compressor.eot_2x_n
testbench353.i_x353.i_camsync.pclk
testbench353.i_x353.i_camsync.outsync
testbench353.external_sync_line
@c00022
testbench353.i_x353.EXT[11:0]
@28
(0)testbench353.i_x353.EXT[11:0]
(1)testbench353.i_x353.EXT[11:0]
(2)testbench353.i_x353.EXT[11:0]
(3)testbench353.i_x353.EXT[11:0]
(4)testbench353.i_x353.EXT[11:0]
(5)testbench353.i_x353.EXT[11:0]
(6)testbench353.i_x353.EXT[11:0]
(7)testbench353.i_x353.EXT[11:0]
(8)testbench353.i_x353.EXT[11:0]
(9)testbench353.i_x353.EXT[11:0]
(10)testbench353.i_x353.EXT[11:0]
(11)testbench353.i_x353.EXT[11:0]
@1401200
-group_end
@28
testbench353.i_x353.i_camsync.ts_external_pclk
testbench353.i_x353.i_camsync.ts_snd_en
testbench353.i_x353.i_camsync.ts_snap
testbench353.i_x353.i_camsync.input_use_intern
@22
testbench353.i_x353.i_camsync.input_pattern[11:0]
testbench353.i_x353.i_camsync.input_use[11:0]
testbench353.i_x353.i_camsync.repeat_period[31:0]
@28
testbench353.i_x353.i_camsync.pre_start0
testbench353.i_x353.i_camsync.pre_set_bit
testbench353.i_x353.i_camsync.pre_set_period
testbench353.i_x353.i_camsync.start
@22
testbench353.i_x353.i_camsync.bit_length[7:0]
@28
testbench353.i_x353.i_camsync.trigger1
testbench353.i_x353.i_camsync.trigger1_dly16
testbench353.i_x353.i_camsync.dly_cntr_run
@22
testbench353.i_x353.i_camsync.bit_snd_counter[5:0]
@28
testbench353.i_x353.i_camsync.trigger_condition
@22
testbench353.i_x353.i_camsync.trigger_filter_cntr[6:0]
@28
testbench353.i_x353.i_camsync.trigger_condition_filtered
@22
testbench353.i_x353.i_camsync.sr_rcv_first[31:0]
testbench353.i_x353.i_camsync.sr_rcv_second[31:0]
testbench353.i_x353.i_camsync.bit_rcv_duration[7:0]
@28
testbench353.i_x353.i_camsync.rcv_run
testbench353.i_x353.i_camsync.rcv_run_or_deaf
testbench353.i_x353.i_camsync.rcv_done_rq
testbench353.i_x353.i_camsync.rcv_done
testbench353.i_x353.i_camsync.rcv_error
@1401200
-camsync
@28
testbench353.i_x353.i_compressor.i_quantizator.clk
testbench353.i_x353.i_compressor.i_quantizator.sclk
testbench353.i_x353.i_compressor.i_quantizator.ctype
testbench353.i_x353.i_compressor.i_quantizator.ctypei
testbench353.i_x353.i_compressor.i_quantizator.stb
@22
testbench353.i_x353.i_compressor.i_quantizator.start[5:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.start_a
testbench353.i_x353.i_compressor.i_quantizator.dcc_stb
testbench353.i_x353.i_compressor.i_quantizator.start_z
testbench353.i_x353.i_compressor.i_quantizator.start_out
@22
testbench353.i_x353.i_compressor.i_quantizator.block_mem_o[15:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.block_mem_ra[2:0]
testbench353.i_x353.i_compressor.i_quantizator.block_mem_wa[2:0]
testbench353.i_x353.i_compressor.i_quantizator.block_mem_wa_save[2:0]
testbench353.i_x353.i_compressor.i_quantizator.color_first
testbench353.i_x353.i_compressor.i_quantizator.copy_dc_tdo
testbench353.i_x353.i_compressor.i_quantizator.coring_num[2:0]
@22
testbench353.i_x353.i_compressor.i_quantizator.d1[12:0]
testbench353.i_x353.i_compressor.i_quantizator.d2[12:0]
testbench353.i_x353.i_compressor.i_quantizator.d3[12:0]
testbench353.i_x353.i_compressor.i_quantizator.d2_dct[10:0]
testbench353.i_x353.i_compressor.i_quantizator.dc1[8:0]
testbench353.i_x353.i_compressor.i_quantizator.dc[8:0]
testbench353.i_x353.i_compressor.i_quantizator.tba[9:0]
testbench353.i_x353.i_compressor.i_quantizator.tbac[3:0]
testbench353.i_x353.i_compressor.i_quantizator.tdco[3:0]
testbench353.i_x353.i_compressor.i_quantizator.tdo[15:0]
testbench353.i_x353.i_compressor.i_quantizator.tdor[15:0]
testbench353.i_x353.i_compressor.i_quantizator.qmul[27:0]
testbench353.i_x353.i_compressor.i_quantizator.qmulr[20:0]
testbench353.i_x353.i_compressor.i_quantizator.qdo0[12:0]
testbench353.i_x353.i_compressor.i_quantizator.qdo[12:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.zwe
testbench353.i_x353.i_compressor.i_quantizator.coring_range
testbench353.i_x353.i_compressor.i_quantizator.coring_sel[2:0]
testbench353.i_x353.i_compressor.i_quantizator.ctype_prev[1:0]
@22
testbench353.i_x353.i_compressor.i_quantizator.dc_tdo[15:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.dcc_Y
@22
testbench353.i_x353.i_compressor.i_quantizator.dcc_acc[12:0]
testbench353.i_x353.i_compressor.i_quantizator.dcc_data[15:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.dcc_en
testbench353.i_x353.i_compressor.i_quantizator.dcc_first
testbench353.i_x353.i_compressor.i_quantizator.dcc_run
testbench353.i_x353.i_compressor.i_quantizator.dcc_vld
@22
testbench353.i_x353.i_compressor.i_quantizator.dci[8:0]
testbench353.i_x353.i_compressor.i_quantizator.di[12:0]
testbench353.i_x353.i_compressor.i_quantizator.do[12:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.ds
testbench353.i_x353.i_compressor.i_quantizator.dv
testbench353.i_x353.i_compressor.i_quantizator.en
testbench353.i_x353.i_compressor.i_quantizator.first_in
testbench353.i_x353.i_compressor.i_quantizator.first_interm
testbench353.i_x353.i_compressor.i_quantizator.first_out
testbench353.i_x353.i_compressor.i_quantizator.first_stb
@22
testbench353.i_x353.i_compressor.i_quantizator.hfc_acc[12:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.hfc_copy
testbench353.i_x353.i_compressor.i_quantizator.hfc_en
testbench353.i_x353.i_compressor.i_quantizator.hfc_sel[2:0]
@22
testbench353.i_x353.i_compressor.i_quantizator.n000[7:0]
testbench353.i_x353.i_compressor.i_quantizator.n255[7:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.next_dv
@22
testbench353.i_x353.i_compressor.i_quantizator.pre_dc_tdo[15:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.pre_start
testbench353.i_x353.i_compressor.i_quantizator.rpage
testbench353.i_x353.i_compressor.i_quantizator.sel_satnum
@22
testbench353.i_x353.i_compressor.i_quantizator.ta[8:0]
testbench353.i_x353.i_compressor.i_quantizator.tdi[15:0]
@28
testbench353.i_x353.i_compressor.i_quantizator.ts[2:0]
testbench353.i_x353.i_compressor.i_quantizator.tsi[2:0]
testbench353.i_x353.i_compressor.i_quantizator.twce
testbench353.i_x353.i_compressor.i_quantizator.twce_d
testbench353.i_x353.i_compressor.i_quantizator.twqe
testbench353.i_x353.i_compressor.i_quantizator.twqe_d
testbench353.i_x353.i_compressor.i_quantizator.wpage
@22
testbench353.i_x353.i_compressor.i_quantizator.zigzag_q[15:0]
testbench353.i_x353.i_compressor.i_quantizator.zra[5:0]
testbench353.i_x353.i_compressor.i_quantizator.zwa[5:0]
<<<<<<< x353_1.sav
@1401200
-quantizer
@c00200
-IMU
@22
testbench353.i_x353.i_imu_logger.ts_rcv_sec[31:0]
testbench353.i_x353.i_imu_logger.ts_rcv_usec[19:0]
@28
testbench353.i_x353.i_imu_logger.ts_stb
@22
testbench353.i_x353.i_imu_logger.bitHalfPeriod[15:0]
testbench353.i_x353.i_imu_logger.bitHalfPeriod_mclk[15:0]
@28
testbench353.i_x353.i_imu_logger.channel[1:0]
@22
testbench353.i_x353.i_imu_logger.channel_next[3:0]
testbench353.i_x353.i_imu_logger.channel_ready[3:0]
@28
testbench353.i_x353.i_imu_logger.clk
@22 @22
testbench353.i_x353.i_imu_logger.config_gps[3:0] testbench353.i_x353.i_mcontr.chnAckn[3:0]
testbench353.i_x353.i_imu_logger.config_gps_mclk[3:0] testbench353.i_x353.i_mcontr.chnReqInit[3:0]
testbench353.i_x353.i_imu_logger.config_gps_pre[3:0] testbench353.i_x353.i_mcontr.chnReq[4:0]
@28 @28
testbench353.i_x353.i_imu_logger.config_imu[1:0] testbench353.i_x353.i_mcontr.clk0[0]
testbench353.i_x353.i_imu_logger.config_imu_mclk[1:0]
testbench353.i_x353.i_imu_logger.config_imu_pre[1:0]
@22 @22
testbench353.i_x353.i_imu_logger.config_msg[4:0] testbench353.i_x353.i_mcontr.confirmRead0[3:0]
testbench353.i_x353.i_imu_logger.config_msg_mclk[4:0] testbench353.i_x353.i_mcontr.confirmRead[3:0]
testbench353.i_x353.i_imu_logger.config_msg_pre[4:0] testbench353.i_x353.i_mcontr.curChanLate[3:0]
testbench353.i_x353.i_mcontr.curChan[4:0]
testbench353.i_x353.i_mcontr.di[31:0]
@28 @28
testbench353.i_x353.i_imu_logger.config_rst testbench353.i_x353.i_mcontr.disSDRAM[0]
testbench353.i_x353.i_imu_logger.config_rst_mclk testbench353.i_x353.i_mcontr.dmask[1:0]
testbench353.i_x353.i_imu_logger.config_rst_pre
testbench353.i_x353.i_imu_logger.config_syn
testbench353.i_x353.i_imu_logger.config_syn_mclk
testbench353.i_x353.i_imu_logger.config_syn_pre
@22 @22
testbench353.i_x353.i_imu_logger.ctrl_addr[6:0] testbench353.i_x353.i_mcontr.dnch[3:0]
testbench353.i_x353.i_imu_logger.data_out[15:0] testbench353.i_x353.i_mcontr.do[31:0]
@28 @28
testbench353.i_x353.i_imu_logger.data_out_stb testbench353.i_x353.i_mcontr.dqs_re[0]
testbench353.i_x353.i_mcontr.dscs[0]
@22 @22
testbench353.i_x353.i_imu_logger.dbg_cntr[7:0] testbench353.i_x353.i_mcontr.dsdo[31:0]
testbench353.i_x353.i_imu_logger.debug_state[31:0]
testbench353.i_x353.i_imu_logger.di[15:0]
testbench353.i_x353.i_imu_logger.di_d[15:0]
@28 @28
testbench353.i_x353.i_imu_logger.enable_gps testbench353.i_x353.i_mcontr.dsel[1:0]
testbench353.i_x353.i_imu_logger.enable_msg testbench353.i_x353.i_mcontr.enRefresh[0]
testbench353.i_x353.i_imu_logger.enable_syn testbench353.i_x353.i_mcontr.enSDRAM[0]
testbench353.i_x353.i_imu_logger.enable_timestamps
@22 @22
testbench353.i_x353.i_imu_logger.ext_di[11:0] testbench353.i_x353.i_mcontr.enXfer[3:0]
testbench353.i_x353.i_imu_logger.ext_do[11:0]
testbench353.i_x353.i_imu_logger.ext_en[11:0]
@28 @28
testbench353.i_x353.i_imu_logger.ext_ts_stb[1:0] testbench353.i_x353.i_mcontr.ench2[0]
@22 @22
testbench353.i_x353.i_imu_logger.extts_data[15:0] testbench353.i_x353.i_mcontr.ia[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.gps_pulse1sec testbench353.i_x353.i_mcontr.init_ch3[0]
testbench353.i_x353.i_imu_logger.gps_pulse1sec_d[2:0]
testbench353.i_x353.i_imu_logger.gps_pulse1sec_denoise[1:0]
@22 @22
testbench353.i_x353.i_imu_logger.gps_pulse1sec_denoise_count[7:0] testbench353.i_x353.i_mcontr.mancmd[17:0]
@28 @28
testbench353.i_x353.i_imu_logger.gps_pulse1sec_single testbench353.i_x353.i_mcontr.menrw[0]
testbench353.i_x353.i_imu_logger.gps_ts_stb testbench353.i_x353.i_mcontr.mode[0]
testbench353.i_x353.i_mcontr.mwnr[0]
testbench353.i_x353.i_mcontr.nBuf[1:0]
@22 @22
testbench353.i_x353.i_imu_logger.imu_data[15:0] testbench353.i_x353.i_mcontr.nextBlocksEn[3:0]
testbench353.i_x353.i_mcontr.nextFrame[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.message_trig testbench353.i_x353.i_mcontr.nextReq[0]
testbench353.i_x353.i_imu_logger.miso testbench353.i_x353.i_mcontr.next_ch3[0]
testbench353.i_x353.i_imu_logger.mosi
@22 @22
testbench353.i_x353.i_imu_logger.msg_data[15:0] testbench353.i_x353.i_mcontr.param[5:0]
testbench353.i_x353.i_imu_logger.mux_data_final[15:0]
testbench353.i_x353.i_imu_logger.mux_data_source[15:0]
@28 @28
testbench353.i_x353.i_imu_logger.mux_data_valid testbench353.i_x353.i_mcontr.predqt[0]
testbench353.i_x353.i_imu_logger.mux_rdy_source testbench353.i_x353.i_mcontr.rdy[0]
testbench353.i_x353.i_mcontr.readNextFrame0[0]
testbench353.i_x353.i_mcontr.readNextFrame1[0]
testbench353.i_x353.i_mcontr.readNextFrame2[0]
testbench353.i_x353.i_mcontr.readNextFrame3[0]
@22 @22
testbench353.i_x353.i_imu_logger.nmea_data[15:0] testbench353.i_x353.i_mcontr.readNextFrameS[3:0]
testbench353.i_x353.i_mcontr.readNextFrame_rst[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.nmea_sent_start testbench353.i_x353.i_mcontr.refrStart[0]
testbench353.i_x353.i_imu_logger.pre_message_trig
testbench353.i_x353.i_imu_logger.rs232_start
testbench353.i_x353.i_imu_logger.rs232_wait_pause
@22 @22
testbench353.i_x353.i_imu_logger.sample_counter[23:0] testbench353.i_x353.i_mcontr.restart[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.scl testbench353.i_x353.i_mcontr.restart_en[0]
testbench353.i_x353.i_imu_logger.scl_en testbench353.i_x353.i_mcontr.rovr[0]
testbench353.i_x353.i_imu_logger.sda
testbench353.i_x353.i_imu_logger.sda_en
@22 @22
testbench353.i_x353.i_imu_logger.sec[31:0] testbench353.i_x353.i_mcontr.sda[12:0]
@28 @28
testbench353.i_x353.i_imu_logger.ser_di testbench353.i_x353.i_mcontr.sdba[1:0]
testbench353.i_x353.i_imu_logger.ser_do testbench353.i_x353.i_mcontr.sdcas[0]
testbench353.i_x353.i_imu_logger.ser_do_stb
@22 @22
testbench353.i_x353.i_imu_logger.timestamp_ackn[3:0] testbench353.i_x353.i_mcontr.sddi[31:0]
testbench353.i_x353.i_imu_logger.timestamp_request[3:0] testbench353.i_x353.i_mcontr.sddo[31:0]
testbench353.i_x353.i_imu_logger.timestamp_request_long[3:0] testbench353.i_x353.i_mcontr.sddo_reg[31:0]
@28 @28
testbench353.i_x353.i_imu_logger.timestamp_sel[1:0] testbench353.i_x353.i_mcontr.sdras[0]
testbench353.i_x353.i_mcontr.sdwe[0]
@22 @22
testbench353.i_x353.i_imu_logger.timestamps_rdata[15:0] testbench353.i_x353.i_mcontr.sfa[24:8]
testbench353.i_x353.i_mcontr.startAddr[24:3]
@28 @28
testbench353.i_x353.i_imu_logger.ts_en testbench353.i_x353.i_mcontr.stch0[0]
@22 testbench353.i_x353.i_mcontr.stch1[0]
testbench353.i_x353.i_imu_logger.ts_rcv_sec[31:0] testbench353.i_x353.i_mcontr.stch2[0]
testbench353.i_x353.i_imu_logger.ts_rcv_usec[19:0] testbench353.i_x353.i_mcontr.trist[0]
@28 testbench353.i_x353.i_mcontr.wrempty[0]
testbench353.i_x353.i_imu_logger.ts_stb
testbench353.i_x353.i_imu_logger.ts_stb_rq
@22
testbench353.i_x353.i_imu_logger.usec[19:0]
@28
testbench353.i_x353.i_imu_logger.wa
testbench353.i_x353.i_imu_logger.we
testbench353.i_x353.i_imu_logger.we_bitHalfPeriod
testbench353.i_x353.i_imu_logger.we_bit_duration
testbench353.i_x353.i_imu_logger.we_config
testbench353.i_x353.i_imu_logger.we_config_gps
testbench353.i_x353.i_imu_logger.we_config_imu
testbench353.i_x353.i_imu_logger.we_config_msg
testbench353.i_x353.i_imu_logger.we_config_syn
testbench353.i_x353.i_imu_logger.we_d
testbench353.i_x353.i_imu_logger.we_gps
testbench353.i_x353.i_imu_logger.we_imu
testbench353.i_x353.i_imu_logger.we_message
testbench353.i_x353.i_imu_logger.we_period
testbench353.i_x353.i_imu_logger.xclk
@1401200 @1401200
-IMU -mcontr
@c00200 @c00200
-imu_spi -chnrq0
@28 @28
testbench353.IMU_103695REVA testbench353.i_x353.i_mcontr.i_channelRequest0.ackn[0]
@22 testbench353.i_x353.i_mcontr.i_channelRequest0.cntrsInit[0]
testbench353.i_x353.i_imu_logger.config_debug[3:0] testbench353.i_x353.i_mcontr.i_channelRequest0.cntrsValid[0]
@800022 testbench353.i_x353.i_mcontr.i_channelRequest0.current_wnr[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0] testbench353.i_x353.i_mcontr.i_channelRequest0.done[0]
@28 testbench353.i_x353.i_mcontr.i_channelRequest0.eclk[0]
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0] testbench353.i_x353.i_mcontr.i_channelRequest0.ecnt[2:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0] testbench353.i_x353.i_mcontr.i_channelRequest0.enXfer[0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0] testbench353.i_x353.i_mcontr.i_channelRequest0.en_done[0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0] testbench353.i_x353.i_mcontr.i_channelRequest0.iclk[0]
@1001200 testbench353.i_x353.i_mcontr.i_channelRequest0.icnt[2:0]
-group_end testbench353.i_x353.i_mcontr.i_channelRequest0.init[0]
@28 testbench353.i_x353.i_mcontr.i_channelRequest0.next_ecnt[2:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.config_single_wire testbench353.i_x353.i_mcontr.i_channelRequest0.next_icnt[2:0]
testbench353.IMU_MOSI_REVA testbench353.i_x353.i_mcontr.i_channelRequest0.next_rcnt[2:0]
testbench353.IMU_NMOSI testbench353.i_x353.i_mcontr.i_channelRequest0.rcnt[2:0]
testbench353.IMU_SCLK testbench353.i_x353.i_mcontr.i_channelRequest0.rdy[0]
testbench353.IMU_MOSI testbench353.i_x353.i_mcontr.i_channelRequest0.rdy_async[0]
testbench353.IMU_CS testbench353.i_x353.i_mcontr.i_channelRequest0.ready_off[0]
testbench353.IMU_ACTIVE testbench353.i_x353.i_mcontr.i_channelRequest0.rqInit[0]
testbench353.IMU_SCLK_OUT testbench353.i_x353.i_mcontr.i_channelRequest0.rq[0]
testbench353.IMU_MOSI_OUT testbench353.i_x353.i_mcontr.i_channelRequest0.rst[0]
testbench353.IMU_MISO testbench353.i_x353.i_mcontr.i_channelRequest0.start[0]
@22 testbench353.i_x353.i_mcontr.i_channelRequest0.wnr[0]
testbench353.IMU_LOOPBACK[15:0] testbench353.i_x353.i_mcontr.i_channelRequest0.wrempty[0]
@c00022 @1401200
testbench353.IMU_TAPS[5:1] -chnrq0
@28
(0)testbench353.IMU_TAPS[5:1]
(1)testbench353.IMU_TAPS[5:1]
(2)testbench353.IMU_TAPS[5:1]
(3)testbench353.IMU_TAPS[5:1]
(4)testbench353.IMU_TAPS[5:1]
@1401200
-group_end
@c00028
testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_stb[2:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_stb[2:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_stb[2:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_stb[2:0]
@1401200
-group_end
@800028
testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_r[1:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_r[1:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_r[1:0]
@1001200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_state[1:0]
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_counter[9:0]
@800022
testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
@1001200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.stall
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi
testbench353.i_x353.i_imu_logger.i_imu_spi.scl
testbench353.i_x353.i_imu_logger.i_imu_spi.sda
testbench353.IMU_DATA_READY
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_ready_reset
@c00022
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(4)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(5)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
@1401200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.skip_stall
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.stall_cntr[7:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.stall
testbench353.i_x353.i_imu_logger.i_imu_spi.set_stall
testbench353.i_x353.i_imu_logger.i_imu_spi.set_mosi_spi
testbench353.i_x353.i_imu_logger.i_imu_spi.shift_mosi
@c00022
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(4)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(5)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(6)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(7)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(8)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(9)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(10)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(11)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(12)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(13)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(14)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(15)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
@1401200
-group_end
@28
testbench353.IMU_MOSI
testbench353.IMU_SCL
testbench353.IMU_CS
testbench353.IMU_MISO
testbench353.i_x353.i_imu_logger.i_imu_spi.stall
testbench353.i_x353.i_imu_logger.i_imu_spi.miso
testbench353.i_x353.i_imu_logger.i_imu_spi.shift_mosi
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.miso_reg[15:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.shift_miso
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_in_buf[15:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_wr_buf
testbench353.i_x353.i_imu_logger.i_imu_spi.last_buf_wr
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.bit_duration[7:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.bit_duration_cntr[7:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.bit_duration_mclk[7:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.bit_duration_zero
testbench353.i_x353.i_imu_logger.i_imu_spi.clk_div[1:0]
@c00022
testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
@1401200
-group_end
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.config_late_clk
testbench353.i_x353.i_imu_logger.i_imu_spi.config_long_sda_en
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.di[15:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.di_d[15:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.en
testbench353.i_x353.i_imu_logger.i_imu_spi.end_prepare
testbench353.i_x353.i_imu_logger.i_imu_spi.end_spi
testbench353.i_x353.i_imu_logger.i_imu_spi.first_prepare
testbench353.i_x353.i_imu_logger.i_imu_spi.first_prepare_d[1:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_enabled[1:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_enabled_mclk
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_in_buf[15:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_in_word[4:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_wr_buf
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.miso_reg[15:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_reg_number[6:1]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_run[1:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_run_confirmed
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_run_mclk
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_first
@c00028
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_grant[1:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_grant[1:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_grant[1:0]
@1401200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_mclk
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_wr_buf
testbench353.i_x353.i_imu_logger.i_imu_spi.last_bit
testbench353.i_x353.i_imu_logger.i_imu_spi.last_bit_ext
testbench353.i_x353.i_imu_logger.i_imu_spi.last_buf_wr
testbench353.i_x353.i_imu_logger.i_imu_spi.miso
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi
testbench353.i_x353.i_imu_logger.i_imu_spi.set_mosi_spi
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.period[31:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.period_counter[31:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.pre_imu_wr_buf
testbench353.i_x353.i_imu_logger.i_imu_spi.pre_seq_counter_zero
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.raddr[4:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.rd_stb
@c00022
testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(4)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(5)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(6)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(7)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(8)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(9)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(10)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(11)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(12)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(13)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(14)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(15)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
@1401200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.rdy
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.reg_seq_number[4:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.scl
testbench353.i_x353.i_imu_logger.i_imu_spi.scl_d
testbench353.i_x353.i_imu_logger.i_imu_spi.scl_en
testbench353.i_x353.i_imu_logger.i_imu_spi.sclk
testbench353.i_x353.i_imu_logger.i_imu_spi.sda
testbench353.i_x353.i_imu_logger.i_imu_spi.sda_d
testbench353.i_x353.i_imu_logger.i_imu_spi.sda_en
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_counter[9:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_counter_zero
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_state[1:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.set_mosi_prepare
testbench353.i_x353.i_imu_logger.i_imu_spi.set_mosi_spi
testbench353.i_x353.i_imu_logger.i_imu_spi.set_stall
testbench353.i_x353.i_imu_logger.i_imu_spi.shift_miso
testbench353.i_x353.i_imu_logger.i_imu_spi.skip_stall
testbench353.i_x353.i_imu_logger.i_imu_spi.stall
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.stall_cntr[7:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.stall_dur[7:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.stall_dur_mclk[7:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.ts
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.wa[4:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.we_div
testbench353.i_x353.i_imu_logger.i_imu_spi.we_period
testbench353.i_x353.i_imu_logger.i_imu_spi.we_ra
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.we_timer[4:1]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.xclk
@1401200
-imu_spi
@c00200 @c00200
-rs232_rcv -chnrq3
@22 @28
testbench353.i_x353.i_imu_logger.i_rs232_rcv.bitHalfPeriod[15:0] testbench353.i_x353.i_mcontr.i_channelRequest3.ackn[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.bit_cntr[4:0] testbench353.i_x353.i_mcontr.i_channelRequest3.cntrsInit[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.bit_dur_cntr[15:0] testbench353.i_x353.i_mcontr.i_channelRequest3.cntrsValid[0]
@28 testbench353.i_x353.i_mcontr.i_channelRequest3.current_wnr[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.bit_half_end testbench353.i_x353.i_mcontr.i_channelRequest3.done[0]
@22 testbench353.i_x353.i_mcontr.i_channelRequest3.eclk[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.debug0[4:0] testbench353.i_x353.i_mcontr.i_channelRequest3.ecnt[2:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.debug[4:0] testbench353.i_x353.i_mcontr.i_channelRequest3.enXfer[0]
@28 testbench353.i_x353.i_mcontr.i_channelRequest3.en_done[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.error testbench353.i_x353.i_mcontr.i_channelRequest3.iclk[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.last_half_bit testbench353.i_x353.i_mcontr.i_channelRequest3.icnt[2:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.receiving_byte testbench353.i_x353.i_mcontr.i_channelRequest3.init[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.reset_bit_duration testbench353.i_x353.i_mcontr.i_channelRequest3.next_ecnt[2:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.reset_wait_pause testbench353.i_x353.i_mcontr.i_channelRequest3.next_icnt[2:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.restart[1:0] testbench353.i_x353.i_mcontr.i_channelRequest3.next_rcnt[2:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.sample_bit testbench353.i_x353.i_mcontr.i_channelRequest3.rcnt[2:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_di testbench353.i_x353.i_mcontr.i_channelRequest3.rdy[0]
@22 testbench353.i_x353.i_mcontr.i_channelRequest3.rdy_async[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_di_d[4:0] testbench353.i_x353.i_mcontr.i_channelRequest3.ready_off[0]
@28 testbench353.i_x353.i_mcontr.i_channelRequest3.rqInit[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_do testbench353.i_x353.i_mcontr.i_channelRequest3.rq[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_do_stb testbench353.i_x353.i_mcontr.i_channelRequest3.rst[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_filt_di testbench353.i_x353.i_mcontr.i_channelRequest3.start[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_filt_di_d testbench353.i_x353.i_mcontr.i_channelRequest3.wnr[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_rst testbench353.i_x353.i_mcontr.i_channelRequest3.wrempty[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.shift_en @1401200
testbench353.i_x353.i_imu_logger.i_rs232_rcv.start -chnrq3
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ts_stb
testbench353.i_x353.i_imu_logger.i_rs232_rcv.wait_just_pause
testbench353.i_x353.i_imu_logger.i_rs232_rcv.wait_pause
testbench353.i_x353.i_imu_logger.i_rs232_rcv.wait_start
testbench353.i_x353.i_imu_logger.i_rs232_rcv.wstart
testbench353.i_x353.i_imu_logger.i_rs232_rcv.xclk
@1401200
-rs232_rcv
=======
@1401200
-quantizer
@c00200 @c00200
-IMU -descrproc
@22
testbench353.i_x353.i_imu_logger.ts_rcv_sec[31:0]
testbench353.i_x353.i_imu_logger.ts_rcv_usec[19:0]
@28 @28
testbench353.i_x353.i_imu_logger.ts_stb testbench353.i_x353.i_mcontr.i_descrproc.WnR[0]
@22 @22
testbench353.i_x353.i_imu_logger.bitHalfPeriod[15:0] testbench353.i_x353.i_mcontr.i_descrproc.am[3:0]
testbench353.i_x353.i_imu_logger.bitHalfPeriod_mclk[15:0] testbench353.i_x353.i_mcontr.i_descrproc.as[3:0]
@28 testbench353.i_x353.i_mcontr.i_descrproc.bonded[3:0]
testbench353.i_x353.i_imu_logger.channel[1:0]
@22
testbench353.i_x353.i_imu_logger.channel_next[3:0]
testbench353.i_x353.i_imu_logger.channel_ready[3:0]
@28
testbench353.i_x353.i_imu_logger.clk
@22
testbench353.i_x353.i_imu_logger.config_gps[3:0]
testbench353.i_x353.i_imu_logger.config_gps_mclk[3:0]
testbench353.i_x353.i_imu_logger.config_gps_pre[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.config_imu[1:0] testbench353.i_x353.i_mcontr.i_descrproc.chInitNum[1:0]
testbench353.i_x353.i_imu_logger.config_imu_mclk[1:0] testbench353.i_x353.i_mcontr.i_descrproc.chInit[0]
testbench353.i_x353.i_imu_logger.config_imu_pre[1:0]
@22 @22
testbench353.i_x353.i_imu_logger.config_msg[4:0] testbench353.i_x353.i_mcontr.i_descrproc.chNumOneHot[3:0]
testbench353.i_x353.i_imu_logger.config_msg_mclk[4:0]
testbench353.i_x353.i_imu_logger.config_msg_pre[4:0]
@28 @28
testbench353.i_x353.i_imu_logger.config_rst testbench353.i_x353.i_mcontr.i_descrproc.chNum[1:0]
testbench353.i_x353.i_imu_logger.config_rst_mclk
testbench353.i_x353.i_imu_logger.config_rst_pre
testbench353.i_x353.i_imu_logger.config_syn
testbench353.i_x353.i_imu_logger.config_syn_mclk
testbench353.i_x353.i_imu_logger.config_syn_pre
@22 @22
testbench353.i_x353.i_imu_logger.ctrl_addr[6:0] testbench353.i_x353.i_mcontr.i_descrproc.chReqInit[3:0]
testbench353.i_x353.i_imu_logger.data_out[15:0]
@28 @28
testbench353.i_x353.i_imu_logger.data_out_stb testbench353.i_x353.i_mcontr.i_descrproc.chStIn[0]
testbench353.i_x353.i_mcontr.i_descrproc.chStOut[0]
@22 @22
testbench353.i_x353.i_imu_logger.dbg_cntr[7:0] testbench353.i_x353.i_mcontr.i_descrproc.channelIsRead[3:0]
testbench353.i_x353.i_imu_logger.debug_state[31:0]
testbench353.i_x353.i_imu_logger.di[15:0]
testbench353.i_x353.i_imu_logger.di_d[15:0]
@28 @28
testbench353.i_x353.i_imu_logger.enable_gps testbench353.i_x353.i_mcontr.i_descrproc.clk[0]
testbench353.i_x353.i_imu_logger.enable_msg
testbench353.i_x353.i_imu_logger.enable_syn
testbench353.i_x353.i_imu_logger.enable_timestamps
@22 @22
testbench353.i_x353.i_imu_logger.ext_di[11:0] testbench353.i_x353.i_mcontr.i_descrproc.confirmRead[3:0]
testbench353.i_x353.i_imu_logger.ext_do[11:0]
testbench353.i_x353.i_imu_logger.ext_en[11:0]
@28 @28
testbench353.i_x353.i_imu_logger.ext_ts_stb[1:0] testbench353.i_x353.i_mcontr.i_descrproc.depend[0]
@22 @22
testbench353.i_x353.i_imu_logger.extts_data[15:0] testbench353.i_x353.i_mcontr.i_descrproc.descr_dyn[21:0]
testbench353.i_x353.i_mcontr.i_descrproc.descr_stat[17:0]
testbench353.i_x353.i_mcontr.i_descrproc.descr_stat_inc[4:0]
@28 @28
testbench353.i_x353.i_imu_logger.gps_pulse1sec testbench353.i_x353.i_mcontr.i_descrproc.destBond[0]
testbench353.i_x353.i_imu_logger.gps_pulse1sec_d[2:0] testbench353.i_x353.i_mcontr.i_descrproc.destChNum[1:0]
testbench353.i_x353.i_imu_logger.gps_pulse1sec_denoise[1:0]
@22 @22
testbench353.i_x353.i_imu_logger.gps_pulse1sec_denoise_count[7:0] testbench353.i_x353.i_mcontr.i_descrproc.dest_bond_en[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.gps_pulse1sec_single testbench353.i_x353.i_mcontr.i_descrproc.dest_mode[0]
testbench353.i_x353.i_imu_logger.gps_ts_stb testbench353.i_x353.i_mcontr.i_descrproc.enRefresh0[0]
testbench353.i_x353.i_mcontr.i_descrproc.enRefresh[0]
@22 @22
testbench353.i_x353.i_imu_logger.imu_data[15:0] testbench353.i_x353.i_mcontr.i_descrproc.enRestart[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.message_trig testbench353.i_x353.i_mcontr.i_descrproc.enSDRAM0[0]
testbench353.i_x353.i_imu_logger.miso testbench353.i_x353.i_mcontr.i_descrproc.enSDRAM[0]
testbench353.i_x353.i_imu_logger.mosi
@22 @22
testbench353.i_x353.i_imu_logger.msg_data[15:0] testbench353.i_x353.i_mcontr.i_descrproc.enXfer0[3:0]
testbench353.i_x353.i_imu_logger.mux_data_final[15:0] testbench353.i_x353.i_mcontr.i_descrproc.enXfer[3:0]
testbench353.i_x353.i_imu_logger.mux_data_source[15:0] testbench353.i_x353.i_mcontr.i_descrproc.extRestartRq0[3:0]
testbench353.i_x353.i_mcontr.i_descrproc.extRestartRq1[3:0]
testbench353.i_x353.i_mcontr.i_descrproc.extRestartRq2[3:0]
testbench353.i_x353.i_mcontr.i_descrproc.extRestartRq[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.mux_data_valid testbench353.i_x353.i_mcontr.i_descrproc.first_tile[0]
testbench353.i_x353.i_imu_logger.mux_rdy_source testbench353.i_x353.i_mcontr.i_descrproc.first_tile_dest[0]
testbench353.i_x353.i_mcontr.i_descrproc.first_tile_reg[0]
@22 @22
testbench353.i_x353.i_imu_logger.nmea_data[15:0] testbench353.i_x353.i_mcontr.i_descrproc.ia[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.nmea_sent_start testbench353.i_x353.i_mcontr.i_descrproc.initChannelAsRead[0]
testbench353.i_x353.i_imu_logger.pre_message_trig testbench353.i_x353.i_mcontr.i_descrproc.lastLineDest[0]
testbench353.i_x353.i_imu_logger.rs232_start testbench353.i_x353.i_mcontr.i_descrproc.last_line[0]
testbench353.i_x353.i_imu_logger.rs232_wait_pause testbench353.i_x353.i_mcontr.i_descrproc.last_lines[0]
testbench353.i_x353.i_mcontr.i_descrproc.last_lines_reg[0]
testbench353.i_x353.i_mcontr.i_descrproc.last_lines_source[0]
@22 @22
testbench353.i_x353.i_imu_logger.sample_counter[23:0] testbench353.i_x353.i_mcontr.i_descrproc.linAddr[16:0]
testbench353.i_x353.i_mcontr.i_descrproc.linAddr_input[18:0]
testbench353.i_x353.i_mcontr.i_descrproc.lineNumDest[13:0]
testbench353.i_x353.i_mcontr.i_descrproc.lineNumSource[13:0]
@28 @28
testbench353.i_x353.i_imu_logger.scl testbench353.i_x353.i_mcontr.i_descrproc.mancmdRqS[2:0]
testbench353.i_x353.i_imu_logger.scl_en
testbench353.i_x353.i_imu_logger.sda
testbench353.i_x353.i_imu_logger.sda_en
@22 @22
testbench353.i_x353.i_imu_logger.sec[31:0] testbench353.i_x353.i_mcontr.i_descrproc.mancmd[17:0]
@28 @28
testbench353.i_x353.i_imu_logger.ser_di testbench353.i_x353.i_mcontr.i_descrproc.mcs[0]
testbench353.i_x353.i_imu_logger.ser_do
testbench353.i_x353.i_imu_logger.ser_do_stb
@22 @22
testbench353.i_x353.i_imu_logger.timestamp_ackn[3:0] testbench353.i_x353.i_mcontr.i_descrproc.mdi[17:0]
testbench353.i_x353.i_imu_logger.timestamp_request[3:0] testbench353.i_x353.i_mcontr.i_descrproc.mdo1[17:0]
testbench353.i_x353.i_imu_logger.timestamp_request_long[3:0] testbench353.i_x353.i_mcontr.i_descrproc.mdo2[21:0]
testbench353.i_x353.i_mcontr.i_descrproc.mdo[31:0]
@28 @28
testbench353.i_x353.i_imu_logger.timestamp_sel[1:0] testbench353.i_x353.i_mcontr.i_descrproc.mode[0]
testbench353.i_x353.i_mcontr.i_descrproc.nBuf[1:0]
@22 @22
testbench353.i_x353.i_imu_logger.timestamps_rdata[15:0] testbench353.i_x353.i_mcontr.i_descrproc.nextBlocksEn[3:0]
testbench353.i_x353.i_mcontr.i_descrproc.nextFrame[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.ts_en testbench353.i_x353.i_mcontr.i_descrproc.notEnoughData[0]
testbench353.i_x353.i_mcontr.i_descrproc.nxtTF_p[2:0]
testbench353.i_x353.i_mcontr.i_descrproc.nxtTFr[0]
testbench353.i_x353.i_mcontr.i_descrproc.nxtTFw[0]
testbench353.i_x353.i_mcontr.i_descrproc.nxtTL[0]
testbench353.i_x353.i_mcontr.i_descrproc.nxtTLw[0]
testbench353.i_x353.i_mcontr.i_descrproc.nxtTf_d[0]
@22 @22
testbench353.i_x353.i_imu_logger.ts_rcv_sec[31:0] testbench353.i_x353.i_mcontr.i_descrproc.padlen[4:0]
testbench353.i_x353.i_imu_logger.ts_rcv_usec[19:0]
@28 @28
testbench353.i_x353.i_imu_logger.ts_stb testbench353.i_x353.i_mcontr.i_descrproc.pre_rovr[0]
testbench353.i_x353.i_imu_logger.ts_stb_rq
@22 @22
testbench353.i_x353.i_imu_logger.usec[19:0] testbench353.i_x353.i_mcontr.i_descrproc.prevStripSource[13:4]
@28
testbench353.i_x353.i_imu_logger.wa
testbench353.i_x353.i_imu_logger.we
testbench353.i_x353.i_imu_logger.we_bitHalfPeriod
testbench353.i_x353.i_imu_logger.we_bit_duration
testbench353.i_x353.i_imu_logger.we_config
testbench353.i_x353.i_imu_logger.we_config_gps
testbench353.i_x353.i_imu_logger.we_config_imu
testbench353.i_x353.i_imu_logger.we_config_msg
testbench353.i_x353.i_imu_logger.we_config_syn
testbench353.i_x353.i_imu_logger.we_d
testbench353.i_x353.i_imu_logger.we_gps
testbench353.i_x353.i_imu_logger.we_imu
testbench353.i_x353.i_imu_logger.we_message
testbench353.i_x353.i_imu_logger.we_period
testbench353.i_x353.i_imu_logger.xclk
@1401200
-IMU
@800200
-imu_spi
@28
testbench353.IMU_103695REVA
@22
testbench353.i_x353.i_imu_logger.config_debug[3:0]
@800022
testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0]
@1001200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.config_single_wire
testbench353.IMU_MOSI_REVA
testbench353.IMU_NMOSI
testbench353.IMU_SCLK
testbench353.IMU_MOSI
testbench353.IMU_CS
testbench353.IMU_ACTIVE
testbench353.IMU_SCLK_OUT
testbench353.IMU_MOSI_OUT
testbench353.IMU_MISO
@23
testbench353.IMU_LOOPBACK[15:0]
@c00022
testbench353.IMU_TAPS[5:1]
@28
(0)testbench353.IMU_TAPS[5:1]
(1)testbench353.IMU_TAPS[5:1]
(2)testbench353.IMU_TAPS[5:1]
(3)testbench353.IMU_TAPS[5:1]
(4)testbench353.IMU_TAPS[5:1]
@1401200
-group_end
@c00028
testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_stb[2:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_stb[2:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_stb[2:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_stb[2:0]
@1401200
-group_end
@800028
testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_r[1:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_r[1:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire_r[1:0]
@1001200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.sngl_wire
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_state[1:0]
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_counter[9:0]
@800022
testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
@1001200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.stall
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi
testbench353.i_x353.i_imu_logger.i_imu_spi.scl
testbench353.i_x353.i_imu_logger.i_imu_spi.sda
testbench353.IMU_DATA_READY
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_ready_reset
@c00022
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(4)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
(5)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_data_ready[5:0]
@1401200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.skip_stall
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.stall_cntr[7:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.stall
testbench353.i_x353.i_imu_logger.i_imu_spi.set_stall
testbench353.i_x353.i_imu_logger.i_imu_spi.set_mosi_spi
testbench353.i_x353.i_imu_logger.i_imu_spi.shift_mosi
@c00022
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
@28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(4)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(5)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(6)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(7)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(8)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(9)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(10)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(11)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(12)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(13)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(14)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
(15)testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
@1401200
-group_end
@28
testbench353.IMU_MOSI
testbench353.IMU_SCL
testbench353.IMU_CS
testbench353.IMU_MISO
testbench353.i_x353.i_imu_logger.i_imu_spi.stall
testbench353.i_x353.i_imu_logger.i_imu_spi.miso
testbench353.i_x353.i_imu_logger.i_imu_spi.shift_mosi
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.miso_reg[15:0]
@28 @28
testbench353.i_x353.i_imu_logger.i_imu_spi.shift_miso testbench353.i_x353.i_mcontr.i_descrproc.rNum[1:0]
testbench353.i_x353.i_mcontr.i_descrproc.resetDestBond[0]
@22 @22
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_in_buf[15:0] testbench353.i_x353.i_mcontr.i_descrproc.restart[3:0]
@28 @28
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_wr_buf testbench353.i_x353.i_mcontr.i_descrproc.restart_en[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.last_buf_wr testbench353.i_x353.i_mcontr.i_descrproc.restart_en_sync[0]
@22 @22
testbench353.i_x353.i_imu_logger.i_imu_spi.bit_duration[7:0] testbench353.i_x353.i_mcontr.i_descrproc.rnTilesY[13:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.bit_duration_cntr[7:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.bit_duration_mclk[7:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.bit_duration_zero
testbench353.i_x353.i_imu_logger.i_imu_spi.clk_div[1:0]
@c00022
testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0]
@28 @28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0] testbench353.i_x353.i_mcontr.i_descrproc.rovr[0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0] testbench353.i_x353.i_mcontr.i_descrproc.rqInitS[0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0] testbench353.i_x353.i_mcontr.i_descrproc.rqInit[0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.clk_en[3:0] testbench353.i_x353.i_mcontr.i_descrproc.rst[0]
@1401200
-group_end
@22 @22
testbench353.i_x353.i_imu_logger.i_imu_spi.config_debug[3:0] testbench353.i_x353.i_mcontr.i_descrproc.sa[24:3]
testbench353.i_x353.i_mcontr.i_descrproc.seq_par[5:0]
@28 @28
testbench353.i_x353.i_imu_logger.i_imu_spi.config_late_clk testbench353.i_x353.i_mcontr.i_descrproc.setDestBond[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.config_long_sda_en testbench353.i_x353.i_mcontr.i_descrproc.setLineNumDest[0]
testbench353.i_x353.i_mcontr.i_descrproc.setLineNumSource[0]
testbench353.i_x353.i_mcontr.i_descrproc.setSourceBond[0]
@22 @22
testbench353.i_x353.i_imu_logger.i_imu_spi.di[15:0] testbench353.i_x353.i_mcontr.i_descrproc.sfa[24:8]
testbench353.i_x353.i_imu_logger.i_imu_spi.di_d[15:0]
@28 @28
testbench353.i_x353.i_imu_logger.i_imu_spi.en testbench353.i_x353.i_mcontr.i_descrproc.srcAtStart[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.end_prepare testbench353.i_x353.i_mcontr.i_descrproc.stepsDwe[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.end_spi testbench353.i_x353.i_mcontr.i_descrproc.stepsEn012[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.first_prepare
testbench353.i_x353.i_imu_logger.i_imu_spi.first_prepare_d[1:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_enabled[1:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_enabled_mclk
@22 @22
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_in_buf[15:0] testbench353.i_x353.i_mcontr.i_descrproc.stepsEn[3:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_in_word[4:0]
@28 @28
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_wr_buf testbench353.i_x353.i_mcontr.i_descrproc.stepsI[0]
testbench353.i_x353.i_mcontr.i_descrproc.stepsIe[0]
@22 @22
testbench353.i_x353.i_imu_logger.i_imu_spi.miso_reg[15:0] testbench353.i_x353.i_mcontr.i_descrproc.steps[3:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_reg_number[6:1] testbench353.i_x353.i_mcontr.i_descrproc.suspXfer[3:0]
@28 testbench353.i_x353.i_mcontr.i_descrproc.tileX[9:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_run[1:0] testbench353.i_x353.i_mcontr.i_descrproc.tileY[13:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_run_confirmed
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_run_mclk
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_first
@c00028
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_grant[1:0]
@28 @28
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_grant[1:0] testbench353.i_x353.i_mcontr.i_descrproc.updSuspXfer[0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_grant[1:0]
@1401200 @1401200
-group_end -descrproc
@28 @200
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_start_mclk -
testbench353.i_x353.i_imu_logger.i_imu_spi.imu_wr_buf @800200
testbench353.i_x353.i_imu_logger.i_imu_spi.last_bit -debug_memcntr
testbench353.i_x353.i_imu_logger.i_imu_spi.last_bit_ext @28
testbench353.i_x353.i_imu_logger.i_imu_spi.last_buf_wr testbench353.i_x353.i_mcontr.i_sdseq.clk0[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.miso testbench353.i_x353.i_mcontr.i_sdseq.rst[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi testbench353.i_x353.i_mcontr.i_sdseq.prerw[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.set_mosi_spi @22
@22 testbench353.i_x353.i_mcontr.i_sdseq.mancmd[17:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.mosi_reg[15:0] testbench353.i_x353.i_mcontr.i_sdseq.prea[12:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.period[31:0] @28
testbench353.i_x353.i_imu_logger.i_imu_spi.period_counter[31:0] testbench353.i_x353.i_mcontr.i_sdseq.first[0]
@28 @22
testbench353.i_x353.i_imu_logger.i_imu_spi.pre_imu_wr_buf testbench353.i_x353.i_mcontr.i_sdseq.fullAddr[24:3]
testbench353.i_x353.i_imu_logger.i_imu_spi.pre_seq_counter_zero @28
@22 testbench353.i_x353.i_mcontr.i_sdseq.pre1act_m1d2[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.raddr[4:0] testbench353.i_x353.i_mcontr.i_sdseq.preact[0]
@28 testbench353.i_x353.i_mcontr.i_sdseq.continue_m1[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.rd_stb testbench353.i_x353.i_mcontr.i_sdseq.precontinue_m1[0]
@c00022 testbench353.i_x353.i_mcontr.i_sdseq.pre2prech_m[0]
testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.pre6prech_m[0]
@28 testbench353.i_x353.i_mcontr.i_sdseq.drun_wr[0]
(0)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.pre7prech_m[1:0]
(1)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.prenext_m1s[0]
(2)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.prenext_m1d[0]
(3)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] @22
(4)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.left[4:0]
(5)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] @28
(6)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.mode[0]
(7)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.prenext_m0[0]
(8)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.prenext_m0r[0]
(9)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.start_m0r[0]
(10)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.prenext_m0w1[0]
(11)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.start_m0w[0]
(12)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] @23
(13)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0] testbench353.i_x353.i_mcontr.i_sdseq.param[5:0]
(14)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
(15)testbench353.i_x353.i_imu_logger.i_imu_spi.rdata[15:0]
@1401200
-group_end
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.rdy
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.reg_seq_number[4:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.scl
testbench353.i_x353.i_imu_logger.i_imu_spi.scl_d
testbench353.i_x353.i_imu_logger.i_imu_spi.scl_en
testbench353.i_x353.i_imu_logger.i_imu_spi.sclk
testbench353.i_x353.i_imu_logger.i_imu_spi.sda
testbench353.i_x353.i_imu_logger.i_imu_spi.sda_d
testbench353.i_x353.i_imu_logger.i_imu_spi.sda_en
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_counter[9:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_counter_zero
testbench353.i_x353.i_imu_logger.i_imu_spi.seq_state[1:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.set_mosi_prepare
testbench353.i_x353.i_imu_logger.i_imu_spi.set_mosi_spi
testbench353.i_x353.i_imu_logger.i_imu_spi.set_stall
testbench353.i_x353.i_imu_logger.i_imu_spi.shift_miso
testbench353.i_x353.i_imu_logger.i_imu_spi.skip_stall
testbench353.i_x353.i_imu_logger.i_imu_spi.stall
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.stall_cntr[7:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.stall_dur[7:0]
testbench353.i_x353.i_imu_logger.i_imu_spi.stall_dur_mclk[7:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.ts
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.wa[4:0]
@28
testbench353.i_x353.i_imu_logger.i_imu_spi.we_div
testbench353.i_x353.i_imu_logger.i_imu_spi.we_period
testbench353.i_x353.i_imu_logger.i_imu_spi.we_ra
@22
testbench353.i_x353.i_imu_logger.i_imu_spi.we_timer[4:1]
@28 @28
testbench353.i_x353.i_imu_logger.i_imu_spi.xclk testbench353.i_x353.i_mcontr.i_sdseq.continue_m0[0]
@1000200 @1000200
-imu_spi -debug_memcntr
@c00200 @200
-rs232_rcv -
@22 @800200
testbench353.i_x353.i_imu_logger.i_rs232_rcv.bitHalfPeriod[15:0] -sdseq
testbench353.i_x353.i_imu_logger.i_rs232_rcv.bit_cntr[4:0] @28
testbench353.i_x353.i_imu_logger.i_rs232_rcv.bit_dur_cntr[15:0] testbench353.i_x353.i_mcontr.i_sdseq.chsel[1:0]
@28 testbench353.i_x353.i_mcontr.i_sdseq.clk0[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.bit_half_end testbench353.i_x353.i_mcontr.i_sdseq.continue_m0[0]
@22 testbench353.i_x353.i_mcontr.i_sdseq.continue_m1[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.debug0[4:0] testbench353.i_x353.i_mcontr.i_sdseq.decLeft[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.debug[4:0] testbench353.i_x353.i_mcontr.i_sdseq.dlast[0]
@28 testbench353.i_x353.i_mcontr.i_sdseq.dmask[1:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.error testbench353.i_x353.i_mcontr.i_sdseq.dqs_re[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.last_half_bit testbench353.i_x353.i_mcontr.i_sdseq.drun_rd[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.receiving_byte testbench353.i_x353.i_mcontr.i_sdseq.drun_wr[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.reset_bit_duration testbench353.i_x353.i_mcontr.i_sdseq.dsel[1:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.reset_wait_pause testbench353.i_x353.i_mcontr.i_sdseq.first[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.restart[1:0] @22
testbench353.i_x353.i_imu_logger.i_rs232_rcv.sample_bit testbench353.i_x353.i_mcontr.i_sdseq.fullAddr[24:3]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_di testbench353.i_x353.i_mcontr.i_sdseq.left[4:0]
@22 testbench353.i_x353.i_mcontr.i_sdseq.mancmd[17:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_di_d[4:0] @28
@28 testbench353.i_x353.i_mcontr.i_sdseq.mode[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_do testbench353.i_x353.i_mcontr.i_sdseq.mode_r[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_do_stb @22
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_filt_di testbench353.i_x353.i_mcontr.i_sdseq.nextAddr[24:3]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_filt_di_d testbench353.i_x353.i_mcontr.i_sdseq.nextPageAddr[24:10]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ser_rst @28
testbench353.i_x353.i_imu_logger.i_rs232_rcv.shift_en testbench353.i_x353.i_mcontr.i_sdseq.next[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.start @22
testbench353.i_x353.i_imu_logger.i_rs232_rcv.ts_stb testbench353.i_x353.i_mcontr.i_sdseq.param[5:0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.wait_just_pause @28
testbench353.i_x353.i_imu_logger.i_rs232_rcv.wait_pause testbench353.i_x353.i_mcontr.i_sdseq.possible_dual[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.wait_start testbench353.i_x353.i_mcontr.i_sdseq.pre1act_m1d2[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.wstart testbench353.i_x353.i_mcontr.i_sdseq.pre2act_m1d2[0]
testbench353.i_x353.i_imu_logger.i_rs232_rcv.xclk testbench353.i_x353.i_mcontr.i_sdseq.pre2firstdrun_rd[0]
@1401200 testbench353.i_x353.i_mcontr.i_sdseq.pre2prech_m1d1[0]
-rs232_rcv testbench353.i_x353.i_mcontr.i_sdseq.pre2prech_m[0]
>>>>>>> 1.14 testbench353.i_x353.i_mcontr.i_sdseq.pre2read[0]
testbench353.i_x353.i_mcontr.i_sdseq.pre2read_next8[0]
testbench353.i_x353.i_mcontr.i_sdseq.pre2refr[0]
testbench353.i_x353.i_mcontr.i_sdseq.pre2trist[0]
testbench353.i_x353.i_mcontr.i_sdseq.pre2write[0]
testbench353.i_x353.i_mcontr.i_sdseq.pre2write_next8[0]
testbench353.i_x353.i_mcontr.i_sdseq.pre4drun_rd[0]
testbench353.i_x353.i_mcontr.i_sdseq.pre4drun_rd_abort[0]
testbench353.i_x353.i_mcontr.i_sdseq.pre6prech_m[0]
testbench353.i_x353.i_mcontr.i_sdseq.pre7prech_m[1:0]
testbench353.i_x353.i_mcontr.i_sdseq.pre_next_old[0]
@22
testbench353.i_x353.i_mcontr.i_sdseq.prea[12:0]
@28
testbench353.i_x353.i_mcontr.i_sdseq.preact[0]
testbench353.i_x353.i_mcontr.i_sdseq.preb[1:0]
testbench353.i_x353.i_mcontr.i_sdseq.precmd[2:0]
testbench353.i_x353.i_mcontr.i_sdseq.precontinue_m1[0]
testbench353.i_x353.i_mcontr.i_sdseq.predlast_rd[0]
testbench353.i_x353.i_mcontr.i_sdseq.predlast_wr[0]
testbench353.i_x353.i_mcontr.i_sdseq.predmask[0]
testbench353.i_x353.i_mcontr.i_sdseq.predqs_re[0]
testbench353.i_x353.i_mcontr.i_sdseq.predqt[0]
testbench353.i_x353.i_mcontr.i_sdseq.predrun_rd[0]
testbench353.i_x353.i_mcontr.i_sdseq.predrun_wr[0]
testbench353.i_x353.i_mcontr.i_sdseq.predrun_wr_abort[0]
testbench353.i_x353.i_mcontr.i_sdseq.prefirst[0]
testbench353.i_x353.i_mcontr.i_sdseq.prefirstdrun[0]
testbench353.i_x353.i_mcontr.i_sdseq.prenext_m0[0]
testbench353.i_x353.i_mcontr.i_sdseq.prenext_m0r[0]
testbench353.i_x353.i_mcontr.i_sdseq.prenext_m0w1[0]
testbench353.i_x353.i_mcontr.i_sdseq.prenext_m1d[0]
testbench353.i_x353.i_mcontr.i_sdseq.prenext_m1s[0]
testbench353.i_x353.i_mcontr.i_sdseq.prenext_refr[0]
testbench353.i_x353.i_mcontr.i_sdseq.prenext_wr[0]
testbench353.i_x353.i_mcontr.i_sdseq.preprech[0]
testbench353.i_x353.i_mcontr.i_sdseq.preread[0]
testbench353.i_x353.i_mcontr.i_sdseq.prerefr[0]
testbench353.i_x353.i_mcontr.i_sdseq.prerw[0]
testbench353.i_x353.i_mcontr.i_sdseq.prewrite[0]
testbench353.i_x353.i_mcontr.i_sdseq.refr[0]
testbench353.i_x353.i_mcontr.i_sdseq.repeat_r[0]
testbench353.i_x353.i_mcontr.i_sdseq.repeat_r_end[0]
testbench353.i_x353.i_mcontr.i_sdseq.repeat_w[0]
testbench353.i_x353.i_mcontr.i_sdseq.rollover[0]
testbench353.i_x353.i_mcontr.i_sdseq.rovr[0]
testbench353.i_x353.i_mcontr.i_sdseq.rst[0]
@22
testbench353.i_x353.i_mcontr.i_sdseq.sa[24:3]
@28
testbench353.i_x353.i_mcontr.i_sdseq.setNextAddr[0]
@22
testbench353.i_x353.i_mcontr.i_sdseq.sfa[24:8]
@28
testbench353.i_x353.i_mcontr.i_sdseq.start_m0r[0]
testbench353.i_x353.i_mcontr.i_sdseq.start_m0w[0]
testbench353.i_x353.i_mcontr.i_sdseq.start_m1[0]
testbench353.i_x353.i_mcontr.i_sdseq.startf_m1[0]
testbench353.i_x353.i_mcontr.i_sdseq.wnr[0]
testbench353.i_x353.i_mcontr.i_sdseq.xfer[0]
@1000200
-sdseq
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
x353_1.tf
View file @ d6e9be6b
...@@ -27,9 +27,11 @@ ...@@ -27,9 +27,11 @@
`define TEST_BAD_FRAME //abbreviate one frame `define TEST_BAD_FRAME //abbreviate one frame
`define TEST_IMU ///AF2015 `define TEST_IMU
module testbench353(); module testbench353();
reg [639:0] TEST_TITLE; //SuppressThisWarning Veditor Simulator wave
parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses
parameter FPGA_XTRA_CYCLES= 1500; // 1072+; parameter FPGA_XTRA_CYCLES= 1500; // 1072+;
parameter HISTOGRAM_LEFT= 0; //2; // left parameter HISTOGRAM_LEFT= 0; //2; // left
...@@ -41,6 +43,7 @@ module testbench353(); ...@@ -41,6 +43,7 @@ module testbench353();
parameter CLK3_PER = 83.33; //12MHz parameter CLK3_PER = 83.33; //12MHz
parameter CPU_PER=10.4; parameter CPU_PER=10.4;
`ifdef IVERILOG `ifdef IVERILOG
`define SIMULATION 1
initial $display("IVERILOG is defined"); initial $display("IVERILOG is defined");
`include "IVERILOG_INCLUDE.v" `include "IVERILOG_INCLUDE.v"
`else `else
...@@ -64,7 +67,7 @@ module testbench353(); ...@@ -64,7 +67,7 @@ module testbench353();
parameter BLANK_ROWS_BEFORE=1; //8; ///2+2 - a little faster than compressor parameter BLANK_ROWS_BEFORE=1; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 1; //8; parameter BLANK_ROWS_AFTER= 1; //8;
parameter TRIG_LINES= 8; parameter TRIG_LINES= 8;
parameter VBLANK= 2; /// 2 lines parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED
parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG
`ifdef PF `ifdef PF
...@@ -78,9 +81,9 @@ module testbench353(); ...@@ -78,9 +81,9 @@ module testbench353();
`endif `endif
parameter VIRTUAL_WIDTH= FULL_WIDTH+HBLANK; parameter VIRTUAL_WIDTH= FULL_WIDTH+HBLANK;
parameter VIRTUAL_HEIGHT= FULL_HEIGHT+BLANK_ROWS_BEFORE+BLANK_ROWS_AFTER; parameter VIRTUAL_HEIGHT= FULL_HEIGHT+BLANK_ROWS_BEFORE+BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED
parameter TRIG_INTERFRAME=100; /// extra 100 clock cycles between frames parameter TRIG_INTERFRAME=100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED
// parameter TRIG_OUT_DATA= 'h800000; // external cable // parameter TRIG_OUT_DATA= 'h800000; // external cable
parameter TRIG_OUT_DATA= 'h80000; // internal cable parameter TRIG_OUT_DATA= 'h80000; // internal cable
parameter TRIG_EXTERNAL_INPUT= 'h20000; // internal cable, low level on EXT[8] parameter TRIG_EXTERNAL_INPUT= 'h20000; // internal cable, low level on EXT[8]
...@@ -113,21 +116,24 @@ module testbench353(); ...@@ -113,21 +116,24 @@ module testbench353();
parameter X313_WA_DCR0_TRIGDIS= 'h100000; parameter X313_WA_DCR0_TRIGDIS= 'h100000;
parameter X313_WA_DCR0_ENDFRAMESEN= 'h600000; parameter X313_WA_DCR0_ENDFRAMESEN= 'h600000;
parameter X313_WA_DCR0_ENDFRAMESDIS= 'h400000; parameter X313_WA_DCR0_ENDFRAMESDIS= 'h400000; //SuppressThisWarning Veditor UNUSED
parameter X353_WA_DCR0_RESET_MCONTREN= 'h60; // 1 - enable reset memory controllers (channles 0,1,2) at each frame parameter X353_WA_DCR0_RESET_MCONTREN= 'h60; // 1 - enable reset memory controllers (channles 0,1,2) at each frame
parameter X353_WA_DCR0_RESET_MCONTRDIS= 'h40; // 0 - disable reset memory controllers (channles 0,1,2) at each frame parameter X353_WA_DCR0_RESET_MCONTRDIS= 'h40; // 0 - disable reset memory controllers (channles 0,1,2) at each frame //SuppressThisWarning Veditor UNUSED
parameter X313_WA_IOPINS= 'h70; // bits [31:24] - enable channels (channel 0 -software, enabled at FPGA init) parameter X313_WA_IOPINS= 'h70; // bits [31:24] - enable channels (channel 0 -software, enabled at FPGA init)
parameter X313_WA_IOPINS_EN_TRIG_OUT= 'h0c000000; parameter X313_WA_IOPINS_EN_TRIG_OUT= 'h0c000000;
parameter X313_WA_IOPINS_DIS_TRIG_OUT='h08000000; parameter X313_WA_IOPINS_DIS_TRIG_OUT='h08000000; //SuppressThisWarning Veditor UNUSED
parameter X313_WA_IOPINS_EN_IMU_OUT= 'hc0000000;
parameter X313_WA_IOPINS_DIS_IMU_OUT='h80000000;
parameter X313_WA_IMU_DATA= 'h7e;
`ifdef TEST_IMU
parameter X313_WA_IOPINS_EN_IMU_OUT= 'hc0000000;
parameter X313_WA_IOPINS_DIS_IMU_OUT='h80000000; //SuppressThisWarning Veditor UNUSED
parameter X313_WA_IMU_CTRL= 'h7f; parameter X313_WA_IMU_CTRL= 'h7f;
parameter X313_WA_IMU_DATA= 'h7e;
parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check) parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready
parameter IMU_PERIOD= 'h800; // normal period parameter IMU_PERIOD= 'h800; // normal period
...@@ -137,19 +143,16 @@ module testbench353(); ...@@ -137,19 +143,16 @@ module testbench353();
parameter IMU_READY_PERIOD=100000; //100usec parameter IMU_READY_PERIOD=100000; //100usec
parameter IMU_NREADY_DURATION=10000; //10usec parameter IMU_NREADY_DURATION=10000; //10usec
parameter IMU_GPS_BIT_PERIOD='h20; // serial communication duration of a bit (in system clocks) parameter IMU_GPS_BIT_PERIOD='h20; // serial communication duration of a bit (in system clocks)
// use start of trigger as a timestamp (in async mode to prevent timestamp jitter) // use start of trigger as a timestamp (in async mode to prevent timestamp jitter)
// parameter X313_WA_DCR1_EARLYTRIGEN='hc; //OBSOLETE! // parameter X313_WA_DCR1_EARLYTRIGEN='hc; //OBSOLETE!
// parameter X313_WA_DCR1_EARLYTRIGDIS='h8; // parameter X313_WA_DCR1_EARLYTRIGDIS='h8;
`endif
parameter X313_WA_DCR1_EXTERNALTSEN='hc; parameter X313_WA_DCR1_EXTERNALTSEN='hc;
parameter X313_WA_DCR1_EXTERNALTSDIS='h8; parameter X313_WA_DCR1_EXTERNALTSDIS='h8; //SuppressThisWarning Veditor UNUSED
parameter X313_WA_DCR1_OUTPUTTSEN= 'h300000; parameter X313_WA_DCR1_OUTPUTTSEN= 'h300000;
parameter X313_WA_DCR1_OUTPUTTSDIS='h200000; parameter X313_WA_DCR1_OUTPUTTSDIS='h200000; //SuppressThisWarning Veditor UNUSED
...@@ -224,87 +227,34 @@ module testbench353(); ...@@ -224,87 +227,34 @@ module testbench353();
// parameter CLK1_PER = 10.4; //96MHz // parameter CLK1_PER = 10.4; //96MHz
// parameter CLK3_PER = 83.33; //12MHz // parameter CLK3_PER = 83.33; //12MHz
// parameter CPU_PER=10.4; // parameter CPU_PER=10.4;
parameter DMA_BURST=8; parameter DMA_BURST=8; //SuppressThisWarning Veditor UNUSED
reg TEST_CPU_WR_OK; ///AF: reg TEST_CPU_WR_OK;
reg TEST_CPU_RD_OK; ///AF: reg TEST_CPU_RD_OK;
reg SERIAL_BIT = 1'b1; reg SERIAL_BIT = 1'b1; // SuppressThisWarning Veditor UNUSED - simulator test WAVE
reg GPS1SEC = 1'b0; reg GPS1SEC = 1'b0; // SuppressThisWarning Veditor UNUSED - simulator test WAVE
reg ODOMETER_PULSE= 1'b0; reg ODOMETER_PULSE= 1'b0;// SuppressThisWarning Veditor UNUSED - simulator test WAVE
integer SERIAL_DATA_FD; integer SERIAL_DATA_FD; // SuppressThisWarning Veditor UNUSED - simulator test WAVE
reg IMU_DATA_READY; reg IMU_DATA_READY; // SuppressThisWarning Veditor UNUSED - simulator test WAVE
/* /*
parameter IMU_READY_PERIOD=100000; //100usec parameter IMU_READY_PERIOD=100000; //100usec
parameter IMU_NREADY_DURATION=10000; //10usec parameter IMU_NREADY_DURATION=10000; //10usec
*/ */
`ifdef TEST_IMU wire [11:0] EXT; // bidirectional
//wire [11:0] EXT; // bidirectional
wire IMU_SCL=EXT[0];
wire IMU_SDA=EXT[1];
wire IMU_MOSI=EXT[2];
wire IMU_MISO=EXT[3];
reg IMU_EN;
wire IMU_ACTIVE;
wire IMU_NMOSI=!IMU_MOSI;
wire [5:1] IMU_TAPS;
reg IMU_LATE_ACKN;
reg IMU_SCLK;
reg IMU_MOSI_REVA;
reg IMU_103695REVA;
wire IMU_MOSI_OUT;
wire IMU_SCLK_OUT;
assign IMU_MOSI_OUT=IMU_103695REVA?IMU_MOSI_REVA:IMU_MOSI;
assign IMU_SCLK_OUT=IMU_103695REVA?(IMU_SCLK):IMU_SCL;
always @ (posedge IMU_SDA) begin
IMU_EN<=IMU_MOSI;
end
wire IMU_CS=IMU_103695REVA?!IMU_ACTIVE:!(IMU_EN &&IMU_SDA);
reg IMU_MOSI_D;
always @ (posedge IMU_SCLK_OUT) begin
// IMU_MOSI_D<=IMU_MOSI;
IMU_MOSI_D<=IMU_MOSI_OUT;
end
reg [15:0] IMU_LOOPBACK;
always @ (negedge IMU_SCLK_OUT) begin
if (!IMU_CS) IMU_LOOPBACK[15:0]<={IMU_LOOPBACK[14:0],IMU_MOSI_D};
end
assign EXT[3]=IMU_CS?IMU_DATA_READY:IMU_LOOPBACK[15];
PULLUP i_IMU_SDA (.O(IMU_SDA));
PULLUP i_IMU_SCL (.O(IMU_SCL));
initial begin
SERIAL_DATA_FD=$fopen("gps_data.dat","r");
end
always begin
#(IMU_READY_PERIOD-IMU_NREADY_DURATION) IMU_DATA_READY=1'b0;
#(IMU_NREADY_DURATION) IMU_DATA_READY=1'b1;
end
assign EXT[4]=SERIAL_BIT;
assign EXT[5]=GPS1SEC;
assign EXT[6]=ODOMETER_PULSE;
oneshot i_oneshot (.trigger(IMU_NMOSI),
.out(IMU_ACTIVE));
dly5taps i_dly5taps (.dly_in(IMU_NMOSI),
.dly_out(IMU_TAPS[5:1]));
always @ (negedge IMU_ACTIVE or posedge IMU_TAPS[5]) if (!IMU_ACTIVE) IMU_LATE_ACKN<= 1'b0; else IMU_LATE_ACKN<= 1'b1;
always @ (negedge IMU_LATE_ACKN or posedge IMU_TAPS[4]) if (!IMU_LATE_ACKN) IMU_SCLK<= 1'b1; else IMU_SCLK<= ~IMU_SCLK;
always @ (negedge IMU_SCLK) IMU_MOSI_REVA<= IMU_NMOSI;
`ifdef TEST_IMU
`include "imu_sim_init_include.vh"
`endif `endif
// Inputs // Inputs
wire [11:0] PXD; wire [11:0] PXD;
wire BPF; wire BPF;
wire HACT; wire HACT;
wire VACT; wire VACT;
wire VACT1CYCLE; //SuppressThisWarning Veditor UNUSED
reg TTRIG; reg TTRIG;
reg CLK3; reg CLK3;
reg CLK2; reg CLK2; //SuppressThisWarning Veditor UNUSED
reg CLK1; reg CLK1;
reg CLK0; reg CLK0;
// reg SDCLK_DLL; // reg SDCLK_DLL;
...@@ -320,20 +270,20 @@ reg IMU_DATA_READY; ...@@ -320,20 +270,20 @@ reg IMU_DATA_READY;
reg [31:0] CPU_DO; reg [31:0] CPU_DO;
reg CPU_OE; // enable data from CPU to D[31:0] reg CPU_OE; // enable data from CPU to D[31:0]
reg [31:0] CPU_DI; reg [31:0] CPU_DI;
reg [31:0] DMA_DI; reg [31:0] DMA_DI; //SuppressThisWarning Veditor UNUSED
reg [31:0] DMA_DI_1; reg [31:0] DMA_DI_1; //SuppressThisWarning Veditor UNUSED
reg [31:0] DMA_CNTR; ///AF: reg [31:0] DMA_CNTR;
reg [31:0] DMA_CNTR_1; ///AF: reg [31:0] DMA_CNTR_1;
reg [11:0] SDRAM_MODE; // shadow register for SDRAM controller modes reg [11:0] SDRAM_MODE; // shadow register for SDRAM controller modes
// Outputs // Outputs
wire DCLK; wire DCLK;
wire MRST; wire MRST;
wire ARO; wire ARO;
wire ARST; wire ARST;
wire CNVSYNC; ///AF: wire CNVSYNC;
wire CNVCLK; ///AF: wire CNVCLK;
wire XRST; ///AF: wire XRST;
wire AUXCLK; ///AF: wire AUXCLK;
wire [14:0] SDA; wire [14:0] SDA;
wire SDCLK, SDNCLK; wire SDCLK, SDNCLK;
// wire SDCKE; // wire SDCKE;
...@@ -353,11 +303,11 @@ reg IMU_DATA_READY; ...@@ -353,11 +303,11 @@ reg IMU_DATA_READY;
// Bidirs // Bidirs
wire SCL0; wire SCL0;
wire SCL1; ///AF: wire SCL1;
wire SDA0; wire SDA0;
wire SDA1; ///AF: wire SDA1;
wire EXPS; ///AF: wire EXPS;
wire TRIG; wire TRIG; //SuppressThisWarning Veditor UNUSED
wire [15:0] SDD; wire [15:0] SDD;
wire [31:0] D; wire [31:0] D;
wire LDQS; wire LDQS;
...@@ -379,10 +329,10 @@ parameter BUSOP_IO_RD1= 7; ...@@ -379,10 +329,10 @@ parameter BUSOP_IO_RD1= 7;
reg [7:0] BUS; // Vector of currently active bus operations reg [7:0] BUS; // Vector of currently active bus operations
reg CPU_IO; // CPU IO in progress, may not start IO/DMA reg CPU_IO; // CPU IO in progress, may not start IO/DMA //SuppressThisWarning Veditor UNUSED
// integer LOCK; // integer LOCK;
reg [10:0] LOCK_ADDR; // LSB - address, 3 MSBs: 0 - read, 1 - write, 2 - DMA0, 3 - DMA1, 4 - INTA ///AF: reg [10:0] LOCK_ADDR; // LSB - address, 3 MSBs: 0 - read, 1 - write, 2 - DMA0, 3 - DMA1, 4 - INTA
reg [31:0] LOCK_DATA; // Data wants to write ///AF: reg [31:0] LOCK_DATA; // Data wants to write
// reg DMA_EN; // reg DMA_EN;
// reg DMA_EN_1; // reg DMA_EN_1;
assign D[31:0]=CPU_OE? CPU_DO[31:0]: 32'bz; assign D[31:0]=CPU_OE? CPU_DO[31:0]: 32'bz;
...@@ -394,25 +344,26 @@ parameter BUSOP_IO_RD1= 7; ...@@ -394,25 +344,26 @@ parameter BUSOP_IO_RD1= 7;
integer histogram_total; integer histogram_total;
reg [9:0] histogram_count; reg [9:0] histogram_count;
reg [23:0] IMG_POINTER; reg [23:0] IMG_POINTER; //SuppressThisWarning Veditor UNUSED
reg [1:0] FOCUS_MODE; reg [1:0] FOCUS_MODE;
reg BLOCK_HACT=0; reg BLOCK_HACT=0;
assign TRIG=TTRIG; assign TRIG=TTRIG;
reg [2:0] I2C_FRAME; // frame number modulo 8 as seen in i2c_writeonly reg [2:0] I2C_FRAME; // frame number modulo 8 as seen in i2c_writeonly //SuppressThisWarning Veditor UNUSED
// ************************* Instantiate the X353 **************************** // ************************* Instantiate the X353 ****************************
wire [11:0] EXT; // bidirectional
assign SYSTEM_A[12:0]={5'b0,A[7:0]}; // will make it tri-state when testing bus acquisition assign SYSTEM_A[12:0]={5'b0,A[7:0]}; // will make it tri-state when testing bus acquisition
wire SENSPGM,DUMMYVFEF,ALWAYS0; wire SENSPGM,DUMMYVFEF,ALWAYS0;
wire SDCLKE; wire SDCLKE;
wire [1:0] BA; // don't need now wire [1:0] BA; // don't need now //SuppressThisWarning Veditor UNUSED
wire SYS_SDWE, SYS_SDCAS, SYS_SDRAS, SYS_SDCLKI, SYS_SDCLK, SYS_BUSEN, BG, BRIN, BROUT; wire SYS_SDWE, SYS_SDCAS, SYS_SDRAS, SYS_SDCLK, SYS_BUSEN, BG, BROUT; //SuppressThisWarning Veditor UNUSED
wire SYS_SDCLKI = 1'bx; // not tested
wire BRIN = 1'bx; // not tested
/// connect external sync /// connect external sync
assign EXT[8]=EXT[9]; assign EXT[8]=EXT[9];
wire external_sync_line=~EXT[9]; wire external_sync_line=~EXT[9]; //SuppressThisWarning Veditor UNUSED
x353 i_x353 ( x353 i_x353 (
.PXD(PXD[11:2]), .PXD(PXD[11:2]),
.DCLK(DCLK), .DCLK(DCLK),
...@@ -481,7 +432,7 @@ x353 i_x353 ( ...@@ -481,7 +432,7 @@ x353 i_x353 (
// Instance of Micron MT48LC8M16LFFF8 // Instance of Micron MT48LC8M16LFFF8
// cheating - no such actual signal :-( // cheating - no such actual signal :-(
reg SDCKE; reg SDCKE; //SuppressThisWarning Veditor UNUSED
initial begin initial begin
SDCKE=0; SDCKE=0;
#1000; #1000;
...@@ -520,7 +471,9 @@ sensor12bits i_sensor12bits(.MCLK(DCLK), // Master clock ...@@ -520,7 +471,9 @@ sensor12bits i_sensor12bits(.MCLK(DCLK), // Master clock
.DCLK(BPF), // Data output clock .DCLK(BPF), // Data output clock
.BPF(), // Black Pixel Flag .BPF(), // Black Pixel Flag
.HACT(HACT), // Horizontal Active .HACT(HACT), // Horizontal Active
.VACT(VACT) .VACT(VACT),
.VACT1(VACT1CYCLE) // output
);// Vertical Active );// Vertical Active
// testing end of SDRAM page - process 17 tiles starting at the 3-rd 128-words ina 512 words page // testing end of SDRAM page - process 17 tiles starting at the 3-rd 128-words ina 512 words page
...@@ -561,13 +514,13 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a ...@@ -561,13 +514,13 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
initial begin initial begin
// $dumpfile("x353.lxt"); // $dumpfile("x353.lxt");
$dumpfile(lxtname); $dumpfile(lxtname);
$dumpvars(0,testbench353); $dumpvars(0,testbench353); //testbench353 cannot be resolved to a signal or parameter //SuppressThisWarning Veditor
TTRIG = 1; TTRIG = 1;
CLK3 = 0; CLK3 = 0;
CLK2 = 0; CLK2 = 0;
CLK1 = 0; CLK1 = 0;
CLK0 = 0; CLK0 = 0;
A = 8'bx; A = 13'bx;
WE = 1'b1; WE = 1'b1;
OE = 1'b1; OE = 1'b1;
CE = 1'b1; CE = 1'b1;
...@@ -586,7 +539,10 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a ...@@ -586,7 +539,10 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
BUS_EN[7:0] =8'h0; BUS_EN[7:0] =8'h0;
BUS_RQ[7:0] =8'h0; BUS_RQ[7:0] =8'h0;
FOCUS_MODE = 2'h0; FOCUS_MODE = 2'h0;
`ifdef TEST_IMU
IMU_103695REVA = 1'b0; IMU_103695REVA = 1'b0;
`endif
`ifdef LATE_DMA `ifdef LATE_DMA
`else `else
dma_en(0,1); dma_en(0,1);
...@@ -594,373 +550,17 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a ...@@ -594,373 +550,17 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
// temporary for IMU testing // temporary for IMU testing
// #200000; // #200000;
// $finish; // $finish;
#250000;
dma_en(0,1);
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA <= 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
#480000;
//#480000;
$finish;
`ifdef TEST_IMU `ifdef TEST_IMU
`include "imu_sim_include.vh"
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); `endif
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); #200000;
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]); TEST_TITLE = "FIRST_INIT_DONE";
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]); $display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
`endif
$finish;
//#250000;
// dma_en(0,1);
//#480000;
dma_en(0,1);
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA <= 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
#480000;
$finish;
`ifdef TEST_IMU
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
`endif
$finish; $finish;
end
//#250000;
// dma_en(0,1);
//#480000;
#200000;
$finish;
end
// Second async test for IMU
`ifdef TEST_IMU `ifdef TEST_IMU
initial begin initial begin
#10000; #10000;
...@@ -1002,6 +602,9 @@ initial begin ...@@ -1002,6 +602,9 @@ initial begin
TTRIG=0; TTRIG=0;
#1000; #1000;
TTRIG=1; TTRIG=1;
TEST_TITLE = "EXT_TRIG_DONE";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
end end
always #(CLK0_PER/2) CLK0 = ~CLK0; always #(CLK0_PER/2) CLK0 = ~CLK0;
...@@ -1106,6 +709,8 @@ end ...@@ -1106,6 +709,8 @@ end
$display (" FRAME_COMPRESS_CYCLES= %d",FRAME_COMPRESS_CYCLES); $display (" FRAME_COMPRESS_CYCLES= %d",FRAME_COMPRESS_CYCLES);
$display ("FRAME_COMPRESS_CYCLES_INPUT= %d",FRAME_COMPRESS_CYCLES_INPUT); $display ("FRAME_COMPRESS_CYCLES_INPUT= %d",FRAME_COMPRESS_CYCLES_INPUT);
$display ("reset done at %t",$time); $display ("reset done at %t",$time);
TEST_TITLE = "RESET_DONE";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
#10; #10;
...@@ -1148,186 +753,7 @@ end ...@@ -1148,186 +753,7 @@ end
cpu_wr(X313_WA_IOPINS, X313_WA_IOPINS_EN_TRIG_OUT); // Enable GPIO output from camsync module cpu_wr(X313_WA_IOPINS, X313_WA_IOPINS_EN_TRIG_OUT); // Enable GPIO output from camsync module
`ifdef TEST_IMU `ifdef TEST_IMU
`include "imu_sim2_include.vh"
cpu_wr(X313_WA_IOPINS, X313_WA_IOPINS_EN_IMU_OUT); // 'hc0000000;
/*
reg we_config_imu; // bits 1:0, 2 - enable slot[1:0]
reg we_config_gps; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_rst; // bit 16, 17 - enable - reset modules
*/
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
// cpu_wr(X313_WA_IMU_DATA, 'h3e695); // configure channels and reset // gps timestamp from 1sec input, positive
// cpu_wr(X313_WA_IMU_DATA, 'h3e6b5); // configure channels and reset // gps timestamp from 1sec input, negative
// cpu_wr(X313_WA_IMU_DATA, 'h3e6d5); // configure channels and reset // gps timestamp after pause
// cpu_wr(X313_WA_IMU_DATA, 'h3e6f5); // configure channels and reset // gps timestamp at "$" start
cpu_wr(X313_WA_IMU_DATA, 'h43e6f5); // configure channels and reset // gps timestamp at "$" start, reset configure_debug
cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration)
cpu_wr(X313_WA_IMU_DATA, 'h8007); // reset rs232 by 1 in MSB
cpu_wr(X313_WA_IMU_CTRL, 2); // select register number 2 (serial half-bit duration)
cpu_wr(X313_WA_IMU_DATA, 'h0007); // serial speed 8 cycles (period = 32 CLK0 cycles)
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h20000); // remove reset
// encode 4 sentences
/*
$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
*/
cpu_wr(X313_WA_IMU_CTRL, 'h20); // format write
// just ($GP)RMC, GGA, GSA and VTG
cpu_wr(X313_WA_IMU_DATA, 'h6); //
cpu_wr(X313_WA_IMU_DATA, 'hf); //
cpu_wr(X313_WA_IMU_DATA, 'he); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h9); //
cpu_wr(X313_WA_IMU_DATA, 'h7); //
cpu_wr(X313_WA_IMU_DATA, 'h6); //
cpu_wr(X313_WA_IMU_DATA, 'hb); //
cpu_wr(X313_WA_IMU_DATA, 'h1); //
cpu_wr(X313_WA_IMU_DATA, 'hc); //
cpu_wr(X313_WA_IMU_DATA, 'hf); //
cpu_wr(X313_WA_IMU_DATA, 'h9); //
cpu_wr(X313_WA_IMU_DATA, 'h8); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
cpu_wr(X313_WA_IMU_DATA, 'h0); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h30); // first format
//$GPRMC,042931.0,A,4043.39929,N,11155.92706,W,000.00,283.8,250411,013.2,E*45
//0101010 000 : 'hb 'h2a 'h04 'h0
// cpu_wr(X313_WA_IMU_DATA, 'h0b); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h0a); // testing - made 1 shorter than actual
cpu_wr(X313_WA_IMU_DATA, 'h2a); //
cpu_wr(X313_WA_IMU_DATA, 'h04); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h34); // second format
//$GPGGA,042931.0,4043.39929,N,11155.92706,W,1,09,0.8,1280.5,M,-13.8,M,,*5B
//0010 1000 0101 0 : 'h0e 'h14 'h0a 'h0
cpu_wr(X313_WA_IMU_DATA, 'h0e); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h14); //
cpu_wr(X313_WA_IMU_DATA, 'h0a); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h38); // third format
//$GPGSA,A,3,04,07,08,11,15,17,24,26,27,,,,1.7,0.8,1.5*36
//01000000 00000000 00 : 'h11 'h01 'h00 'h0
cpu_wr(X313_WA_IMU_DATA, 'h11); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'h01); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
/// cpu_wr(X313_WA_IMU_CTRL, 'h3c); // fourth format
//$GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
//00101010 1 : 'h08 'haa 'h00 'h0
cpu_wr(X313_WA_IMU_DATA, 'h08); //number of fields including dummy comma
cpu_wr(X313_WA_IMU_DATA, 'haa); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_DATA, 'h00); //
cpu_wr(X313_WA_IMU_CTRL, 4); // select register number 4
cpu_wr(X313_WA_IMU_DATA, 'h10); // x gyro low
cpu_wr(X313_WA_IMU_DATA, 'h12); // x gyro high
cpu_wr(X313_WA_IMU_DATA, 'h14); //
cpu_wr(X313_WA_IMU_DATA, 'h16); //
cpu_wr(X313_WA_IMU_DATA, 'h18); //
cpu_wr(X313_WA_IMU_DATA, 'h1a); //
cpu_wr(X313_WA_IMU_DATA, 'h1c); // x accel low
cpu_wr(X313_WA_IMU_DATA, 'h1e); //
cpu_wr(X313_WA_IMU_DATA, 'h20); //
cpu_wr(X313_WA_IMU_DATA, 'h22); //
cpu_wr(X313_WA_IMU_DATA, 'h24); //
cpu_wr(X313_WA_IMU_DATA, 'h26); // z accel high
cpu_wr(X313_WA_IMU_DATA, 'h40); // x delta ang low
cpu_wr(X313_WA_IMU_DATA, 'h42); // x delta ang high
cpu_wr(X313_WA_IMU_DATA, 'h44); //
cpu_wr(X313_WA_IMU_DATA, 'h46); //
cpu_wr(X313_WA_IMU_DATA, 'h48); //
cpu_wr(X313_WA_IMU_DATA, 'h4a); //
cpu_wr(X313_WA_IMU_DATA, 'h4c); // x delta vel low
cpu_wr(X313_WA_IMU_DATA, 'h4e); //
cpu_wr(X313_WA_IMU_DATA, 'h50); //
cpu_wr(X313_WA_IMU_DATA, 'h52); //
cpu_wr(X313_WA_IMU_DATA, 'h54); //
cpu_wr(X313_WA_IMU_DATA, 'h56); // z delta vel high
cpu_wr(X313_WA_IMU_DATA, 'h0e); // temperature
cpu_wr(X313_WA_IMU_DATA, 'h70); // time m/s
cpu_wr(X313_WA_IMU_DATA, 'h72); // time d/h
cpu_wr(X313_WA_IMU_DATA, 'h74); // time y/m
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, 0); // reset IMU
cpu_wr(X313_WA_IMU_DATA, 0); // reset bit counter
#1000;
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION); // set bit counter (clock frequency divider)
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_PERIOD); // set period
// set "odometer" message
cpu_wr(X313_WA_IMU_CTRL, 'h40); // select start of message
cpu_wr(X313_WA_IMU_DATA, 'h01234567); // Message first 4 bytes
cpu_wr(X313_WA_IMU_DATA, 'h12345678); //next
cpu_wr(X313_WA_IMU_DATA, 'h23456789); //next
cpu_wr(X313_WA_IMU_DATA, 'h3456789a); //next
cpu_wr(X313_WA_IMU_DATA, 'h456789ab); //next
cpu_wr(X313_WA_IMU_DATA, 'h56789abc); //next
cpu_wr(X313_WA_IMU_DATA, 'h6789abcd); //next
cpu_wr(X313_WA_IMU_DATA, 'h789abcde); //next
cpu_wr(X313_WA_IMU_DATA, 'h89abcdef); //next
cpu_wr(X313_WA_IMU_DATA, 'h9abcdef0); //next
cpu_wr(X313_WA_IMU_DATA, 'habcdef01); //next
cpu_wr(X313_WA_IMU_DATA, 'hbcdef012); //next
cpu_wr(X313_WA_IMU_DATA, 'hcdef0123); //next
cpu_wr(X313_WA_IMU_DATA, 'hdef01234); //next
// extra 8 bytes - will not be logged
cpu_wr(X313_WA_IMU_DATA, 'hef012345); //next
cpu_wr(X313_WA_IMU_DATA, 'hf0123456); //next
// cpu_wr(1,32'h00000); // disable and reset dma
// cpu_wr(1,32'h20000); // enable DMA channel 1
cpu_wr(1,32'h00024); // disable and reset dma (both channels)
cpu_wr(1,32'h00028); // enable DMA channel 1
// cpu_wr(X313_WA_IMU_DATA, 1); // set period
/*
parameter X313_WA_IMU_DATA= 'h7e;
parameter X313_WA_IMU_CTRL= 'h7f;
parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready
*/
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
cpu_rd_ce1(1);
`endif `endif
program_quantization; program_quantization;
...@@ -1341,7 +767,7 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F ...@@ -1341,7 +767,7 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
set_focus_filt(0,100,8,24,127,0,1); set_focus_filt(0,100,8,24,127,0,1);
set_zero_bin (8'hc0,8'h80); // zero_bin 0.75 (half), bias (0.5 - true rounding) set_zero_bin (8'hc0,8'h80); // zero_bin 0.75 (half), bias (0.5 - true rounding)
cpu_wr(X313_WA_CAMSYNCPER, TRIG_PERIOD); /// starts generatoe *******************new cpu_wr(X313_WA_CAMSYNCPER, {8'b0,TRIG_PERIOD}); /// starts generatoe *******************new
...@@ -1450,8 +876,8 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F ...@@ -1450,8 +876,8 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
cpu_rd('h10) ; //status cpu_rd('h10) ; //status
// program rtc // program rtc
cpu_wr('h4a, 16'h8000); // maximal correction to the rtc cpu_wr('h4a, 'h8000); // maximal correction to the rtc
cpu_wr('h48, 20'h00000); // microseconds cpu_wr('h48, 'h00000); // microseconds
cpu_wr('h49,32'h12345678); // seconds cpu_wr('h49,32'h12345678); // seconds
// #1000; // #1000;
// cpu_wr('h45,32'h12345678); // seconds - repeat for simulation // cpu_wr('h45,32'h12345678); // seconds - repeat for simulation
...@@ -1490,9 +916,13 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F ...@@ -1490,9 +916,13 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
cpu_wr('h61,'h43000000 | (HISTOGRAM_HEIGHT-2)); // height cpu_wr('h61,'h43000000 | (HISTOGRAM_HEIGHT-2)); // height
TEST_TITLE = "INIT_DRAM";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
init_sdram; init_sdram;
TEST_TITLE = "INIT_DRAM_DONE";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
`ifdef ENDFRAMES `ifdef ENDFRAMES
cpu_wr(X313_WA_DCR0, X313_WA_DCR0_ENDFRAMESEN); // enable ending frames if insufficient data cpu_wr(X313_WA_DCR0, X313_WA_DCR0_ENDFRAMESEN); // enable ending frames if insufficient data
`else `else
...@@ -1563,6 +993,8 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F ...@@ -1563,6 +993,8 @@ $GPVTG,283.8,T,270.5,M,000.00,N,0000.00,K*7F
// dma_en(0,1); // dma_en(0,1);
dma_en(1,1); dma_en(1,1);
TEST_TITLE = "DMA_EN_1_1";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
//*************** cpu_wr(1,32'h00000); // disable and reset dma *** immediate *** //*************** cpu_wr(1,32'h00000); // disable and reset dma *** immediate ***
// cpu_wr('h60,'h01000000); // cpu_wr('h60,'h01000000);
...@@ -1725,7 +1157,11 @@ $display ("saturation=2"); ...@@ -1725,7 +1157,11 @@ $display ("saturation=2");
cpu_wr('h64,'h31400000); // [BY] => 0x180000 cpu_wr('h64,'h31400000); // [BY] => 0x180000
`ifdef CONTINUOUS_COMPRESSION `ifdef CONTINUOUS_COMPRESSION
TEST_TITLE = "START_CONTINUOUS_COMPRESSION";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
`else `else
TEST_TITLE = "INIT_CHAN_SEQ";
init_chan_seq ('h64,2,1,(PF_HEIGHT>0)?1:0,DEPEND,'h200000,(WOI_WIDTH>>4)-1,(WOI_HEIGHT & 'h3ff0)-'h10); // ch2,mode1,wnr0,depend1,sa000000,nTileX10, nTileY10 init_chan_seq ('h64,2,1,(PF_HEIGHT>0)?1:0,DEPEND,'h200000,(WOI_WIDTH>>4)-1,(WOI_HEIGHT & 'h3ff0)-'h10); // ch2,mode1,wnr0,depend1,sa000000,nTileX10, nTileY10
`ifdef TEST_INSUFFICIENT_DATA `ifdef TEST_INSUFFICIENT_DATA
// Don't set correct number of blocks, leave the number larger // Don't set correct number of blocks, leave the number larger
...@@ -1767,13 +1203,29 @@ task program_compressor; ...@@ -1767,13 +1203,29 @@ task program_compressor;
read_ch3_descript; read_ch3_descript;
read_status; read_status;
`ifdef TEST_CH3_AND_PHASE `ifdef TEST_CH3_AND_PHASE
TEST_TITLE = "write256_ch3-1";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
write256_ch3(16'h1100); write256_ch3(16'h1100);
TEST_TITLE = "write256_ch3-2";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
write256_ch3(16'h2200); write256_ch3(16'h2200);
TEST_TITLE = "write256_ch3-3";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
write256_ch3(16'h3300); write256_ch3(16'h3300);
TEST_TITLE = "write256_ch3-4";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
write256_ch3(16'h4400); write256_ch3(16'h4400);
TEST_TITLE = "write256_ch3-5";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
write256_ch3(16'h5500); write256_ch3(16'h5500);
TEST_TITLE = "write256_ch3-6";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
write256_ch3(16'h6600); write256_ch3(16'h6600);
TEST_TITLE = "write256_ch3-7";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
close_ch3; // wait write buffer empty close_ch3; // wait write buffer empty
TEST_TITLE = "write256_ch3-8";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
read_ch3_descript; read_ch3_descript;
read_status; read_status;
init_chan (3,0,0,0,0,'h20,'hf); // ch3,mode1,wnr1,depend0,sa0,nTileX1f, nTileY2 writes 1 full and 1 small init_chan (3,0,0,0,0,'h20,'hf); // ch3,mode1,wnr1,depend0,sa0,nTileX1f, nTileY2 writes 1 full and 1 small
...@@ -2037,7 +1489,7 @@ parameter CPU_RH_A = 2; ...@@ -2037,7 +1489,7 @@ parameter CPU_RH_A = 2;
end end
endtask endtask
task cpu_rd_ce1_isr; task cpu_rd_ce1_isr; //SuppressThisWarning Veditor UNUSED TASK
input [ 7:0] ia; input [ 7:0] ia;
begin begin
wait (~BUS[BUSOP_ISR_RD1]); wait (~BUS[BUSOP_ISR_RD1]);
...@@ -2094,10 +1546,10 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0?? ...@@ -2094,10 +1546,10 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0??
// enable SDRAM controller and refresh (all channels disabled) // enable SDRAM controller and refresh (all channels disabled)
SDRAM_MODE=6'h00; cpu_wr(SDRAM_ENABLE,SDRAM_MODE); // to init to 0 (for simulation only) SDRAM_MODE = 'h00; cpu_wr(SDRAM_ENABLE,{20'b0,SDRAM_MODE}); // to init to 0 (for simulation only)
#(100); #(100);
// SDRAM_MODE=6'h03; cpu_wr(SDRAM_ENABLE,SDRAM_MODE); // All channels disabled, only refresh and sdram itself // SDRAM_MODE=6'h03; cpu_wr(SDRAM_ENABLE,SDRAM_MODE); // All channels disabled, only refresh and sdram itself
SDRAM_MODE=12'haaf; cpu_wr(SDRAM_ENABLE,SDRAM_MODE); // All channels disabled, only refresh and sdram itself SDRAM_MODE= 'haaf; cpu_wr(SDRAM_ENABLE,{20'b0,SDRAM_MODE}); // All channels disabled, only refresh and sdram itself
end end
endtask endtask
...@@ -2122,11 +1574,11 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0?? ...@@ -2122,11 +1574,11 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0??
w1[15:0]= {2'b0,inTileX[9:0],isa[24:21]}; w1[15:0]= {2'b0,inTileX[9:0],isa[24:21]};
w2[15:0]= {4'b0,inTileY[11:0]}; w2[15:0]= {4'b0,inTileY[11:0]};
$display (" writing %x to %x",w1,CHN_BASEA+4*ichnum+1); $display (" writing %x to %x",w1,CHN_BASEA+4*ichnum+1);
cpu_wr(CHN_BASEA+4*ichnum+1,w1); cpu_wr(CHN_BASEA+4*ichnum+1,{16'b0,w1});
$display (" writing %x to %x",w2,CHN_BASEA+4*ichnum+2); $display (" writing %x to %x",w2,CHN_BASEA+4*ichnum+2);
cpu_wr(CHN_BASEA+4*ichnum+2,w2); cpu_wr(CHN_BASEA+4*ichnum+2,{16'b0,w2});
$display (" writing %x to %x",w0,CHN_BASEA+4*ichnum+0); $display (" writing %x to %x",w0,CHN_BASEA+4*ichnum+0);
cpu_wr(CHN_BASEA+4*ichnum+0,w0); cpu_wr(CHN_BASEA+4*ichnum+0,{16'b0,w0});
// enable channel: // enable channel:
// SDRAM_MODE=SDRAM_MODE | (6'h4 << ichnum); // SDRAM_MODE=SDRAM_MODE | (6'h4 << ichnum);
SDRAM_MODE= (12'h030 << (ichnum <<1)); SDRAM_MODE= (12'h030 << (ichnum <<1));
...@@ -2136,7 +1588,7 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0?? ...@@ -2136,7 +1588,7 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0??
4'h2: SDRAM_MODE= 12'h300; 4'h2: SDRAM_MODE= 12'h300;
4'h3: SDRAM_MODE= 12'hc00; 4'h3: SDRAM_MODE= 12'hc00;
endcase endcase
cpu_wr(SDRAM_ENABLE,SDRAM_MODE); cpu_wr(SDRAM_ENABLE,{20'b0,SDRAM_MODE});
end end
endtask endtask
// init_chan (2,1,0,1,'h200000,'h07,'h10); // ch2,mode1,wnr0,depend1,sa000000,nTileX10, nTileY10 // init_chan (2,1,0,1,'h200000,'h07,'h10); // ch2,mode1,wnr0,depend1,sa000000,nTileX10, nTileY10
...@@ -2218,7 +1670,7 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0?? ...@@ -2218,7 +1670,7 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0??
end end
endtask endtask
/*
task writeGrad_ch3; // write 256 8-bit words (as 64 x 32) , same all lines, with value=first+x task writeGrad_ch3; // write 256 8-bit words (as 64 x 32) , same all lines, with value=first+x
input [7:0] first; input [7:0] first;
integer i; integer i;
...@@ -2253,7 +1705,7 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0?? ...@@ -2253,7 +1705,7 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0??
end end
endtask endtask
*/
// 1-cycle latency! // 1-cycle latency!
task read256_ch3; // read 16 16-bit words (as 8 x 32) task read256_ch3; // read 16 16-bit words (as 8 x 32)
reg [15:0] i; reg [15:0] i;
...@@ -2286,13 +1738,13 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0?? ...@@ -2286,13 +1738,13 @@ parameter CH3_WEMPTY_BITNUM=8; // was 0??
*/ */
task program_huffman; task program_huffman;
// huffman tables data // huffman tables data
reg [23:0] huff_data[0:511]; reg [23:0] huff_data[0:511]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i; integer i;
begin begin
$readmemh("huffman.dat",huff_data); $readmemh("huffman.dat",huff_data);
cpu_wr ('he,'h200); // start address of huffman tables cpu_wr ('he,'h200); // start address of huffman tables
for (i=0;i<512;i=i+1) begin for (i=0;i<512;i=i+1) begin
cpu_wr('hf,huff_data[i]); cpu_wr('hf,{8'b0,huff_data[i]});
end end
end end
endtask endtask
...@@ -2300,7 +1752,7 @@ endtask ...@@ -2300,7 +1752,7 @@ endtask
task program_quantization; task program_quantization;
// quantization tables data // quantization tables data
// reg [11:0] quant_data[0:255]; // reg [11:0] quant_data[0:255];
reg [15:0] quant_data[0:255]; reg [15:0] quant_data[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i; integer i;
begin begin
// $readmemh("quantization.dat",quant_data); // $readmemh("quantization.dat",quant_data);
...@@ -2314,7 +1766,7 @@ endtask ...@@ -2314,7 +1766,7 @@ endtask
task program_coring; task program_coring;
// coring tables data // coring tables data
reg [15:0] coring_data[0:1023]; reg [15:0] coring_data[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i; integer i;
begin begin
// $readmemh("quantization.dat",quant_data); // $readmemh("quantization.dat",quant_data);
...@@ -2330,13 +1782,13 @@ endtask ...@@ -2330,13 +1782,13 @@ endtask
task program_focus_filt; task program_focus_filt;
// focus quality filter data // focus quality filter data
reg [15:0] filt_data[0:127]; reg [15:0] filt_data[0:127]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i; integer i;
begin begin
$readmemh("focus_filt.dat",filt_data); $readmemh("focus_filt.dat",filt_data);
cpu_wr ('he,'h800); // start address of focus filter tables cpu_wr ('he,'h800); // start address of focus filter tables
for (i=0;i<128;i=i+1) begin for (i=0;i<128;i=i+1) begin
cpu_wr('hf,filt_data[i]); cpu_wr('hf,{16'b0,filt_data[i]});
end end
end end
endtask endtask
...@@ -2409,9 +1861,9 @@ endtask ...@@ -2409,9 +1861,9 @@ endtask
task program_curves; task program_curves;
reg [9:0] curves_data[0:1027]; reg [9:0] curves_data[0:1027]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer n,i,base,diff,diff1; integer n,i,base,diff,diff1;
reg [10:0] curv_diff; ///AF: reg [10:0] curv_diff;
begin begin
$readmemh("linear1028rgb.dat",curves_data); $readmemh("linear1028rgb.dat",curves_data);
// $readmemh("zero1028rgb.dat",curves_data); // $readmemh("zero1028rgb.dat",curves_data);
...@@ -2424,18 +1876,18 @@ task program_curves; ...@@ -2424,18 +1876,18 @@ task program_curves;
diff1=curves_data[257*n+i+1]-curves_data[257*n+i]+8; diff1=curves_data[257*n+i+1]-curves_data[257*n+i]+8;
// $display ("%x %x %x %x %x %x",n,i,curves_data[257*n+i], base, diff, diff1); // $display ("%x %x %x %x %x %x",n,i,curves_data[257*n+i], base, diff, diff1);
#1; #1;
if ((diff>63) || (diff < -64)) cpu_wr('hf,{1'b1,diff1[10:4],base[9:0]}); if ((diff>63) || (diff < -64)) cpu_wr('hf,{14'b0,1'b1,diff1[10:4],base[9:0]});
else cpu_wr('hf,{1'b0,diff [ 6:0],base[9:0]}); else cpu_wr('hf,{14'b0,1'b0,diff [ 6:0],base[9:0]});
end end
end end
end end
endtask endtask
/// NOTE: Can not use sequencer to program tables - may collide with software table writes !!! /// NOTE: Can not use sequencer to program tables - may collide with software table writes !!!
task pre_program_curves; // all but last word, last word schedule through sequencer to provided address task pre_program_curves; // all but last word, last word schedule through sequencer to provided address //SuppressThisWarning Veditor UNUSED TASK
input [7:0] seq_addr; input [7:0] seq_addr;
reg [9:0] curves_data[0:1027]; reg [9:0] curves_data[0:1027]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer n,i,base,diff,diff1; integer n,i,base,diff,diff1;
reg [10:0] curv_diff; ///AF: reg [10:0] curv_diff;
reg [23:0] data; reg [23:0] data;
begin begin
$readmemh("linear1028rgb.dat",curves_data); $readmemh("linear1028rgb.dat",curves_data);
...@@ -2449,9 +1901,9 @@ task pre_program_curves; // all but last word, last word schedule through sequen ...@@ -2449,9 +1901,9 @@ task pre_program_curves; // all but last word, last word schedule through sequen
diff1=curves_data[257*n+i+1]-curves_data[257*n+i]+8; diff1=curves_data[257*n+i+1]-curves_data[257*n+i]+8;
// $display ("%x %x %x %x %x %x",n,i,curves_data[257*n+i], base, diff, diff1); // $display ("%x %x %x %x %x %x",n,i,curves_data[257*n+i], base, diff, diff1);
#1; #1;
if ((diff>63) || (diff < -64)) data={1'b1,diff1[10:4],base[9:0]}; if ((diff>63) || (diff < -64)) data={6'b0,1'b1,diff1[10:4],base[9:0]};
else data={1'b0,diff [ 6:0],base[9:0]}; else data={6'b0,1'b0,diff [ 6:0],base[9:0]};
if ((n<3) || (i<255)) cpu_wr('hf, data); if ((n<3) || (i<255)) cpu_wr('hf, {8'b0,data});
else begin else begin
cpu_wr(seq_addr,'h0e0007ff); cpu_wr(seq_addr,'h0e0007ff);
cpu_wr(seq_addr,{8'h0f,data[23:0]}); cpu_wr(seq_addr,{8'h0f,data[23:0]});
...@@ -2486,52 +1938,9 @@ task program_compressor; ...@@ -2486,52 +1938,9 @@ task program_compressor;
1'b1,cmd[1:0]}); 1'b1,cmd[1:0]});
end end
endtask endtask
`ifdef TEST_IMU
task send_serial_bit; `include "imu_sim_tasks_include.vh"
input [7:0] data_byte; `endif
reg [7:0] d;
begin
d <= data_byte;
wait (CLK0); wait (~CLK0);
// SERIAL_BIT should be 1 here
// Send start bit
SERIAL_BIT <= 1'b0;
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
// Send 8 data bits, LSB first
repeat (8) begin
SERIAL_BIT <= d[0];
#1 d[7:0] <= {1'b0,d[7:1]};
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end
// Send stop bit
SERIAL_BIT <= 1'b1;
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end
endtask
task send_serial_pause;
begin
wait (CLK0); wait (~CLK0);
SERIAL_BIT <= 1'b1;
repeat (16) begin
repeat (IMU_GPS_BIT_PERIOD) begin wait (CLK0); wait (~CLK0); end
end
end
endtask
// SERIAL_DATA_FD=$fopen("gps_data.dat","r");
task send_serial_line;
integer char;
begin
char=0;
while (!$feof (SERIAL_DATA_FD) && (char != 'h0a)) begin
char=$fgetc(SERIAL_DATA_FD);
send_serial_bit(char);
end
end
endtask
endmodule endmodule
...@@ -2541,7 +1950,7 @@ module oneshot(trigger, ...@@ -2541,7 +1950,7 @@ module oneshot(trigger,
input trigger; input trigger;
output out; output out;
reg out; reg out;
event start; event start; //SuppressThisWarning Veditor "event" is not supported in VDT?
parameter duration=4000; parameter duration=4000;
initial out= 0; initial out= 0;
always @ (posedge trigger) begin always @ (posedge trigger) begin
......
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