Commit d6e9be6b authored by Andrey Filippov's avatar Andrey Filippov
Browse files

fixing VDT warnings, splitting testbench file, adding modified primitive SLR version for simulation

parent 5d6f430e

.project

+33 −3
Original line number Original line Diff line number Diff line
@@ -9,20 +9,50 @@ 
	<natures>

	<natures>

	</natures>

	</natures>

	<linkedResources>

	<linkedResources>

		<link>

			<name>ise_logs/ISEMap.log</name>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_logs/ISEMap-20150726165658761.log</location>

		</link>

		<link>

			<name>ise_logs/ISENGDBuild.log</name>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150726165546847.log</location>

		</link>

		<link>

			<name>ise_logs/ISEPAR.log</name>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150726165911986.log</location>

		</link>

		<link>

		<link>

			<name>ise_logs/ISEPartgen.log</name>

			<name>ise_logs/ISEPartgen.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log</location>

			<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150726172041010.log</location>

		</link>

		<link>

			<name>ise_logs/ISETraceMap.log</name>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150726213039147.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>ise_logs/ISExst.log</name>

			<name>ise_logs/ISExst.log</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_logs/ISExst-20150726141146079.log</location>

			<location>/home/andrey/git/x353/ise_logs/ISExst-20150726165049304.log</location>

		</link>

		<link>

			<name>ise_state/x353-map.tgz</name>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_state/x353-map-20150726165658761.tgz</location>

		</link>

		<link>

			<name>ise_state/x353-ngdbuild.tgz</name>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150726165546847.tgz</location>

		</link>

		</link>

		<link>

		<link>

			<name>ise_state/x353-synth.tgz</name>

			<name>ise_state/x353-synth.tgz</name>

			<type>1</type>

			<type>1</type>

			<location>/home/andrey/git/x353/ise_state/x353-synth-20150726135708468.tgz</location>

			<location>/home/andrey/git/x353/ise_state/x353-synth-20150726165049304.tgz</location>

		</link>

		</link>

	</linkedResources>

	</linkedResources>

</projectDescription>
 
</projectDescription>

README.md

+1 −1
Original line number Original line Diff line number Diff line
@@ -18,7 +18,7 @@ Here is what makes it difficult: 
2. Last verion of the ISE (it is ISE 14.7) can not use the older code "as is"

2. Last verion of the ISE (it is ISE 14.7) can not use the older code "as is"

3. We were able to modify the Verilog code to be parsed by the current XST, but it does not

3. We were able to modify the Verilog code to be parsed by the current XST, but it does not

recognize some statements in the *.xcf constraints file (I had to rename original *.ucf to *.xcf).

recognize some statements in the *.xcf constraints file (I had to rename original *.ucf to *.xcf).

4. Attempt to try old parser (Suggested by XST itself as the new parser is not the default for

4. Attempt to try old parser (suggested by XST itself as the new parser is not the default for

the Spartan 3e): 

the Spartan 3e): 

```

```

WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default

WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default

compressor/color_proc353.v

+3 −3
Original line number Original line Diff line number Diff line
@@ -198,7 +198,7 @@ input hdr; // second green absolute, not difference 
   reg            four_blocks_r;

   reg            four_blocks_r;

   reg            scale_diff_r;

   reg            scale_diff_r;

   reg            hdr_r;

   reg            hdr_r;

   reg    [1:0]   tile_margin_r;

   reg    [1:0]   tile_margin_r; // SuppressThisWarning Veditor UNUSED

//   reg    [2:0]   tile_shift_r;

//   reg    [2:0]   tile_shift_r;

   reg    [1:0]   bayer_phase_r;

   reg    [1:0]   bayer_phase_r;

   reg    [3:0]   bayer_phase_onehot;

   reg    [3:0]   bayer_phase_onehot;
@@ -259,7 +259,7 @@ input hdr; // second green absolute, not difference 
     last_from_sdram <= en & preline_was_0 && (prepix[4:0]==0);

     last_from_sdram <= en & preline_was_0 && (prepix[4:0]==0);

     inc_sdrama <= en & (pre_first_pixel || (inc_sdrama && !last_from_sdram ));

     inc_sdrama <= en & (pre_first_pixel || (inc_sdrama && !last_from_sdram ));

     if      (pre_first_pixel)    sdram_a9[8:0] <= sdrama_top_left[8:0];

     if      (pre_first_pixel)    sdram_a9[8:0] <= sdrama_top_left[8:0];

     else if (inc_sdrama)         sdram_a9[8:0] <= sdram_a9[8:0] + (pre_start_of_line ? sdrama_line_inc[2:0] : 1);

     else if (inc_sdrama)         sdram_a9[8:0] <= sdram_a9[8:0] + (pre_start_of_line ? sdrama_line_inc[2:0] : 3'b1);





     if      (!en || memWasInit)             sdram_a9_page[1:0] <= 2'h0;

     if      (!en || memWasInit)             sdram_a9_page[1:0] <= 2'h0;

     else if (last_from_sdram && inc_sdrama) sdram_a9_page[1:0] <= sdram_a9_page[1:0]+1;

     else if (last_from_sdram && inc_sdrama) sdram_a9_page[1:0] <= sdram_a9_page[1:0]+1;
@@ -445,7 +445,7 @@ input hdr; // second green absolute, not difference 




     if (first_pixel) begin

     if (first_pixel) begin

	    first0 <= willbe_first;

	    first0 <= willbe_first;

		 last0  <= (bcntr[17:0]==17'b0);

		 last0  <= (bcntr[17:0] == 18'b0);

	  end

	  end

     if (ccv_out_start) begin

     if (ccv_out_start) begin

	    first <= first0;

	    first <= first0;

compressor/compressor333.v

+19 −18
Original line number Original line Diff line number Diff line
@@ -220,8 +220,8 @@ module compressor(// cwr, // CPU write - global clock 
//

//

// control registetr bits

// control registetr bits

   wire            cr_w;                // data written to cr (1 cycle) - now just to reset legacy IRQ

   wire            cr_w;                // data written to cr (1 cycle) - now just to reset legacy IRQ

   wire            raw_dv;                     // input pixel data valid (pxd[7:0]may be sent to DMA buffer through multiplexor)

   wire            raw_dv;              // input pixel data valid (pxd[7:0]may be sent to DMA buffer through multiplexor) // SuppressThisWarning Veditor UNUSED

   wire            color_dv; // unused                  // color data valid       (color_d[7:0] may be sent to DMA buffer through multiplexor)

   wire            color_dv; // unused  // color data valid       (color_d[7:0] may be sent to DMA buffer through multiplexor)// SuppressThisWarning Veditor UNUSED

   wire   [ 9:0]   color_d;             // data out stream from color space converter (6X64 blocks for each MCU - 4Y, Cb,Cr)

   wire   [ 9:0]   color_d;             // data out stream from color space converter (6X64 blocks for each MCU - 4Y, Cb,Cr)

   wire   [ 2:0]   color_tn;            // tile number in an MCU from color space converter (valid @ color_dv)

   wire   [ 2:0]   color_tn;            // tile number in an MCU from color space converter (valid @ color_dv)

   wire   [ 8:0]   color_avr;           // [8:0]   DC (average value) 9 bit signed for Y: 9'h000..9'h0ff, for C - 9h100..9'h000..9'h0ff

   wire   [ 8:0]   color_avr;           // [8:0]   DC (average value) 9 bit signed for Y: 9'h000..9'h0ff, for C - 9h100..9'h000..9'h0ff
@@ -230,7 +230,7 @@ module compressor(// cwr, // CPU write - global clock 




//   wire         dct_en;

//   wire         dct_en;

   wire          dct_start;

   wire          dct_start;

   wire         dct_dv;

   wire          dct_dv; // SuppressThisWarning Veditor UNUSED

   wire [12:0]   dct_out;

   wire [12:0]   dct_out;

   wire          dct_last_in;   // output high during input of the last of 64 pixels in a 8x8 block

   wire          dct_last_in;   // output high during input of the last of 64 pixels in a 8x8 block

   wire          dct_pre_first_out; // 1 cycle ahead of the first output in a 64 block

   wire          dct_pre_first_out; // 1 cycle ahead of the first output in a 64 block
@@ -245,7 +245,7 @@ module compressor(// cwr, // CPU write - global clock 
   wire         focus_ds;

   wire         focus_ds;

 

 

// wire   enc_first;

// wire   enc_first;

 wire enc_last;

 wire          enc_last; // SuppressThisWarning Veditor UNUSED

 wire   [15:0] enc_do;

 wire   [15:0] enc_do;

 wire          enc_dv;

 wire          enc_dv;
@@ -665,7 +665,7 @@ FD i_is_compressing (.Q(is_compressing),.C(clk), .D(cmprs_en && (go_single || (i 
                        

                        

`ifdef debug_compressor

`ifdef debug_compressor

    wire        debug_bcntrIsZero;

    wire        debug_bcntrIsZero;

wire [17:0] debug_bcntr;

    wire [17:0] debug_bcntr; //SuppressThisWarning Veditor UNUSED

`endif

`endif

 color_proc i_color_proc(.clk(clk),            // pixel clock 37.5MHz

 color_proc i_color_proc(.clk(clk),            // pixel clock 37.5MHz

                         .en(cmprs_en),      // Enable (0 will reset states)

                         .en(cmprs_en),      // Enable (0 will reset states)
@@ -1080,7 +1080,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk) 












   reg  [23:0]   cr;

///AF:     reg  [23:0]   cr;

   reg  [17:0]   ntiles;

   reg  [17:0]   ntiles;

   reg  [15:0] ntiles0;

   reg  [15:0] ntiles0;

   reg  [17:0] ntiles1;

   reg  [17:0] ntiles1;
@@ -1095,7 +1095,8 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk) 








   assign      rcs[1:0]={cwe && rs, cwe && ~rs};

   assign      rcs[1:0]={cwe && rs, cwe && ~rs};

   reg         rcs0_d, rcs0_dd, rcs1_d;

   reg         rcs0_d, rcs0_dd;

///AF:     reg         rcs1_d;

   reg [2:0]   rcs1d;

   reg [2:0]   rcs1d;





   reg    [1:0]   is_compressing_sclk; // sync to negedge sclk

   reg    [1:0]   is_compressing_sclk; // sync to negedge sclk
@@ -1168,7 +1169,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk) 
//   always @ (posedge clk) cr[23:0] <=cri[23:0];   // make it sync

//   always @ (posedge clk) cr[23:0] <=cri[23:0];   // make it sync

   always @ (negedge sclk) if (rcs[1]) ntiles0[15:0] <= di[15:0];

   always @ (negedge sclk) if (rcs[1]) ntiles0[15:0] <= di[15:0];

//   always @ (negedge sclk) if (rcs1_d) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]};

//   always @ (negedge sclk) if (rcs1_d) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]};

   always @ (negedge sclk) if (rcs1d[0]) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]};

   always @ (negedge sclk) if (rcs1d[0]) ntiles1[17:0] <= {di[ 1:0],ntiles0[15:0]};

   always @ (negedge sclk) if (rcs1d[2]) ntiles1_prev[17:0] <= ntiles1[17:0];

   always @ (negedge sclk) if (rcs1d[2]) ntiles1_prev[17:0] <= ntiles1[17:0];





//     rcs1d[2:0]<={rcs1d[1:0],rcs[1]};

//     rcs1d[2:0]<={rcs1d[1:0],rcs[1]};

compressor/csconvert_mono.v

+4 −1
Original line number Original line Diff line number Diff line
@@ -129,7 +129,10 @@ module csconvert_jp4diff (en, 
    reg          dly_1;

    reg          dly_1;

    reg   [14:0] dly_16;

    reg   [14:0] dly_16;

    reg          dly_17;

    reg          dly_17;

    wire         start_out=bayer_phase[1]?(bayer_phase[0]?dly_17:dly_16):(bayer_phase[0]?dly_1:pre_first_in);

//    wire         start_out=bayer_phase[1]?(bayer_phase[0]?dly_17:dly_16):(bayer_phase[0]?dly_1:pre_first_in);

///AF2015 - What was supposed to be here for "dly_16" (15 bits, expected 1) - any non-zero or [14]? 

//    wire         start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: (|dly_16)):(bayer_phase[0]?dly_1:pre_first_in);

    wire         start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: dly_16[14]):(bayer_phase[0]?dly_1:pre_first_in);

    reg    [7:0] iadr;

    reg    [7:0] iadr;

    reg          iadr_run;

    reg          iadr_run;

    reg    [1:0] mux_plus_sel;

    reg    [1:0] mux_plus_sel;