Commit 59d8b5dc authored by Andrey Filippov's avatar Andrey Filippov

changing physical constraints to parameters to pass implementation

parent aafa6d1d
......@@ -9,20 +9,25 @@
<natures>
</natures>
<linkedResources>
<link>
<name>ise_logs/ISEBitgen.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEBitgen-20150727142725079.log</location>
</link>
<link>
<name>ise_logs/ISEMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEMap-20150726165658761.log</location>
<location>/home/andrey/git/x353/ise_logs/ISEMap-20150727164109616.log</location>
</link>
<link>
<name>ise_logs/ISENGDBuild.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150726165546847.log</location>
<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150727164109616.log</location>
</link>
<link>
<name>ise_logs/ISEPAR.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150726165911986.log</location>
<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150727142725079.log</location>
</link>
<link>
<name>ise_logs/ISEPartgen.log</name>
......@@ -32,27 +37,37 @@
<link>
<name>ise_logs/ISETraceMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150726213039147.log</location>
<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150727164109616.log</location>
</link>
<link>
<name>ise_logs/ISETracePAR.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETracePAR-20150727142725079.log</location>
</link>
<link>
<name>ise_logs/ISExst.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150726165049304.log</location>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150727170341943.log</location>
</link>
<link>
<name>ise_state/x353-map.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-map-20150726165658761.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-map-20150727164109616.tgz</location>
</link>
<link>
<name>ise_state/x353-ngdbuild.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150726165546847.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150727164109616.tgz</location>
</link>
<link>
<name>ise_state/x353-par.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-par-20150727142725079.tgz</location>
</link>
<link>
<name>ise_state/x353-synth.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150726165049304.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150727170341943.tgz</location>
</link>
</linkedResources>
</projectDescription>
......@@ -26,7 +26,10 @@
**
*/
// Some placement constraints are in this file
module dcm333(
module dcm333#(
parameter IOSTANDARD_SDRAM_DIFF = "DIFF_SSTL2_I",
parameter SLEW_SDRAM_DIFF = "SLOW"
)(
sclk, // input global clock, 120MHz, phase=0
SDCLK, // positive clock to SDRAM
SDNCLK, // negative clock to SDRAM
......@@ -99,7 +102,10 @@ DCM #(
.PSDONE (dcm_done_dcm));
// BUFG i_gsdclk (.I(isdclk90), .O(gsdclk));
OBUFDS i_SDCLK (.O(SDCLK),.OB(SDNCLK),.I(isdclk));
OBUFDS #(
.IOSTANDARD(IOSTANDARD_SDRAM_DIFF),
.SLEW(SLEW_SDRAM_DIFF))
i_SDCLK (.O(SDCLK),.OB(SDNCLK),.I(isdclk));
// OBUFDS i_SDCLK (.O(SDNCLK),.OB(SDCLK),.I(!isdclk));
// make dcm_done behave as dcm_ready
always @ (posedge dcm_clk or posedge dcm_rst)
......
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