Skip to content

X
x353
Commit 59d8b5dc authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

changing physical constraints to parameters to pass implementation

parent aafa6d1d
Hide whitespace changes
Inline Side-by-side
Showing with 481 additions and 372 deletions
.project
View file @ 59d8b5dc
......@@ -9,20 +9,25 @@
<natures>
</natures>
<linkedResources>
<link>
<name>ise_logs/ISEBitgen.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEBitgen-20150727142725079.log</location>
</link>
<link>
<name>ise_logs/ISEMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEMap-20150726165658761.log</location>
<location>/home/andrey/git/x353/ise_logs/ISEMap-20150727164109616.log</location>
</link>
<link>
<name>ise_logs/ISENGDBuild.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150726165546847.log</location>
<location>/home/andrey/git/x353/ise_logs/ISENGDBuild-20150727164109616.log</location>
</link>
<link>
<name>ise_logs/ISEPAR.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150726165911986.log</location>
<location>/home/andrey/git/x353/ise_logs/ISEPAR-20150727142725079.log</location>
</link>
<link>
<name>ise_logs/ISEPartgen.log</name>
......@@ -32,27 +37,37 @@
<link>
<name>ise_logs/ISETraceMap.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150726213039147.log</location>
<location>/home/andrey/git/x353/ise_logs/ISETraceMap-20150727164109616.log</location>
</link>
<link>
<name>ise_logs/ISETracePAR.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISETracePAR-20150727142725079.log</location>
</link>
<link>
<name>ise_logs/ISExst.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150726165049304.log</location>
<location>/home/andrey/git/x353/ise_logs/ISExst-20150727170341943.log</location>
</link>
<link>
<name>ise_state/x353-map.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-map-20150726165658761.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-map-20150727164109616.tgz</location>
</link>
<link>
<name>ise_state/x353-ngdbuild.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150726165546847.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-ngdbuild-20150727164109616.tgz</location>
</link>
<link>
<name>ise_state/x353-par.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-par-20150727142725079.tgz</location>
</link>
<link>
<name>ise_state/x353-synth.tgz</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150726165049304.tgz</location>
<location>/home/andrey/git/x353/ise_state/x353-synth-20150727170341943.tgz</location>
</link>
</linkedResources>
</projectDescription>
control/clkios353.v
View file @ 59d8b5dc
......@@ -26,7 +26,10 @@
**
*/
// Some placement constraints are in this file
module dcm333(
module dcm333#(
parameter IOSTANDARD_SDRAM_DIFF = "DIFF_SSTL2_I",
parameter SLEW_SDRAM_DIFF = "SLOW"
)(
sclk, // input global clock, 120MHz, phase=0
SDCLK, // positive clock to SDRAM
SDNCLK, // negative clock to SDRAM
......@@ -99,7 +102,10 @@ DCM #(
.PSDONE (dcm_done_dcm));
// BUFG i_gsdclk (.I(isdclk90), .O(gsdclk));
OBUFDS i_SDCLK (.O(SDCLK),.OB(SDNCLK),.I(isdclk));
OBUFDS #(
.IOSTANDARD(IOSTANDARD_SDRAM_DIFF),
.SLEW(SLEW_SDRAM_DIFF))
i_SDCLK (.O(SDCLK),.OB(SDNCLK),.I(isdclk));
// OBUFDS i_SDCLK (.O(SDNCLK),.OB(SDCLK),.I(!isdclk));
// make dcm_done behave as dcm_ready
always @ (posedge dcm_clk or posedge dcm_rst)
......
control/ioports353.v
View file @ 59d8b5dc
......@@ -452,45 +452,34 @@ module dpads32(c,t,d,q,dq);
endmodule
module sddrio16(c0,/*c90,*/c270,d,t,q,dq); //added an extra FF for the t signal
input c0,/*c90,*/c270;
module sddrio16 #(
parameter IOSTANDARD = "SSTL2_I",
parameter DRIVE = 12,
parameter SLEW = "SLOW"
)(c0,c270,d,t,q,dq); //added an extra FF for the t signal
input c0,c270;
input [31:0] d;
input t;
output [31:0] q;
inout [15:0] dq;
wire [31:0] q;
sddrio0 i_dq0 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[16],d[ 0]}),.t(t),.q({q[16],q[ 0]}),.dq(dq[ 0]));
sddrio0 i_dq1 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[17],d[ 1]}),.t(t),.q({q[17],q[ 1]}),.dq(dq[ 1]));
sddrio0 i_dq2 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[18],d[ 2]}),.t(t),.q({q[18],q[ 2]}),.dq(dq[ 2]));
sddrio0 i_dq3 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[19],d[ 3]}),.t(t),.q({q[19],q[ 3]}),.dq(dq[ 3]));
sddrio0 i_dq4 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[20],d[ 4]}),.t(t),.q({q[20],q[ 4]}),.dq(dq[ 4]));
sddrio0 i_dq5 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[21],d[ 5]}),.t(t),.q({q[21],q[ 5]}),.dq(dq[ 5]));
sddrio0 i_dq6 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[22],d[ 6]}),.t(t),.q({q[22],q[ 6]}),.dq(dq[ 6]));
sddrio0 i_dq7 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[23],d[ 7]}),.t(t),.q({q[23],q[ 7]}),.dq(dq[ 7]));
sddrio0 i_dq8 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[24],d[ 8]}),.t(t),.q({q[24],q[ 8]}),.dq(dq[ 8]));
sddrio0 i_dq9 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[25],d[ 9]}),.t(t),.q({q[25],q[ 9]}),.dq(dq[ 9]));
sddrio0 i_dq10 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[26],d[10]}),.t(t),.q({q[26],q[10]}),.dq(dq[10]));
sddrio0 i_dq11 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[27],d[11]}),.t(t),.q({q[27],q[11]}),.dq(dq[11]));
sddrio0 i_dq12 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[28],d[12]}),.t(t),.q({q[28],q[12]}),.dq(dq[12]));
sddrio0 i_dq13 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[29],d[13]}),.t(t),.q({q[29],q[13]}),.dq(dq[13]));
sddrio0 i_dq14 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[30],d[14]}),.t(t),.q({q[30],q[14]}),.dq(dq[14]));
sddrio0 i_dq15 (.c0(c0),/*.c90(c90),*/.c270(c270),.d({d[31],d[15]}),.t(t),.q({q[31],q[15]}),.dq(dq[15]));
// s---ynthesis attribute KEEP_HIERARCHY of i_dq0 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq1 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq2 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq3 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq4 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq5 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq6 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq7 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq8 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq9 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq10 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq11 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq12 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq13 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq14 is "TRUE"
// s---ynthesis attribute KEEP_HIERARCHY of i_dq15 is "TRUE"
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq0 (.c0(c0),.c270(c270),.d({d[16],d[ 0]}),.t(t),.q({q[16],q[ 0]}),.dq(dq[ 0]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq1 (.c0(c0),.c270(c270),.d({d[17],d[ 1]}),.t(t),.q({q[17],q[ 1]}),.dq(dq[ 1]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq2 (.c0(c0),.c270(c270),.d({d[18],d[ 2]}),.t(t),.q({q[18],q[ 2]}),.dq(dq[ 2]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq3 (.c0(c0),.c270(c270),.d({d[19],d[ 3]}),.t(t),.q({q[19],q[ 3]}),.dq(dq[ 3]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq4 (.c0(c0),.c270(c270),.d({d[20],d[ 4]}),.t(t),.q({q[20],q[ 4]}),.dq(dq[ 4]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq5 (.c0(c0),.c270(c270),.d({d[21],d[ 5]}),.t(t),.q({q[21],q[ 5]}),.dq(dq[ 5]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq6 (.c0(c0),.c270(c270),.d({d[22],d[ 6]}),.t(t),.q({q[22],q[ 6]}),.dq(dq[ 6]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq7 (.c0(c0),.c270(c270),.d({d[23],d[ 7]}),.t(t),.q({q[23],q[ 7]}),.dq(dq[ 7]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq8 (.c0(c0),.c270(c270),.d({d[24],d[ 8]}),.t(t),.q({q[24],q[ 8]}),.dq(dq[ 8]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq9 (.c0(c0),.c270(c270),.d({d[25],d[ 9]}),.t(t),.q({q[25],q[ 9]}),.dq(dq[ 9]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq10 (.c0(c0),.c270(c270),.d({d[26],d[10]}),.t(t),.q({q[26],q[10]}),.dq(dq[10]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq11 (.c0(c0),.c270(c270),.d({d[27],d[11]}),.t(t),.q({q[27],q[11]}),.dq(dq[11]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq12 (.c0(c0),.c270(c270),.d({d[28],d[12]}),.t(t),.q({q[28],q[12]}),.dq(dq[12]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq13 (.c0(c0),.c270(c270),.d({d[29],d[13]}),.t(t),.q({q[29],q[13]}),.dq(dq[13]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq14 (.c0(c0),.c270(c270),.d({d[30],d[14]}),.t(t),.q({q[30],q[14]}),.dq(dq[14]));
sddrio0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq15 (.c0(c0),.c270(c270),.d({d[31],d[15]}),.t(t),.q({q[31],q[15]}),.dq(dq[15]));
endmodule
// Made for CL=2.5
// all data to write is expected to be sync to posedge of c0 - phase=0,
......@@ -499,7 +488,11 @@ endmodule
// tristate will be clocked at rising edge of c270
// All data read will be also sync to rising edge of c0 (LSB will be delayed internally)
module sddrio0(c0,/*c90,*/c270,d,t,q,dq); // made for CL=2.5, LSB first - c0 falling edge is before rising, gets LSB
module sddrio0 #(
parameter IOSTANDARD = "SSTL2_I",
parameter DRIVE = 12,
parameter SLEW = "SLOW"
)(c0,/*c90,*/c270,d,t,q,dq); // made for CL=2.5, LSB first - c0 falling edge is before rising, gets LSB
input c0,/*c90,*/c270;
input [1:0] d;
input t;
......@@ -514,7 +507,7 @@ module sddrio0(c0,/*c90,*/c270,d,t,q,dq); // made for CL=2.5, LSB first - c0 fal
FD i_d1d (.C(c270),.D(d0[1]),.Q(d1d)); //regular FF, not IOB
FD_1 i_q0 (.C(c0),.D(q00),.Q(q[0])); //regular FF, not IOB
IOBUF i_dq (.I(dr), .T(tr),.O(qp), .IO(dq));
IOBUF #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq (.I(dr), .T(tr),.O(qp), .IO(dq));
FDDRCPE i_dr (.Q(dr),.C0(c270),.C1(!c270),.D0(d0[0]),.D1(d1d),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));
FD_1 #(.INIT(1'b1)) i_t0 (.C(c0), .D(t), .Q(t0));
FD #(.INIT(1'b1)) i_t1 (.C(c0), .D(t0), .Q(t1));
......@@ -527,7 +520,11 @@ module sddrio0(c0,/*c90,*/c270,d,t,q,dq); // made for CL=2.5, LSB first - c0 fal
endmodule
module dqs2 (c0,/*c90,*/c270,
module dqs2 #(
parameter IOSTANDARD = "SSTL2_I",
parameter DRIVE = 12,
parameter SLEW = "SLOW"
)(c0,/*c90,*/c270,
t, // 1.5 cycles before cmd "write" sent out to the SDRAM, sync to sclk180
UDQS, // UDQS I/O pin
LDQS, // LDQS I/O pin
......@@ -545,12 +542,21 @@ module dqs2 (c0,/*c90,*/c270,
FD #(.INIT(1'b1)) i_t1 (.C(c0),.D(t0),.Q(t1));
///AF: FD #(.INIT(1'b1)) i_t2 (.C(c270),.D(t0),.Q(t2));
assign tr= t1;
dqs2_0 i_dqsu(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({udqsr270,udqsr90}),.dq(UDQS));
dqs2_0 i_dqsl(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({ldqsr270,ldqsr90}),.dq(LDQS));
dqs2_0 #(.IOSTANDARD(IOSTANDARD),
.DRIVE(DRIVE),
.SLEW(SLEW))
i_dqsu(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({udqsr270,udqsr90}),.dq(UDQS));
dqs2_0 #(.IOSTANDARD(IOSTANDARD),
.DRIVE(DRIVE),
.SLEW(SLEW))
i_dqsl(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({ldqsr270,ldqsr90}),.dq(LDQS));
endmodule
module dqs2_0(c0,/*c90,*/c270,t,q,dq);
module dqs2_0#(
parameter IOSTANDARD = "SSTL2_I",
parameter DRIVE = 12,
parameter SLEW = "SLOW"
) (c0,/*c90,*/c270,t,q,dq);
input c0,/*c90,*/c270;
input t;
output [1:0] q;
......@@ -559,7 +565,7 @@ module dqs2_0(c0,/*c90,*/c270,t,q,dq);
wire qp;
wire virtc0; // sync to c0
IOBUF i_dq (.I(virtc0), .T(t),.O(qp), .IO(dq));
IOBUF #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq (.I(virtc0), .T(t),.O(qp), .IO(dq));
// reset DQS when tristated
FDDRCPE i_dr (.Q(virtc0),.C0(c0),.C1(!c0),.D0(1'b1),.D1(1'b0),.CE(1'b1),.CLR(t),.PRE(1'b0));
......@@ -579,22 +585,30 @@ module dqs2_0(c0,/*c90,*/c270,t,q,dq);
endmodule
//both bits are strobed at rising c270
module sddrdm(c0,/*c90,*/c270,d,dq);
input c0,/*c90,*/c270;
module sddrdm #(
parameter IOSTANDARD = "SSTL2_I",
parameter DRIVE = 12,
parameter SLEW = "SLOW"
) (c0,c270,d,dq);
input c0,c270;
input [1:0] d;
inout dq; //SuppressThisWarning Veditor UNUSED
sddrdm0 i_dq (.c0(c0),/*.c90(c90),*/.c270(c270),.d(d),.dq(dq));
// s--ynthesis attribute KEEP_HIERARCHY of i_dq is "TRUE"
sddrdm0 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq (.c0(c0),.c270(c270),.d(d),.dq(dq));
endmodule
module sddrdm0(c0,/*c90,*/c270,d,dq);
input c0,/*c90,*/c270;
module sddrdm0 #(
parameter IOSTANDARD = "SSTL2_I",
parameter DRIVE = 12,
parameter SLEW = "SLOW"
) (c0,c270,d,dq);
input c0,c270;
input [1:0] d;
output dq;
wire dr,d1d;
wire [1:0] d0;
OBUF i_dq (.I(dr), .O(dq));
OBUF #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_dq (.I(dr), .O(dq));
// FDDRCPE i_dr (.Q(dr),.C0(c270),.C1(c90),.D0(d0[0]),.D1(d1d),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));
FDDRCPE i_dr (.Q(dr),.C0(c270),.C1(!c270),.D0(d0[0]),.D1(d1d),.CE(1'b1),.CLR(1'b0),.PRE(1'b0));
FD i_d00(.C(c0),.D(d[0]),.Q(d0[0])); //regular FF, not IOB
......@@ -608,41 +622,68 @@ endmodule
// SDRAM address and ras/cas/we
module sdo15_2(c,d,q); // inputs at rising edge, resyncs to falling edge, all go high at reset
module sdo15_2#(
parameter IOSTANDARD = "SSTL2_I",
parameter DRIVE = 12,
parameter SLEW = "SLOW"
)(c,d,q); // inputs at rising edge, resyncs to falling edge, all go high at reset
input c;
input [14:0] d;
output [14:0] q;
sdo1_2 i_q0 (.c(c),.d(d[ 0]),.q(q[ 0]));
sdo1_2 i_q1 (.c(c),.d(d[ 1]),.q(q[ 1]));
sdo1_2 i_q2 (.c(c),.d(d[ 2]),.q(q[ 2]));
sdo1_2 i_q3 (.c(c),.d(d[ 3]),.q(q[ 3]));
sdo1_2 i_q4 (.c(c),.d(d[ 4]),.q(q[ 4]));
sdo1_2 i_q5 (.c(c),.d(d[ 5]),.q(q[ 5]));
sdo1_2 i_q6 (.c(c),.d(d[ 6]),.q(q[ 6]));
sdo1_2 i_q7 (.c(c),.d(d[ 7]),.q(q[ 7]));
sdo1_2 i_q8 (.c(c),.d(d[ 8]),.q(q[ 8]));
sdo1_2 i_q9 (.c(c),.d(d[ 9]),.q(q[ 9]));
sdo1_2 i_q10 (.c(c),.d(d[10]),.q(q[10]));
sdo1_2 i_q11 (.c(c),.d(d[11]),.q(q[11]));
sdo1_2 i_q12 (.c(c),.d(d[12]),.q(q[12]));
sdo1_2 i_q13 (.c(c),.d(d[13]),.q(q[13]));
sdo1_2 i_q14 (.c(c),.d(d[14]),.q(q[14]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q0 (.c(c),.d(d[ 0]),.q(q[ 0]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q1 (.c(c),.d(d[ 1]),.q(q[ 1]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q2 (.c(c),.d(d[ 2]),.q(q[ 2]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q3 (.c(c),.d(d[ 3]),.q(q[ 3]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q4 (.c(c),.d(d[ 4]),.q(q[ 4]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q5 (.c(c),.d(d[ 5]),.q(q[ 5]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q6 (.c(c),.d(d[ 6]),.q(q[ 6]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q7 (.c(c),.d(d[ 7]),.q(q[ 7]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q8 (.c(c),.d(d[ 8]),.q(q[ 8]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q9 (.c(c),.d(d[ 9]),.q(q[ 9]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q10 (.c(c),.d(d[10]),.q(q[10]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q11 (.c(c),.d(d[11]),.q(q[11]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q12 (.c(c),.d(d[12]),.q(q[12]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q13 (.c(c),.d(d[13]),.q(q[13]));
sdo1_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW))
i_q14 (.c(c),.d(d[14]),.q(q[14]));
endmodule
module sdo1_2(c,d,q); // input at rising edge, resyncs to falling
module sdo1_2#(
parameter IOSTANDARD = "SSTL2_I",
parameter DRIVE = 12,
parameter SLEW = "SLOW"
)(c,d,q); // input at rising edge, resyncs to falling
input c;
input d;
output q;
sdo0_2 i_q (.c(c),.d(d),.q(q));
sdo0_2 #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_q (.c(c),.d(d),.q(q));
// s--ynthesis attribute KEEP_HIERARCHY of i_q is "TRUE"
endmodule
module sdo0_2(c,d,q); // input at rising edge, resyncs to falling, initializes to "1"
module sdo0_2 #(
parameter IOSTANDARD = "SSTL2_I",
parameter DRIVE = 12,
parameter SLEW = "SLOW"
)(c,d,q); // input at rising edge, resyncs to falling, initializes to "1"
input c;
input d;
output q;
wire d0, dr;
OBUF i_q (.I(dr), .O(q));
OBUF #(.IOSTANDARD(IOSTANDARD), .DRIVE(DRIVE), .SLEW(SLEW)) i_q (.I(dr), .O(q));
FD #(.INIT(1'b1)) i_d0 (.C(c), .D(d), .Q(d0));
//FD_1 i_dr (.C(c), .D(d), .Q(dr));
FD_1 #(.INIT(1'b1)) i_dr (.C(c), .D(d0), .Q(dr));
......
x353.v
View file @ 59d8b5dc
......@@ -31,15 +31,86 @@
`define debug_compressor
`define debug_mcontr_reset
// `define DEBUG_IMU
module x353(PXD,DCLK,BPF,VACT,HACT,MRST,ARO,ARST,SCL0,SDA0,CNVSYNC,CNVCLK, SENSPGM,
DUMMYVFEF, ALWAYS0,
EXT,
CLK3,CLK2,CLK4,CLK1,CLK0,
UDQS,LDQS,SDD,SDA,SDWE,SDCAS,SDRAS,SDUDM,SDLDM,SDCLK_FB,SDCLK,SDNCLK,SDNCLK_FB,SDCLKE,
D,A,
BA,SYS_SDWE,SYS_SDCAS,SYS_SDRAS,SYS_SDCLKI,SYS_SDCLK,SYS_BUSEN,
WE,OE,CE,CE1,DREQ0,DACK0,DREQ1,DACK1,
IRQ,BG,BRIN,BROUT);
module x353 #(
parameter IOSTANDARD_EXT = "LVCMOS33",
parameter SLEW_EXT = "SLOW",
parameter DRIVE_EXT = 12,
parameter IOSTANDARD_SENSOR = "LVCMOS33",
parameter SLEW_SENSOR = "SLOW",
parameter DRIVE_SENSOR = 4,
parameter IOSTANDARD_SENSOR_CLK = "LVCMOS33",
parameter SLEW_SENSOR_CLK = "SLOW",
parameter DRIVE_SENSOR_CLK = 4,
parameter IOSTANDARD_SDRAM = "SSTL2_I",
parameter DRIVE_SDRAM_DATA = 12,
parameter SLEW_SDRAM_DATA = "SLOW",
parameter DRIVE_SDRAM_ABC = 12,
parameter SLEW_SDRAM_ABC = "SLOW",
parameter IOSTANDARD_SDRAM_DIFF = "DIFF_SSTL2_I",
parameter SLEW_SDRAM_DIFF = "SLOW"
) (
inout [9:0] PXD,
inout DCLK,
inout BPF,
input VACT,
input HACT,
inout MRST,
output ARO,
output ARST,
inout SCL0,
inout SDA0,
inout CNVSYNC,
inout CNVCLK,
inout SENSPGM,
inout DUMMYVFEF, // output is not enough
inout ALWAYS0, // will be pulled down to fool the software - it does not know it is always 0.
inout [11:0] EXT,
input CLK3,
input CLK2,
input CLK4,
input CLK1,
input CLK0,
inout UDQS,
inout LDQS,
inout [15:0] SDD,
output [14:0] SDA,
output SDWE,
output SDCAS,
output SDRAS,
output SDUDM,
output SDLDM,
input SDCLK_FB,
output SDCLK,
output SDNCLK,
input SDNCLK_FB,
output SDCLKE,
inout [31:0] D,
inout [12:0] A,
inout [1:0] BA,
output SYS_SDWE,
output SYS_SDCAS,
output SYS_SDRAS,
input SYS_SDCLKI,
output SYS_SDCLK,
output SYS_BUSEN,
input WE,
input OE,
input CE,
input CE1,
output DREQ0,
input DACK0,
output DREQ1,
input DACK1,
output IRQ,
output BG,
input BRIN,
output BROUT);
parameter MODELREV=32'h0353402b; // adding more bits to motors positions
// parameter MODELREV=32'h0353402a; // IMU restart after ready (DIO2)
// parameter MODELREV=32'h03534029; // working on IMU
......@@ -160,91 +231,13 @@ module x353(PXD,DCLK,BPF,VACT,HACT,MRST,ARO,ARST,SCL0,SDA0,CNVSYNC,CNVCLK, SENSP
// parameter MODELREV=32'h0333000f; // temporarily reusing for rev B
// parameter MODELREV=32'h0333000e; // restoring JPEG
inout [9:0] PXD;
inout BPF;
input HACT;
input VACT;
input CLK4;
input CLK3;
input CLK2;
input CLK1;
input CLK0;
input SDCLK_FB;
input SDNCLK_FB;
inout [12:0] A;
output [ 1:0] BA;
input WE;
input OE;
input CE;
input CE1;
input DACK0;
input DACK1;
inout SCL0;
inout SDA0;
inout [11:0] EXT;
inout [15:0] SDD;
inout UDQS;
inout LDQS;
inout [31:0] D;
inout DCLK;
inout MRST;
output ARO;
output ARST;
inout CNVSYNC;
inout CNVCLK;
output [14:0] SDA;
output SDCLK;
output SDNCLK;
output SDCLKE;
output SDWE;
output SDCAS;
output SDRAS;
output SDUDM;
output SDLDM;
output DREQ0;
output DREQ1;
output IRQ;
inout SENSPGM; // grounded on 10338
output SYS_SDWE, SYS_SDCAS, SYS_SDRAS,SYS_SDCLK,SYS_BUSEN,BG,BROUT;
input SYS_SDCLKI,BRIN;
inout DUMMYVFEF; // output is not enough
inout ALWAYS0; // will be pulled down to fool the software - it does not know it is always 0.
PULLDOWN i_PD_ALWAYS0(.O(ALWAYS0)); // Pulldown output (connect directly to top-level port)
`ifdef debug_mcontr_reset
wire [31:0] debug_mcontr_reset_data;
`endif
// external wires
wire [14:0] SDA; //+
wire SDRAS; //+
wire SDCAS; //+
wire SDWE; //+
wire DCLK;
wire MRST;
wire ARO;
wire ARST;
wire CNVSYNC;
wire CNVCLK;
///AF: wire XRST;
///AF: wire AUXCLK;
wire SDCLK;
wire DREQ0,DREQ1;
wire IRQ;
// internal wires
wire iclk3;
......@@ -705,20 +698,55 @@ wire [3:0] restart; // reinitialize mcontr channels (normally after frame syn
// will change bits later (with software) to separate MRST and CLK sensor polarity
// IO pads and related FFs
sddrio16 i_SDDd (.c0(sclk0),/*.c90(sclk90),*/.c270(sclk270),
.d(sddo_p[31:0]),.t(pretrist),
.q(sddi_r[31:0]),.dq(SDD[15:0]));
sddrdm i_SDUDM (.c0(sclk0),/*.c90(sclk90),*/.c270(sclk270),.d(sddm_p[1:0]),.dq(SDUDM));
sddrdm i_SDLDM (.c0(sclk0),/*.c90(sclk90),*/.c270(sclk270),.d(sddm_p[1:0]),.dq(SDLDM));
sdo15_2 i_SDA (.c(sclk0),.d({sdba_p[1:0],sda_p[12:0]}),.q(SDA[14:0]));
sdo1_2 i_SDRAS (.c(sclk0),.d(sdras_p),.q(SDRAS));
sdo1_2 i_SDCAS (.c(sclk0),.d(sdcas_p),.q(SDCAS));
sdo1_2 i_SDWE (.c(sclk0),.d(sdwe_p),. q(SDWE ));
sdo1_2 i_SDCLKE (.c(sclk0),.d(1'b1),. q(SDCLKE ));
sddrio16 #(
.IOSTANDARD (IOSTANDARD_SDRAM),
.DRIVE (DRIVE_SDRAM_DATA),
.SLEW (SLEW_SDRAM_DATA))
i_SDDd (.c0(sclk0),.c270(sclk270),
.d(sddo_p[31:0]),.t(pretrist),
.q(sddi_r[31:0]),.dq(SDD[15:0]));
sddrdm #(
.IOSTANDARD (IOSTANDARD_SDRAM),
.DRIVE (DRIVE_SDRAM_DATA),
.SLEW (SLEW_SDRAM_DATA))
i_SDUDM (.c0(sclk0),.c270(sclk270),.d(sddm_p[1:0]),.dq(SDUDM));
sddrdm #(
.IOSTANDARD (IOSTANDARD_SDRAM),
.DRIVE (DRIVE_SDRAM_DATA),
.SLEW (SLEW_SDRAM_DATA))
i_SDLDM (.c0(sclk0),.c270(sclk270),.d(sddm_p[1:0]),.dq(SDLDM));
sdo15_2 #(
.IOSTANDARD (IOSTANDARD_SDRAM),
.DRIVE (DRIVE_SDRAM_ABC),
.SLEW (SLEW_SDRAM_ABC))
i_SDA (.c(sclk0),.d({sdba_p[1:0],sda_p[12:0]}),.q(SDA[14:0]));
sdo1_2 #(
.IOSTANDARD (IOSTANDARD_SDRAM),
.DRIVE (DRIVE_SDRAM_ABC),
.SLEW (SLEW_SDRAM_ABC))
i_SDRAS (.c(sclk0),.d(sdras_p),.q(SDRAS));
sdo1_2 #(
.IOSTANDARD (IOSTANDARD_SDRAM),
.DRIVE (DRIVE_SDRAM_ABC),
.SLEW (SLEW_SDRAM_ABC))
i_SDCAS (.c(sclk0),.d(sdcas_p),.q(SDCAS));
sdo1_2 #(
.IOSTANDARD (IOSTANDARD_SDRAM),
.DRIVE (DRIVE_SDRAM_ABC),
.SLEW (SLEW_SDRAM_ABC))
i_SDWE (.c(sclk0),.d(sdwe_p),. q(SDWE ));
sdo1_2 #(
.IOSTANDARD (IOSTANDARD_SDRAM),
.DRIVE (DRIVE_SDRAM_ABC),
.SLEW (SLEW_SDRAM_ABC))
i_SDCLKE (.c(sclk0),.d(1'b1),. q(SDCLKE ));
// temporary change behaviour of dqs2 to fix pinout problem - will influence adjustment goal
dqs2 i_sddqs(.c0(sclk0),/*.c90(sclk90),*/.c270(sclk270),
dqs2 #(.IOSTANDARD(IOSTANDARD_SDRAM),
.DRIVE (DRIVE_SDRAM_DATA),
.SLEW (SLEW_SDRAM_DATA))
i_sddqs(.c0(sclk0), .c270(sclk270),
.t (sddqt), // 1/2 cycle before cmd "write" sent out to the SDRAM, sync to sclk180
.UDQS (UDQS), // UDQS I/O pin
.LDQS (LDQS), // LDQS I/O pin
......@@ -898,7 +926,7 @@ timestamp353 i_timestamp353(.mclk(sclk0), // system clock (negedge)
//SDCLK_FB // feedback input from SDCLK pin
//SDNCLK_FB // feedback input from SDCLK pin
// IBUFDS i_sdcl_fb(.O(sdcl_fb),.I(SDCLK_FB),.IB(SDNCLK_FB)); // not used
IBUFDS i_sdcl_fb(.O(sdcl_fb),.I(SDNCLK_FB),.IB(SDCLK_FB)); // not used
IBUFDS #(.IOSTANDARD(IOSTANDARD_SDRAM_DIFF)) i_sdcl_fb(.O(sdcl_fb),.I(SDNCLK_FB),.IB(SDCLK_FB)); // not used
// synthesis attribute KEEP of i_sdcl_fb is "TRUE"
// assumed CL=2.5
......@@ -961,7 +989,10 @@ BUFGMUX i_pclk (.O(pclk), .I0(pclki), .I1(sens_clk), .S(|cb_pclksrc[1:0]));
dcm333 i_dcm333( .sclk(sclk0), // input clock pad - 120MHz
dcm333 #(
.IOSTANDARD_SDRAM_DIFF (IOSTANDARD_SDRAM_DIFF),
.SLEW_SDRAM_DIFF (SLEW_SDRAM_DIFF)
) i_dcm333 ( .sclk(sclk0), // input clock pad - 120MHz
.SDCLK(SDCLK), // positive clock to SDRAM
.SDNCLK(SDNCLK), // negative clock to SDRAM
.sdcl_fb(sdcl_fb),
......@@ -1007,7 +1038,14 @@ always @ (posedge pclk) begin
end
sensorpads i_sensorpads (
sensorpads #(
.IOSTANDARD_SENSOR (IOSTANDARD_SENSOR),
.SLEW_SENSOR (SLEW_SENSOR),
.DRIVE_SENSOR (DRIVE_SENSOR),
.IOSTANDARD_SENSOR_CLK (IOSTANDARD_SENSOR_CLK),
.SLEW_SENSOR_CLK (SLEW_SENSOR_CLK),
.DRIVE_SENSOR_CLK (DRIVE_SENSOR_CLK)
) i_sensorpads(
.sclk(sclk0), // system clock, @negedge
.cmd(idi[10:4]), // [6:0] command for phase adjustment @ negedge (slck) (MSB - reset x2 DCM)
.wcmd(da_dcm), // write command@ negedge (slck)
......@@ -1725,20 +1763,30 @@ wire iclk4; // SuppressThisWarning Veditor UNUSED
///AF: assign sr_sda1=io_pins[1];
///AF: assign sr_scl1=io_pins[0];
IOBUF i_iopins0 (.I(io_do[ 0]), .T(io_t[ 0]), .O(io_pins[ 0]), .IO(EXT[ 0]));
IOBUF i_iopins1 (.I(io_do[ 1]), .T(io_t[ 1]), .O(io_pins[ 1]), .IO(EXT[ 1]));
IOBUF i_iopins2 (.I(io_do[ 2]), .T(io_t[ 2]), .O(io_pins[ 2]), .IO(EXT[ 2]));
IOBUF i_iopins3 (.I(io_do[ 3]), .T(io_t[ 3]), .O(io_pins[ 3]), .IO(EXT[ 3]));
IOBUF i_iopins4 (.I(io_do[ 4]), .T(io_t[ 4]), .O(io_pins[ 4]), .IO(EXT[ 4]));
IOBUF i_iopins5 (.I(io_do[ 5]), .T(io_t[ 5]), .O(io_pins[ 5]), .IO(EXT[ 5]));
IOBUF i_iopins6 (.I(io_do[ 6]), .T(io_t[ 6]), .O(io_pins[ 6]), .IO(EXT[ 6]));
IOBUF i_iopins7 (.I(io_do[ 7]), .T(io_t[ 7]), .O(io_pins[ 7]), .IO(EXT[ 7]));
IOBUF i_iopins8 (.I(io_do[ 8]), .T(io_t[ 8]), .O(io_pins[ 8]), .IO(EXT[ 8]));
IOBUF i_iopins9 (.I(io_do[ 9]), .T(io_t[ 9]), .O(io_pins[ 9]), .IO(EXT[ 9]));
IOBUF i_iopins10(.I(io_do[10]), .T(io_t[10]), .O(io_pins[10]), .IO(EXT[10]));
IOBUF i_iopins11(.I(io_do[11]), .T(io_t[11]), .O(io_pins[11]), .IO(EXT[11]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins0 (.I(io_do[ 0]), .T(io_t[ 0]), .O(io_pins[ 0]), .IO(EXT[ 0]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins1 (.I(io_do[ 1]), .T(io_t[ 1]), .O(io_pins[ 1]), .IO(EXT[ 1]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins2 (.I(io_do[ 2]), .T(io_t[ 2]), .O(io_pins[ 2]), .IO(EXT[ 2]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins3 (.I(io_do[ 3]), .T(io_t[ 3]), .O(io_pins[ 3]), .IO(EXT[ 3]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins4 (.I(io_do[ 4]), .T(io_t[ 4]), .O(io_pins[ 4]), .IO(EXT[ 4]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins5 (.I(io_do[ 5]), .T(io_t[ 5]), .O(io_pins[ 5]), .IO(EXT[ 5]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins6 (.I(io_do[ 6]), .T(io_t[ 6]), .O(io_pins[ 6]), .IO(EXT[ 6]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins7 (.I(io_do[ 7]), .T(io_t[ 7]), .O(io_pins[ 7]), .IO(EXT[ 7]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins8 (.I(io_do[ 8]), .T(io_t[ 8]), .O(io_pins[ 8]), .IO(EXT[ 8]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins9 (.I(io_do[ 9]), .T(io_t[ 9]), .O(io_pins[ 9]), .IO(EXT[ 9]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins10(.I(io_do[10]), .T(io_t[10]), .O(io_pins[10]), .IO(EXT[10]));
IOBUF #(.IOSTANDARD(IOSTANDARD_EXT), .SLEW(SLEW_EXT), .DRIVE(DRIVE_EXT))
i_iopins11(.I(io_do[11]), .T(io_t[11]), .O(io_pins[11]), .IO(EXT[11]));
endmodule
x353.xcf
View file @ 59d8b5dc
......@@ -3,188 +3,187 @@
# Project: ~/PCB/10353/REVB/10353b
# Created: Sat Jan 20 01:40:47 2007
NET "PXD<0>" LOC = "J3" | IOSTANDARD = "LVCMOS25" ;
NET "PXD<1>" LOC = "H6" | IOSTANDARD = "LVCMOS25" ;
NET "PXD<2>" LOC = "J2" | IOSTANDARD = "LVCMOS25" ;
NET "PXD<3>" LOC = "H5" | IOSTANDARD = "LVCMOS25" ;
NET "PXD<4>" LOC = "J1" | IOSTANDARD = "LVCMOS25" ;
NET "PXD<5>" LOC = "G5" | IOSTANDARD = "LVCMOS25" ;
NET "PXD<6>" LOC = "H4" | IOSTANDARD = "LVCMOS25" ;
NET "PXD<7>" LOC = "G4" | IOSTANDARD = "LVCMOS25" ;
NET "PXD<8>" LOC = "G3" | IOSTANDARD = "LVCMOS25" ;
NET "PXD<9>" LOC = "H3" | IOSTANDARD = "LVCMOS25" ;
#NET "DCLK" LOC = "L3" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 2 ; # default
NET "DCLK" LOC = "L3" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW" | DRIVE = 4 ; # increased for Eyesis4pi 450mm cable
NET "BPF" LOC = "K5" | IOSTANDARD = "LVCMOS25" ;
NET "VACT" LOC = "K1" | IOSTANDARD = "LVCMOS25" ;
NET "HACT" LOC = "J5" | IOSTANDARD = "LVCMOS25" ;
NET "MRST" LOC = "E3" | IOSTANDARD = "LVCMOS25" ;
NET "ARO" LOC = "C1" | IOSTANDARD = "LVCMOS25" ;
NET "ARST" LOC = "E1" | IOSTANDARD = "LVCMOS25" ;
NET "SCL0" LOC = "G2" | IOSTANDARD = "LVCMOS25" ;
NET "SDA0" LOC = "E4" | IOSTANDARD = "LVCMOS25" ;
NET "CNVSYNC" LOC = "B1" | IOSTANDARD = "LVCMOS25" ;
NET "CNVCLK" LOC = "B2" | IOSTANDARD = "LVCMOS25" ;
NET "SENSPGM" LOC = "D1" | IOSTANDARD = "LVCMOS25" ;
NET "EXT<0>" LOC = "C4" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<1>" LOC = "C5" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<2>" LOC = "A4" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<3>" LOC = "A5" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<4>" LOC = "D6" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<5>" LOC = "C6" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<6>" LOC = "C7" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<7>" LOC = "B7" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<8>" LOC = "E7" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<9>" LOC = "D7" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<10>" LOC = "F8" | IOSTANDARD = "LVCMOS33" ;
NET "EXT<11>" LOC = "E8" | IOSTANDARD = "LVCMOS33" ;
NET "CLK3" LOC = "A8" | IOSTANDARD = "LVCMOS33" ;
NET "CLK2" LOC = "C9" | IOSTANDARD = "LVCMOS33" ;
NET "CLK4" LOC = "B8" | IOSTANDARD = "LVCMOS33" ;
NET "CLK1" LOC = "A10" | IOSTANDARD = "LVCMOS33" ;
NET "CLK0" LOC = "A9" | IOSTANDARD = "LVCMOS33" ;
NET "LDQS" LOC = "N8" | IOSTANDARD = "SSTL2_I" ;
NET "UDQS" LOC = "P8" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<0>" LOC = "R14" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<1>" LOC = "T12" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<2>" LOC = "N12" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<3>" LOC = "N10" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<4>" LOC = "R11" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<5>" LOC = "N9" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<6>" LOC = "M9" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<7>" LOC = "L8" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<8>" LOC = "P9" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<9>" LOC = "P10" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<10>" LOC = "M10" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<11>" LOC = "P11" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<12>" LOC = "P12" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<13>" LOC = "R13" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<14>" LOC = "T13" | IOSTANDARD = "SSTL2_I" ;
NET "SDD<15>" LOC = "P14" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<0>" LOC = "P1" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<1>" LOC = "K3" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<2>" LOC = "M1" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<3>" LOC = "K2" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<4>" LOC = "T4" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<5>" LOC = "M4" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<6>" LOC = "T5" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<7>" LOC = "P5" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<8>" LOC = "N5" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<9>" LOC = "R6" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<10>" LOC = "N1" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<11>" LOC = "P6" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<12>" LOC = "P7" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<13>" LOC = "P2" | IOSTANDARD = "SSTL2_I" ;
NET "SDA<14>" LOC = "L4" | IOSTANDARD = "SSTL2_I" ;
NET "SDWE" LOC = "M7" | IOSTANDARD = "SSTL2_I" ;
NET "SDCAS" LOC = "N7" | IOSTANDARD = "SSTL2_I" ;
NET "SDRAS" LOC = "M6" | IOSTANDARD = "SSTL2_I" ;
NET "SDLDM" LOC = "M8" | IOSTANDARD = "SSTL2_I" ;
NET "SDUDM" LOC = "T8" | IOSTANDARD = "SSTL2_I" ;
NET "SDCLK" LOC = "R2" | IOSTANDARD = DIFF_SSTL2_I ;
NET "SDCLK_FB" LOC = "R3" | IOSTANDARD = DIFF_SSTL2_I ;
NET "SDNCLK" LOC = "R1" | IOSTANDARD = DIFF_SSTL2_I ;
NET "SDNCLK_FB" LOC = "T3" | IOSTANDARD = DIFF_SSTL2_I ;
#NET "SDNCLK_FB" LOC = "T3" | IOSTANDARD = "DIFF_SSTL2_I" ;
#NET "SDCLK_FB" LOC = "R3" | IOSTANDARD = "DIFF_SSTL2_I" ;
#NET "SDCLK" LOC = "R2" | IOSTANDARD = "DIFF_SSTL2_I ";
#NET "SDNCLK" LOC = "R1" | IOSTANDARD = "DIFF_SSTL2_I ";
NET "SDCLKE" LOC = "N6" | IOSTANDARD = "SSTL2_I" ;
NET "D<0>" LOC = "M16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<1>" LOC = "N15" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<2>" LOC = "N16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<3>" LOC = "L13" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<4>" LOC = "P16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<5>" LOC = "N14" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<6>" LOC = "R16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<7>" LOC = "P15" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<8>" LOC = "R15" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<9>" LOC = "L12" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<10>" LOC = "C11" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<11>" LOC = "A13" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<12>" LOC = "B11" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<13>" LOC = "D9" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<14>" LOC = "B10" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<15>" LOC = "A12" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<16>" LOC = "A7" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<17>" LOC = "K12" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<18>" LOC = "E9" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<19>" LOC = "B4" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<20>" LOC = "F9" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<21>" LOC = "C3" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<22>" LOC = "H11" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<23>" LOC = "B6" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<24>" LOC = "K14" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<25>" LOC = "E10" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<26>" LOC = "K15" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<27>" LOC = "L14" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<28>" LOC = "L15" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<29>" LOC = "K13" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<30>" LOC = "C8" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "D<31>" LOC = "D8" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8 ;
NET "A<0>" LOC = "D14" | IOSTANDARD = "LVCMOS33" ;
NET "A<1>" LOC = "F13" | IOSTANDARD = "LVCMOS33" ;
NET "A<2>" LOC = "F12" | IOSTANDARD = "LVCMOS33" ;
NET "A<3>" LOC = "E11" | IOSTANDARD = "LVCMOS33" ;
NET "A<4>" LOC = "E13" | IOSTANDARD = "LVCMOS33" ;
NET "A<5>" LOC = "E16" | IOSTANDARD = "LVCMOS33" ;
NET "A<6>" LOC = "F14" | IOSTANDARD = "LVCMOS33" ;
NET "A<7>" LOC = "F15" | IOSTANDARD = "LVCMOS33" ;
NET "A<8>" LOC = "G14" | IOSTANDARD = "LVCMOS33" ;
NET "A<9>" LOC = "G13" | IOSTANDARD = "LVCMOS33" ;
NET "A<10>" LOC = "G16" | IOSTANDARD = "LVCMOS33" ;
NET "A<11>" LOC = "G15" | IOSTANDARD = "LVCMOS33" ;
NET "A<12>" LOC = "H12" | IOSTANDARD = "LVCMOS33" ;
NET "BA<0>" LOC = "H14" | IOSTANDARD = "LVCMOS33" ;
NET "BA<1>" LOC = "H15" | IOSTANDARD = "LVCMOS33" ;
NET "SYS_SDWE" LOC = "J13" | IOSTANDARD = "LVCMOS33" ;
NET "SYS_SDCAS" LOC = "J16" | IOSTANDARD = "LVCMOS33" ;
NET "SYS_SDRAS" LOC = "K16" | IOSTANDARD = "LVCMOS33" ;
NET "SYS_SDCLKI" LOC = "J12" | IOSTANDARD = "LVCMOS33" ;
NET "SYS_SDCLK" LOC = "J14" | IOSTANDARD = "LVCMOS33" ;
NET "SYS_BUSEN" LOC = "C16" | IOSTANDARD = "LVCMOS33" ;
NET "WE" LOC = "M13" | IOSTANDARD = "LVCMOS33" ;
NET "OE" LOC = "M14" | IOSTANDARD = "LVCMOS33" ;
NET "CE" LOC = "D16" | IOSTANDARD = "LVCMOS33" ;
NET "CE1" LOC = "E14" | IOSTANDARD = "LVCMOS33" ;
NET "DREQ0" LOC = "C15" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 4 ; # default
NET "DACK0" LOC = "B14" | IOSTANDARD = "LVCMOS33" ;
NET "DREQ1" LOC = "D10" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 4 ; # default
NET "DACK1" LOC = "A14" | IOSTANDARD = "LVCMOS33" ;
NET "IRQ" LOC = "D15" | IOSTANDARD = "LVCMOS33" ;
NET "BG" LOC = "D11" | IOSTANDARD = "LVCMOS33" ;
NET "BRIN" LOC = "B16" | IOSTANDARD = "LVCMOS33" ;
NET "BROUT" LOC = "B13" | IOSTANDARD = "LVCMOS33" ;
#Only pinout
NET "PXD<0>" LOC = "J3" ;
NET "PXD<1>" LOC = "H6" ;
NET "PXD<2>" LOC = "J2" ;
NET "PXD<3>" LOC = "H5" ;
NET "PXD<4>" LOC = "J1" ;
NET "PXD<5>" LOC = "G5" ;
NET "PXD<6>" LOC = "H4" ;
NET "PXD<7>" LOC = "G4" ;
NET "PXD<8>" LOC = "G3" ;
NET "PXD<9>" LOC = "H3" ;
NET "DCLK" LOC = "L3" ;
NET "BPF" LOC = "K5" ;
NET "VACT" LOC = "K1" ;
NET "HACT" LOC = "J5" ;
NET "MRST" LOC = "E3" ;
NET "ARO" LOC = "C1" ;
NET "ARST" LOC = "E1" ;
NET "SCL0" LOC = "G2" ;
NET "SDA0" LOC = "E4" ;
NET "CNVSYNC" LOC = "B1" ;
NET "CNVCLK" LOC = "B2" ;
NET "SENSPGM" LOC = "D1" ;
NET "EXT<0>" LOC = "C4" ;
NET "EXT<1>" LOC = "C5" ;
NET "EXT<2>" LOC = "A4" ;
NET "EXT<3>" LOC = "A5" ;
NET "EXT<4>" LOC = "D6" ;
NET "EXT<5>" LOC = "C6" ;
NET "EXT<6>" LOC = "C7" ;
NET "EXT<7>" LOC = "B7" ;
NET "EXT<8>" LOC = "E7" ;
NET "EXT<9>" LOC = "D7" ;
NET "EXT<10>" LOC = "F8" ;
NET "EXT<11>" LOC = "E8" ;
NET "CLK3" LOC = "A8" ;
NET "CLK2" LOC = "C9" ;
NET "CLK4" LOC = "B8" ;
NET "CLK1" LOC = "A10" ;
NET "CLK0" LOC = "A9" ;
NET "LDQS" LOC = "N8" ;
NET "UDQS" LOC = "P8" ;
NET "SDD<0>" LOC = "R14" ;
NET "SDD<1>" LOC = "T12" ;
NET "SDD<2>" LOC = "N12" ;
NET "SDD<3>" LOC = "N10" ;
NET "SDD<4>" LOC = "R11" ;
NET "SDD<5>" LOC = "N9" ;
NET "SDD<6>" LOC = "M9" ;
NET "SDD<7>" LOC = "L8" ;
NET "SDD<8>" LOC = "P9" ;
NET "SDD<9>" LOC = "P10" ;
NET "SDD<10>" LOC = "M10" ;
NET "SDD<11>" LOC = "P11" ;
NET "SDD<12>" LOC = "P12" ;
NET "SDD<13>" LOC = "R13" ;
NET "SDD<14>" LOC = "T13" ;
NET "SDD<15>" LOC = "P14" ;
NET "SDA<0>" LOC = "P1" ;
NET "SDA<1>" LOC = "K3" ;
NET "SDA<2>" LOC = "M1" ;
NET "SDA<3>" LOC = "K2" ;
NET "SDA<4>" LOC = "T4" ;
NET "SDA<5>" LOC = "M4" ;
NET "SDA<6>" LOC = "T5" ;
NET "SDA<7>" LOC = "P5" ;
NET "SDA<8>" LOC = "N5" ;
NET "SDA<9>" LOC = "R6" ;
NET "SDA<10>" LOC = "N1" ;
NET "SDA<11>" LOC = "P6" ;
NET "SDA<12>" LOC = "P7" ;
NET "SDA<13>" LOC = "P2" ;
NET "SDA<14>" LOC = "L4" ;
NET "SDWE" LOC = "M7" ;
NET "SDCAS" LOC = "N7" ;
NET "SDRAS" LOC = "M6" ;
NET "SDLDM" LOC = "M8" ;
NET "SDUDM" LOC = "T8" ;
#NET "SDCLK" LOC = "R2" | IOSTANDARD = "DIFF_SSTL2_I" ;
NET "SDCLK" LOC = "R2" ;
NET "SDCLK_FB" LOC = "R3" ;
NET "SDNCLK" LOC = "R1" ;
NET "SDNCLK_FB" LOC = "T3" ;
NET "SDCLKE" LOC = "N6" ;
NET "D<0>" LOC = "M16" ;
NET "D<1>" LOC = "N15" ;
NET "D<2>" LOC = "N16" ;
NET "D<3>" LOC = "L13" ;
NET "D<4>" LOC = "P16" ;
NET "D<5>" LOC = "N14" ;
NET "D<6>" LOC = "R16" ;
NET "D<7>" LOC = "P15" ;
NET "D<8>" LOC = "R15" ;
NET "D<9>" LOC = "L12" ;
NET "D<10>" LOC = "C11" ;
NET "D<11>" LOC = "A13" ;
NET "D<12>" LOC = "B11" ;
NET "D<13>" LOC = "D9" ;
NET "D<14>" LOC = "B10" ;
NET "D<15>" LOC = "A12" ;
NET "D<16>" LOC = "A7" ;
NET "D<17>" LOC = "K12" ;
NET "D<18>" LOC = "E9" ;
NET "D<19>" LOC = "B4" ;
NET "D<20>" LOC = "F9" ;
NET "D<21>" LOC = "C3" ;
NET "D<22>" LOC = "H11" ;
NET "D<23>" LOC = "B6" ;
NET "D<24>" LOC = "K14" ;
NET "D<25>" LOC = "E10" ;
NET "D<26>" LOC = "K15" ;
NET "D<27>" LOC = "L14" ;
NET "D<28>" LOC = "L15" ;
NET "D<29>" LOC = "K13" ;
NET "D<30>" LOC = "C8" ;
NET "D<31>" LOC = "D8" ;
NET "A<0>" LOC = "D14" ;
NET "A<1>" LOC = "F13" ;
NET "A<2>" LOC = "F12" ;
NET "A<3>" LOC = "E11" ;
NET "A<4>" LOC = "E13" ;
NET "A<5>" LOC = "E16" ;
NET "A<6>" LOC = "F14" ;
NET "A<7>" LOC = "F15" ;
NET "A<8>" LOC = "G14" ;
NET "A<9>" LOC = "G13" ;
NET "A<10>" LOC = "G16" ;
NET "A<11>" LOC = "G15" ;
NET "A<12>" LOC = "H12" ;
NET "BA<0>" LOC = "H14" ;
NET "BA<1>" LOC = "H15" ;
NET "SYS_SDWE" LOC = "J13" ;
NET "SYS_SDCAS" LOC = "J16" ;
NET "SYS_SDRAS" LOC = "K16" ;
NET "SYS_SDCLKI" LOC = "J12" ;
NET "SYS_SDCLK" LOC = "J14" ;
NET "SYS_BUSEN" LOC = "C16" ;
NET "WE" LOC = "M13" ;
NET "OE" LOC = "M14" ;
NET "CE" LOC = "D16" ;
NET "CE1" LOC = "E14" ;
NET "DREQ0" LOC = "C15" ;
NET "DACK0" LOC = "B14" ;
NET "DREQ1" LOC = "D10" ;
NET "DACK1" LOC = "A14" ;
NET "IRQ" LOC = "D15" ;
NET "BG" LOC = "D11" ;
NET "BRIN" LOC = "B16" ;
NET "BROUT" LOC = "B13" ;
#assign an output with SSTL2_I so VREF will be used in bank 3
NET "DUMMYVFEF" LOC = "J4" | IOSTANDARD = "SSTL2_I" ;
NET "DUMMYVFEF" LOC = "J4" ;
#week pulldown to fool the software into keeping signals
NET "ALWAYS0" LOC = "J6" | IOSTANDARD = "LVCMOS25" ;
NET "ALWAYS0" LOC = "J6" ;
#end of pinout
################### Timing Constraints #########################
NET "CLK0" TNM_NET = "CLK0";
NET "CLK1" TNM_NET = "CLK1";
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment