Loading NC353_TESTING/README.md 0 → 100644 +78 −0 Original line number Original line Diff line number Diff line Testing new generated bitstream images in Elphel NC353 cameras ============================================================== CAUTION: Replacing /etc/x353.bit bit file with the experimental one can make the camera hang, at it it will repeat each time you reboot the camera as the /etc/init.d/fpga script will attempt to use the same file again. Here is the modified version of this script - you may use ftp client to replace the original 'fpga' script: $ ftp 192.168.0.9 Connected to 192.168.0.9. 220 Elphel (R) Model 353 Camera release 8.2.16 (May 16 2015) ready. Name (192.168.0.9:user): root 331 User name okay, need password. Password: <pass> 230 User logged in, proceed. Remote system type is UNIX. Using binary mode to transfer files. ftp> cd /etc/init.d 250 Command successful. ftp> put fpga local: fpga remote: fpga 200 Command okay. 150 Opening data connection. 226 Transfer complete. 16251 bytes sent in 0.00 secs (453431.9 kB/s) ftp> exit 221 Goodbye. This is the modified part of the script: FPGA_ONE_TIME_IMAGE="/etc/x353_experimental.bit" FPGA_TMP_IMAGE="/var/tmp/x353_experimental.bit" if [ -f $FPGA_ONE_TIME_IMAGE ] ; then echo "Moving $FPGA_ONE_TIME_IMAGE to /var/tmp" mv $FPGA_ONE_TIME_IMAGE /var/tmp sync FPGA_IMAGE=$FPGA_TMP_IMAGE fi echo "For testing unsafe experimental bitsteam images:" echo "Name this file as $FPGA_ONE_TIME_IMAGE - it will be 'deleted before used'" echo "so next boot will use the original (safe) bitstream file" So regardless of success or failure of the testing of the experimental bitstream file it will be used only until the next reboot/power cycle. To test the new bitstream file you need to rename it to x353_experimental.bit and ftp to camera /etc directory (supposing you started from the local directory with the x353_experimental.bit file: $ ftp 192.168.0.9 Connected to 192.168.0.9. 220 Elphel (R) Model 353 Camera release 8.2.16 (May 16 2015) ready. Name (192.168.0.9:user): root 331 User name okay, need password. Password: <pass> 230 User logged in, proceed. Remote system type is UNIX. Using binary mode to transfer files. ftp> put x353_experimental.bit local: x353_experimental.bit remote: x353_experimental.bit 200 Command okay. 150 Opening data connection. 226 Transfer complete. 480220 bytes sent in 1.45 secs (324.2 kB/s) ftp> exit 221 Goodbye. A sample bitstream file is in the ISE_14_7_results directory, with the default project settings the new generated bitstream files will be in the ise_results subdirectory. It is a good idea to telnet to the camera and issue a 'sync' command (equivalent to the "safely remove" for the flash cards). Or just open [http://<your_camera_ip>/phpshell.php?command=sync] in the browser. Good hacking! Elphel team No newline at end of file NC353_TESTING/fpga 0 → 100755 +407 −0 Original line number Original line Diff line number Diff line #!/bin/sh #******************************************************************************** # FILE NAME : fpga # DESCRIPTION: fpgas configuration script # Copyright (C) 2012 Elphel, Inc # -----------------------------------------------------------------------------** # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation, either version 3 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # The four essential freedoms with GNU GPL software: # * the freedom to run the program for any purpose # * the freedom to study how the program works and change it to make it do what you wish # * the freedom to redistribute copies so you can help your neighbor # * the freedom to distribute copies of your modified versions to others # # You should have received a copy of the GNU General Public License # along with this program. If not, see <http://www.gnu.org/licenses/>. # -----------------------------------------------------------------------------** . /etc/init.d/functions.sh FPGA_IMAGE="/etc/x353.bit" FPGA_10359_IMAGE="/etc/x359.bit" FPGA_10347_IMAGE="/etc/x347.bit" FPGAFREQ=160 CABLECORR=450 #ps for 30 mm cable to sensor (or 10359 board, 10359-> sensor cables are set lower) ~15ps/mm, increase for longer cables. delete /etc/autocampars.xml to use new values. FPGA_ONE_TIME_IMAGE="/etc/x353_experimental.bit" FPGA_TMP_IMAGE="/var/tmp/x353_experimental.bit" if [ -f $FPGA_ONE_TIME_IMAGE ] ; then echo "Moving $FPGA_ONE_TIME_IMAGE to /var/tmp" mv $FPGA_ONE_TIME_IMAGE /var/tmp sync FPGA_IMAGE=$FPGA_TMP_IMAGE fi echo "For testing unsafe experimental bitsteam images:" echo "Name this file as $FPGA_ONE_TIME_IMAGE - it will be 'deleted before used'" echo "so next boot will use the original (safe) bitstream file" # if it was just after "init 3" from "init 4", flash was not mounted if [ ! -n "`mount | grep /mnt/flash`" ] ; then begin "Mounting /dev/part/rwfsblock as /mnt/flash" mount -t jffs2 /dev/part/rwfsblock /mnt/flash end $? fi fpcf -gwpd 7 $CABLECORR >/dev/null; ## Uncomment the next line to use system clock for the 10359-connected sensors. When commented - local (to 10359) oscillator is used #fpcf -gwpd 23 1 >/dev/null; # disable on-board clock generator - mooved to 10359 branch below #fpcf -gwpx 2 10000 >/dev/null; #debug mask #fpcf -gwpx 2 2000019 >/dev/null; #debug mask for troubleshooting startup with less sensors #fpcf -gwpx 2 A >/dev/null; #debug mask #fpcf -gwpx 2 B >/dev/null; #debug mask #fpcf -gwpx 2 8 >/dev/null; #debug mask #fpcf -gwpx 2 1000000 >/dev/null; #debug mask for SDRAM phase debug #echo "killall klogd" #killall klogd #echo "sleep 5" #sleep 5 #echo "echo 1 > /proc/sys/kernel/printk" #echo 1 > /proc/sys/kernel/printk #echo "cat /proc/kmsg >/var/html/klog.txt" #cat /proc/kmsg >/var/html/klog.txt & #fpcf -gwpx 2 48 >/dev/null; #debug mask #fpcf -gwpx 2 148 >/dev/null; #debug mask #fpcf -gwpx 2 14c >/dev/null; #debug mask #fpcf -gwpx 2 8 >/dev/null; #debug mask #fpcf -gwpx 2 14c >/dev/null; #debug mask FPGAPHASECORR=-8; # 0353301b: -44/+28 begin "Setting FPGA master clock to $FPGAFREQ MHz" fpcf -X 0 $FPGAFREQ >/dev/null end $? begin "Programming FPGA with $FPGA_IMAGE" cat $FPGA_IMAGE >/dev/fpgaconfjtag end $? # later will make default FPGA code not to turn on sensor clock at startup # turn off clcock to sensor board (float the pin) before configuring as x347 - with the clock long sensor cable does not work # it induces signal on "run" output of FPGA # fpcf -c 13 2 # #define X353DCR1__DCLKMODE__BITNM 4 # #define X313_WA_DCR1 0x4f fpcf -w 4f 30 >/dev/null # set clock from sensor (safe) begin "Loaded FPGA rev" FPGA_REV=`fpcf -r 13` if [ "$?" = 0 ]; then echo -e "${OKPOS}${BRACKET}[ ${GOOD}$FPGA_REV${BRACKET} ]${NORMAL}" else echo -e "${FAILPOS}${BRACKET}[ ${BAD}fail${BRACKET} ]${NORMAL}" fi case "$FPGA_REV" in '3534017') FPGAPHASECORR=-4; # # fpcf -gwpd 8 2580 >/dev/null; #2580 ps # fpcf -gwpd 8 1620 >/dev/null; #1620 ps -17E # fpcf -gwpd 8 3500 >/dev/null; measured , Xilinx 4824 fpcf -gwpd 8 1620 >/dev/null; #1793 ps -17D - from Xilinx (x1.38) ;; '3534018') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3500 >/dev/null; # fpcf -gwpd 8 2950 >/dev/null; #3615 ps -18D (C?) - from Xilinx (x1.225) # fpcf -gwpd 8 1400 >/dev/null; #1464 ps -18D - from Xilinx (x1.225) fpcf -gwpd 8 2940 >/dev/null; #3864 ps -18F (x1.314) ;; '3534019') FPGAPHASECORR=-4; # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401a') FPGAPHASECORR=-4; # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401b') FPGAPHASECORR=-4; # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401c') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401d') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401e') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401f') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '3534020') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '3534021') FPGAPHASECORR=-2; # fpcf -gwpd 8 1587 >/dev/null; #1.587 ns, sensor phase 0xffcc ;; '3534022') FPGAPHASECORR=-2; # fpcf -gwpd 8 3724 >/dev/null; #sen sensor phase ff84 ;; '3534024') FPGAPHASECORR=-2; # fpcf -gwpd 8 1932 >/dev/null; #sensor phase fff0 (decreased by 450ps of the cable) ;; '3534025') FPGAPHASECORR=-2; # fpcf -gwpd 8 1160 >/dev/null; #sensor phase 0xffcd ;; '353402a') FPGAPHASECORR=-9; # fpcf -gwpd 8 1160 >/dev/null; #sensor phase 0xffcd ;; '353402b') FPGAPHASECORR=-9; # fpcf -gwpd 8 1160 >/dev/null; #sensor phase 0xffcd ;; *) echo "**** Unknown FPGA revision ****" FPGAPHASECORR=-1; # does not work with "0" !!! (No "manually corrected") echo "Setting phase correction - always needed fro the new FPGA image." echo "Procedure to set the correct shift:" echo "1 - manually set the phase with " echo "fpcf -phase -65 63 <phase_correction_value>" echo " # setting 90-degrees with fpcf -w 8 c; repeating fpcf -w 8 8 as needed" echo "# 2 - test SDRAM, whatch for errors" echo "# 3 - find margins for the phase_correction_value (repeating steps 1 and 2), select average between low and high ones" echo "# 4 - update code below" ;; esac # Setting phase correction - always needed fro the new FPGA image. # Procedure to set the correct shift: # 1 - manually set the phase with # fpcf -phase -65 63 <phase_correction_value> # setting 90-degrees with fpcf -w 8 c; repeating fpcf -w 8 8 as needed # 2 - test SDRAM, whatch for errors # 3 - find margins for the phase_correction_value (repeating steps 1 and 2), select average between low and high ones # 4 - update code below begin "Adjusting DDR SDRAM clock phase" fpcf -phase -65 63 $FPGAPHASECORR > /var/log/fpga_sdram_phase # for 3533017 @ 160MHz (one failed at 69) if [ "$?" = 0 ]; then SDRAMPHASE=`cat /var/log/fpga_sdram_phase | grep "manually" | sed -e 's/manually corrected optimal phase = \([-0-9]*\).*/\1/'` echo -e "${OKPOS}${BRACKET}[ ${GOOD}PH 0/${SDRAMPHASE}${BRACKET} ]${NORMAL}" else fpcf -w 8 8 >/dev/null fpcf -phase -65 63 $FPGAPHASECORR > /var/log/fpga_sdram_phase if [ "$?" = 0 ]; then SDRAMPHASE=`cat /var/log/fpga_sdram_phase | grep "manually" | sed -e 's/manually corrected optimal phase = \([-0-9]*\).*/\1/'` echo -e "${OKPOS}${BRACKET}[ ${GOOD}PH 90/${SDRAMPHASE}${BRACKET} ]${NORMAL}" else fpcf -w 8 8 >/dev/null fpcf -phase -65 63 $FPGAPHASECORR > /var/log/fpga_sdram_phase if [ "$?" = 0 ]; then SDRAMPHASE=`cat /var/log/fpga_sdram_phase | grep "manually" | sed -e 's/manually corrected optimal phase = \([-0-9]*\).*/\1/'` echo -e "${OKPOS}${BRACKET}[ ${GOOD}PH 180/${SDRAMPHASE}${BRACKET} ]${NORMAL}" else fpcf -w 8 8 >/dev/null fpcf -phase -65 63 $FPGAPHASECORR > /var/log/fpga_sdram_phase if [ "$?" = 0 ]; then SDRAMPHASE=`cat /var/log/fpga_sdram_phase | grep "manually" | sed -e 's/manually corrected optimal phase = \([-0-9]*\).*/\1/'` echo -e "${OKPOS}${BRACKET}[ ${GOOD}PH 270/${SDRAMPHASE}${BRACKET} ]${NORMAL}" else echo -e "${FAILPOS}${BRACKET}[ ${BAD}fail${BRACKET} ]${NORMAL}" fi fi fi fi #worked with +10..+60 - ? #fpcf -phase -60 80 35 > /var/log/fpga_sdram_phase #end $? #begin "Writing Huffman tables from /etc/huffman.dat" #fpcf -table 200 /etc/huffman.dat >/dev/null #end $? #begin "Writing default JPEG header from /etc/header.jpeg" #cat /etc/header.jpeg >/dev/ccam_dma.raw #end $? #echo "writing precalculated gamma tables from /etc/gamma.dat" #fpcf -gamma /etc/gamma.dat begin "Turn on xtall output (12MHz) to FPGA" fpcf -X 3 12.0 >/dev/null end $? # set correction to 0 fpcf -w 46 0 >/dev/null #set microseconds to 0 fpcf -w 44 0 >/dev/null #set seconds to 0 fpcf -w 45 0 >/dev/null #for now - start here (on port 81) #lighttpd -f /etc/lighttpd.conf -m /lib #exit 0; #program 10347/10359 FPGA if it is not a sensor board SENSOR_FPGA="" #line below identifies CMOS sensor (10318, 10338) attached directly to 353. It is still possible # to have it connected through 10359 if [ $(( $(echo "0x`fpcf -r 74`") & 0x10000)) -ne 0 ] ; then #looking for additional boards connected to the sensor port (currently - 10347, 10359) begin "Looking for sensor FPGA" SENSOR_FPGA=`php -q /usr/html/bdetect.php` # SENSOR_FPGA="10359" if [ "$?" = 0 ]; then echo -e "${OKPOS}${BRACKET}[ ${GOOD}$SENSOR_FPGA${BRACKET} ]${NORMAL}" case "$SENSOR_FPGA" in '10347') #program 10347 sensor #turn off clcock to sensor board (float the pin) before configuring as x347 # fpcf -c 13 2 #already # set 14-bit input pixel data # fpcf -c 14 2 #//PXD14 - 1 - 14-bit data from sensor ##define X353DCR1__PXD14__BITNM 6 ##define X353DCR1__PXD14__WIDTH 1 fpcf -w 4f c0 >/dev/null # set PXD14 (14-bit mode) on # set pixel clock source to external # fpcf -c 18 2 #// source of pixel clock. Now 0 - internal (CLK1), 1,2,3 - external (bpf) ##define X353DCR1__PCLKSRC__BITNM 11 ##define X353DCR1__PCLKSRC__WIDTH 2 fpcf -w 4f 280 >/dev/null # set clock source to "01" - external begin "Programming 10347 board FPGA with $FPGA_10347_IMAGE" cat $FPGA_10347_IMAGE >/dev/sfpgaconfjtag end $? begin "initializing 10347 registers" php -q /usr/html/init347.php >/dev/null end $? #reset sensor DCM # fpcf -w 8 f0 # not really needed #not understood so far, was not needed with older software revision begin "running idle CCD acquisition" fpcf -i2cw16 1014 0 end $? #make it so that that state file reflects success/failure echo "$FPGA_10347_IMAGE" > /var/state/$SENSOR_FPGA echo "ctype=\"CCD\"" > /var/state/ctype ;; '10359') #program 10359 fpga begin "Programming 10359 board FPGA with $FPGA_10359_IMAGE" cat $FPGA_10359_IMAGE >/dev/sfpgaconfjtag end $? echo "$FPGA_10359_IMAGE" > /var/state/$SENSOR_FPGA #reenable clock to sensor # fpcf -c 13 1 fpcf -w 4f 20 >/dev/null # set clock from FPGA to sensor echo "Setting temporary mode resetting DMA/compressor when detecting sensor" fpcf -gwpx 3 1; # setting bit 0 - controls reset during sensordetect #define G_DEBUG (FRAMEPAR_GLOBALS + 2) /// Each bit turns on/off some debug outputs #define G_TEST_CTL_BITS (FRAMEPAR_GLOBALS + 3) /// turn some features on/off in the drivers for debuggin purposes fpcf -gwpd 11 3800 >/dev/null; # output delay in 10359 board (clock to out) in ps, signed ->1ffd0 (need 1ffec) #10359 FPFGA internal delays, may depend on bitstream (x359.bit) file: fpcf -gwpd 12 3902 >/dev/null; # delay in 10359 board sensor port 1 (clock to sensor - clock to DCM) in ps, fpcf -gwpd 13 3836 >/dev/null; # delay in 10359 board sensor port 2 (clock to sensor - clock to DCM) in ps, fpcf -gwpd 14 4122 >/dev/null; # delay in 10359 board sensor port 3 (clock to sensor - clock to DCM) in ps, #cable dealys - approximately 12-15ps/mm fpcf -gwpd 15 1800 >/dev/null; # cable delay in sensor port 1 in ps, signed (120mm cable) fpcf -gwpd 16 1800 >/dev/null; # cable delay in sensor port 2 in ps, signed (120mm cable) fpcf -gwpd 17 1800 >/dev/null; # cable delay in sensor port 3 in ps, signed (120mm cable) #define G_DLY359_OUT (FRAMEPAR_GLOBALS + 11) /// output delay in 10359 board (clock to out) in ps, signed #define G_DLY359_P1 (FRAMEPAR_GLOBALS + 12) /// delay in 10359 board sensor port 1 (clock to sensor - clock to DCM) in ps, signed #define G_DLY359_P2 (FRAMEPAR_GLOBALS + 13) /// delay in 10359 board sensor port 2 (clock to sensor - clock to DCM) in ps, signed #define G_DLY359_P3 (FRAMEPAR_GLOBALS + 14) /// delay in 10359 board sensor port 3 (clock to sensor - clock to DCM) in ps, signed #define G_DLY359_C1 (FRAMEPAR_GLOBALS + 15) /// cable delay in sensor port 1 in ps, signed #define G_DLY359_C2 (FRAMEPAR_GLOBALS + 16) /// cable delay in sensor port 2 in ps, signed #define G_DLY359_C3 (FRAMEPAR_GLOBALS + 17) /// cable delay in sensor port 3 in ps, signed # fpcf -gwpx 17 2 >/dev/null; # +1 - use system clock, +2 - delay i2c to 10359, +4 - send i2c to 10359 before sensor (after frame sync) fpcf -gwpx 17 0 >/dev/null; # +1 - use system clock, +2 - delay i2c to 10359, +4 - send i2c to 10359 before sensor (after frame sync) #define G_MULTI_CFG (FRAMEPAR_GLOBALS + 23) /// Additional configuration options for 10359 board. #define G_MULTI_CFG_SYSCLK 0 /// Bit 0 - use 10353 system clock, not the local one (as on 10359 rev 0) #define G_MULTI_CFG_DLYI2C 1 /// Bit 1 - delay 10359 i2c commands with respect to sesnor ones (in multi_pgm_window) #define G_MULTI_CFG_BEFORE 2 /// Bit 2 - send 10359 i2c commands first (to be sent after frame sync, 0 - sesnor commands first) #uncomment next line to use CMOS+10359 # echo "ctype=CMOS" > /var/state/ctype echo "ctype=\"10359\"" > /var/state/ctype ;; *) echo "**** Other FPGA-based sensor board (should not get here) ****" ;; esac else echo -e "${FAILPOS}${BRACKET}[ ${BAD}none${BRACKET} ]${NORMAL}" echo "ctype=\"NONE\"" > /var/state/ctype fi else begin "Some CMOS-based sensor board attached" echo -e "${OKPOS}${BRACKET}[ ${WARN}assuming 10338${BRACKET} ]${NORMAL}" #enable clock to sensor # fpcf -c 13 1 fpcf -w 4f 20 >/dev/null # set clock from FPGA to sensor # end 1 "assuming 10338" # . /etc/init.d/conf_353.sh echo "ctype=\"CMOS\"" > /var/state/ctype # echo "starting autocampars daemon: /usr/local/sbin/autocampars &" # /usr/local/sbin/autocampars & # echo "starting autoexposure daemon: /usr/local/sbin/autoexposure &" # /usr/local/sbin/autoexposure & # echo "initializing camera/sensor parameters: /usr/html/autocampars.php --init" # /usr/html/autocampars.php --init #last thing - trying to start 354 camera if code available (later will fix that # begin "trying model 354" # php -q /usr/html/init354.php # end $? fi #for now - start here (on port 81) #moved to /usr/local to be able to modify just it # /usr/local/sbin/lighttpd -f /etc/lighttpd.conf -m /usr/local/lib # begin "Everything in /etc/init.d/fpga is done" # end 0 if [ `fpcf -req_io` != 1 ]; then echo "Disabling FPGA I/O pins conrol as there is no 10369 I/O board" fpcf -w 70 aa000000 fi sync exit 0 README.md +13 −64 Original line number Original line Diff line number Diff line Loading @@ -8,71 +8,20 @@ This repository is created as a reference for simulation of image acquisition, p in the new NC393 camera that includes functionality of the previous one, so the same input image (on one of in the new NC393 camera that includes functionality of the previous one, so the same input image (on one of the 4 channels) should generate the same intermediate and final compressed files on both cameras. the 4 channels) should generate the same intermediate and final compressed files on both cameras. We will also try to make it possible to generate functional bitstream files compatible with the existing Project is modified to work with the current (and the last!) version of Xilinx ISE - 14.7, NC353 camera (so others will be able to modify their camera code with the current version of Xilinx tools), not tested enough, but the generated bitstream proved to be operational on just one camera. It is not yet safe but we are not there yet - ***this project is valid for simulation only!*** to replace the x353.bit camera unless you have experience in reflashing "bricked" camera as described in [http://wiki.elphel.com/index.php?title=Netboot_firmware_upgrade] as it is easy to accidentally make a camera non-bootable. Here is what makes it difficult: **NC353_TESTING** sub-directory contains description how to make such testing reasonably safe, together with the 'fpga' init script (automatically executed at boot time) that should be replaced in the camera file system. 1. Xilinx abandoned support for the older devices in the current software called "Vivado". **ISE_10_1_03_files** directory contains files from the original design that relied on ancient ISE 10.1.03. 2. Last verion of the ISE (it is ISE 14.7) can not use the older code "as is" 3. We were able to modify the Verilog code to be parsed by the current XST, but it does not recognize some statements in the *.xcf constraints file (I had to rename original *.ucf to *.xcf). 4. Attempt to try old parser (suggested by XST itself as the new parser is not the default for the Spartan 3e): ``` WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution for the specified device family. You are free to use it in order to take advantage of its enhanced HDL parsing/elaboration capabilities. However, please be aware that you may be impacted by language support differences. This version may also result in circuit performance and device utilization differences for your particular design. You can always revert back to the default XST solution by setting the "use_new_parser" option to value "no" on the XST command line or in the XST process properties panel. ``` also failed. After I added recommended options: ``` **ISE_14_7_results** includes log and results from the current tools run -use_new_parser no -ifn x353.prj -ofn x353.ngc -top x353 -p xc3s1200eft256 -uc x353.xcf -opt_mode speed -opt_level 1 ``` and ISE noticed that: You may follow instructions in the README.md for the [VDT plugin](https://github.com/Elphel/vdt-plugin) , just use this (x353) project instead of the eddr3 mentioned in the documentation. And you will need to use Xilinx ISE (not Xilinx Vivado) for this Spartan3e FPGA. ``` WARNING:Xst:1583 - You are using an internal switch '-use_new_parser'. ``` It still repeated the same WARNING:Xst:3152 (see above) disregarding its own suggestion. So we will need to find a way how to replace lines in the *xst file that cause errors in XST: ``` 204 TIMEGRP "CPU_ADDR" = pads("A<*>"); 205 TIMEGRP "CPU_ADDRCE" = "CPU_ADDR" pads("CE*"); 206 TIMEGRP "CPU_DATA" = pads("D<*>"); 207 TIMEGRP "WE" = pads("WE"); 208 TIMEGRP "OE" = pads("OE"); 209 TIMEGRP "DACK_PAD"= pads("DACK*"); 209 TIMEGRP "DREQ_PAD"= pads("DREQ*"); 210 TIMEGRP "ALLPADS"= pads("*"); ``` ``` ERROR:Xst:1888 - Processing TIMEGRP CPU_ADDR: User group 'pads("A<*>")' defined from other user group pattern not supported. ``` Even Google does not know what to do about this Xilinx XST feature: > No results found for "ERROR:Xst:1888". > > Results for ERROR:Xst:1888 (without quotes): > > ... So we'try to find other ways to re-formulate old timing constraints preserving the same meaning and try again to run tools. Until then I'll have to mention again ***this project is valid for simulation only!*** Update: Not yet tested with the real hardware, but the project was modified to work with ISE 14.7 (physical constraints were changed to parameters from the old style synthesis attributes, and the tools genereted a bitfile and even original timing constraints (after changing to uppercase) were met. Loading
NC353_TESTING/README.md 0 → 100644 +78 −0 Original line number Original line Diff line number Diff line Testing new generated bitstream images in Elphel NC353 cameras ============================================================== CAUTION: Replacing /etc/x353.bit bit file with the experimental one can make the camera hang, at it it will repeat each time you reboot the camera as the /etc/init.d/fpga script will attempt to use the same file again. Here is the modified version of this script - you may use ftp client to replace the original 'fpga' script: $ ftp 192.168.0.9 Connected to 192.168.0.9. 220 Elphel (R) Model 353 Camera release 8.2.16 (May 16 2015) ready. Name (192.168.0.9:user): root 331 User name okay, need password. Password: <pass> 230 User logged in, proceed. Remote system type is UNIX. Using binary mode to transfer files. ftp> cd /etc/init.d 250 Command successful. ftp> put fpga local: fpga remote: fpga 200 Command okay. 150 Opening data connection. 226 Transfer complete. 16251 bytes sent in 0.00 secs (453431.9 kB/s) ftp> exit 221 Goodbye. This is the modified part of the script: FPGA_ONE_TIME_IMAGE="/etc/x353_experimental.bit" FPGA_TMP_IMAGE="/var/tmp/x353_experimental.bit" if [ -f $FPGA_ONE_TIME_IMAGE ] ; then echo "Moving $FPGA_ONE_TIME_IMAGE to /var/tmp" mv $FPGA_ONE_TIME_IMAGE /var/tmp sync FPGA_IMAGE=$FPGA_TMP_IMAGE fi echo "For testing unsafe experimental bitsteam images:" echo "Name this file as $FPGA_ONE_TIME_IMAGE - it will be 'deleted before used'" echo "so next boot will use the original (safe) bitstream file" So regardless of success or failure of the testing of the experimental bitstream file it will be used only until the next reboot/power cycle. To test the new bitstream file you need to rename it to x353_experimental.bit and ftp to camera /etc directory (supposing you started from the local directory with the x353_experimental.bit file: $ ftp 192.168.0.9 Connected to 192.168.0.9. 220 Elphel (R) Model 353 Camera release 8.2.16 (May 16 2015) ready. Name (192.168.0.9:user): root 331 User name okay, need password. Password: <pass> 230 User logged in, proceed. Remote system type is UNIX. Using binary mode to transfer files. ftp> put x353_experimental.bit local: x353_experimental.bit remote: x353_experimental.bit 200 Command okay. 150 Opening data connection. 226 Transfer complete. 480220 bytes sent in 1.45 secs (324.2 kB/s) ftp> exit 221 Goodbye. A sample bitstream file is in the ISE_14_7_results directory, with the default project settings the new generated bitstream files will be in the ise_results subdirectory. It is a good idea to telnet to the camera and issue a 'sync' command (equivalent to the "safely remove" for the flash cards). Or just open [http://<your_camera_ip>/phpshell.php?command=sync] in the browser. Good hacking! Elphel team No newline at end of file
NC353_TESTING/fpga 0 → 100755 +407 −0 Original line number Original line Diff line number Diff line #!/bin/sh #******************************************************************************** # FILE NAME : fpga # DESCRIPTION: fpgas configuration script # Copyright (C) 2012 Elphel, Inc # -----------------------------------------------------------------------------** # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation, either version 3 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # The four essential freedoms with GNU GPL software: # * the freedom to run the program for any purpose # * the freedom to study how the program works and change it to make it do what you wish # * the freedom to redistribute copies so you can help your neighbor # * the freedom to distribute copies of your modified versions to others # # You should have received a copy of the GNU General Public License # along with this program. If not, see <http://www.gnu.org/licenses/>. # -----------------------------------------------------------------------------** . /etc/init.d/functions.sh FPGA_IMAGE="/etc/x353.bit" FPGA_10359_IMAGE="/etc/x359.bit" FPGA_10347_IMAGE="/etc/x347.bit" FPGAFREQ=160 CABLECORR=450 #ps for 30 mm cable to sensor (or 10359 board, 10359-> sensor cables are set lower) ~15ps/mm, increase for longer cables. delete /etc/autocampars.xml to use new values. FPGA_ONE_TIME_IMAGE="/etc/x353_experimental.bit" FPGA_TMP_IMAGE="/var/tmp/x353_experimental.bit" if [ -f $FPGA_ONE_TIME_IMAGE ] ; then echo "Moving $FPGA_ONE_TIME_IMAGE to /var/tmp" mv $FPGA_ONE_TIME_IMAGE /var/tmp sync FPGA_IMAGE=$FPGA_TMP_IMAGE fi echo "For testing unsafe experimental bitsteam images:" echo "Name this file as $FPGA_ONE_TIME_IMAGE - it will be 'deleted before used'" echo "so next boot will use the original (safe) bitstream file" # if it was just after "init 3" from "init 4", flash was not mounted if [ ! -n "`mount | grep /mnt/flash`" ] ; then begin "Mounting /dev/part/rwfsblock as /mnt/flash" mount -t jffs2 /dev/part/rwfsblock /mnt/flash end $? fi fpcf -gwpd 7 $CABLECORR >/dev/null; ## Uncomment the next line to use system clock for the 10359-connected sensors. When commented - local (to 10359) oscillator is used #fpcf -gwpd 23 1 >/dev/null; # disable on-board clock generator - mooved to 10359 branch below #fpcf -gwpx 2 10000 >/dev/null; #debug mask #fpcf -gwpx 2 2000019 >/dev/null; #debug mask for troubleshooting startup with less sensors #fpcf -gwpx 2 A >/dev/null; #debug mask #fpcf -gwpx 2 B >/dev/null; #debug mask #fpcf -gwpx 2 8 >/dev/null; #debug mask #fpcf -gwpx 2 1000000 >/dev/null; #debug mask for SDRAM phase debug #echo "killall klogd" #killall klogd #echo "sleep 5" #sleep 5 #echo "echo 1 > /proc/sys/kernel/printk" #echo 1 > /proc/sys/kernel/printk #echo "cat /proc/kmsg >/var/html/klog.txt" #cat /proc/kmsg >/var/html/klog.txt & #fpcf -gwpx 2 48 >/dev/null; #debug mask #fpcf -gwpx 2 148 >/dev/null; #debug mask #fpcf -gwpx 2 14c >/dev/null; #debug mask #fpcf -gwpx 2 8 >/dev/null; #debug mask #fpcf -gwpx 2 14c >/dev/null; #debug mask FPGAPHASECORR=-8; # 0353301b: -44/+28 begin "Setting FPGA master clock to $FPGAFREQ MHz" fpcf -X 0 $FPGAFREQ >/dev/null end $? begin "Programming FPGA with $FPGA_IMAGE" cat $FPGA_IMAGE >/dev/fpgaconfjtag end $? # later will make default FPGA code not to turn on sensor clock at startup # turn off clcock to sensor board (float the pin) before configuring as x347 - with the clock long sensor cable does not work # it induces signal on "run" output of FPGA # fpcf -c 13 2 # #define X353DCR1__DCLKMODE__BITNM 4 # #define X313_WA_DCR1 0x4f fpcf -w 4f 30 >/dev/null # set clock from sensor (safe) begin "Loaded FPGA rev" FPGA_REV=`fpcf -r 13` if [ "$?" = 0 ]; then echo -e "${OKPOS}${BRACKET}[ ${GOOD}$FPGA_REV${BRACKET} ]${NORMAL}" else echo -e "${FAILPOS}${BRACKET}[ ${BAD}fail${BRACKET} ]${NORMAL}" fi case "$FPGA_REV" in '3534017') FPGAPHASECORR=-4; # # fpcf -gwpd 8 2580 >/dev/null; #2580 ps # fpcf -gwpd 8 1620 >/dev/null; #1620 ps -17E # fpcf -gwpd 8 3500 >/dev/null; measured , Xilinx 4824 fpcf -gwpd 8 1620 >/dev/null; #1793 ps -17D - from Xilinx (x1.38) ;; '3534018') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3500 >/dev/null; # fpcf -gwpd 8 2950 >/dev/null; #3615 ps -18D (C?) - from Xilinx (x1.225) # fpcf -gwpd 8 1400 >/dev/null; #1464 ps -18D - from Xilinx (x1.225) fpcf -gwpd 8 2940 >/dev/null; #3864 ps -18F (x1.314) ;; '3534019') FPGAPHASECORR=-4; # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401a') FPGAPHASECORR=-4; # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401b') FPGAPHASECORR=-4; # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401c') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401d') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401e') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '353401f') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '3534020') FPGAPHASECORR=-4; # # fpcf -gwpd 8 3556 >/dev/null; #4004 - 19 (x1.125) ;; '3534021') FPGAPHASECORR=-2; # fpcf -gwpd 8 1587 >/dev/null; #1.587 ns, sensor phase 0xffcc ;; '3534022') FPGAPHASECORR=-2; # fpcf -gwpd 8 3724 >/dev/null; #sen sensor phase ff84 ;; '3534024') FPGAPHASECORR=-2; # fpcf -gwpd 8 1932 >/dev/null; #sensor phase fff0 (decreased by 450ps of the cable) ;; '3534025') FPGAPHASECORR=-2; # fpcf -gwpd 8 1160 >/dev/null; #sensor phase 0xffcd ;; '353402a') FPGAPHASECORR=-9; # fpcf -gwpd 8 1160 >/dev/null; #sensor phase 0xffcd ;; '353402b') FPGAPHASECORR=-9; # fpcf -gwpd 8 1160 >/dev/null; #sensor phase 0xffcd ;; *) echo "**** Unknown FPGA revision ****" FPGAPHASECORR=-1; # does not work with "0" !!! (No "manually corrected") echo "Setting phase correction - always needed fro the new FPGA image." echo "Procedure to set the correct shift:" echo "1 - manually set the phase with " echo "fpcf -phase -65 63 <phase_correction_value>" echo " # setting 90-degrees with fpcf -w 8 c; repeating fpcf -w 8 8 as needed" echo "# 2 - test SDRAM, whatch for errors" echo "# 3 - find margins for the phase_correction_value (repeating steps 1 and 2), select average between low and high ones" echo "# 4 - update code below" ;; esac # Setting phase correction - always needed fro the new FPGA image. # Procedure to set the correct shift: # 1 - manually set the phase with # fpcf -phase -65 63 <phase_correction_value> # setting 90-degrees with fpcf -w 8 c; repeating fpcf -w 8 8 as needed # 2 - test SDRAM, whatch for errors # 3 - find margins for the phase_correction_value (repeating steps 1 and 2), select average between low and high ones # 4 - update code below begin "Adjusting DDR SDRAM clock phase" fpcf -phase -65 63 $FPGAPHASECORR > /var/log/fpga_sdram_phase # for 3533017 @ 160MHz (one failed at 69) if [ "$?" = 0 ]; then SDRAMPHASE=`cat /var/log/fpga_sdram_phase | grep "manually" | sed -e 's/manually corrected optimal phase = \([-0-9]*\).*/\1/'` echo -e "${OKPOS}${BRACKET}[ ${GOOD}PH 0/${SDRAMPHASE}${BRACKET} ]${NORMAL}" else fpcf -w 8 8 >/dev/null fpcf -phase -65 63 $FPGAPHASECORR > /var/log/fpga_sdram_phase if [ "$?" = 0 ]; then SDRAMPHASE=`cat /var/log/fpga_sdram_phase | grep "manually" | sed -e 's/manually corrected optimal phase = \([-0-9]*\).*/\1/'` echo -e "${OKPOS}${BRACKET}[ ${GOOD}PH 90/${SDRAMPHASE}${BRACKET} ]${NORMAL}" else fpcf -w 8 8 >/dev/null fpcf -phase -65 63 $FPGAPHASECORR > /var/log/fpga_sdram_phase if [ "$?" = 0 ]; then SDRAMPHASE=`cat /var/log/fpga_sdram_phase | grep "manually" | sed -e 's/manually corrected optimal phase = \([-0-9]*\).*/\1/'` echo -e "${OKPOS}${BRACKET}[ ${GOOD}PH 180/${SDRAMPHASE}${BRACKET} ]${NORMAL}" else fpcf -w 8 8 >/dev/null fpcf -phase -65 63 $FPGAPHASECORR > /var/log/fpga_sdram_phase if [ "$?" = 0 ]; then SDRAMPHASE=`cat /var/log/fpga_sdram_phase | grep "manually" | sed -e 's/manually corrected optimal phase = \([-0-9]*\).*/\1/'` echo -e "${OKPOS}${BRACKET}[ ${GOOD}PH 270/${SDRAMPHASE}${BRACKET} ]${NORMAL}" else echo -e "${FAILPOS}${BRACKET}[ ${BAD}fail${BRACKET} ]${NORMAL}" fi fi fi fi #worked with +10..+60 - ? #fpcf -phase -60 80 35 > /var/log/fpga_sdram_phase #end $? #begin "Writing Huffman tables from /etc/huffman.dat" #fpcf -table 200 /etc/huffman.dat >/dev/null #end $? #begin "Writing default JPEG header from /etc/header.jpeg" #cat /etc/header.jpeg >/dev/ccam_dma.raw #end $? #echo "writing precalculated gamma tables from /etc/gamma.dat" #fpcf -gamma /etc/gamma.dat begin "Turn on xtall output (12MHz) to FPGA" fpcf -X 3 12.0 >/dev/null end $? # set correction to 0 fpcf -w 46 0 >/dev/null #set microseconds to 0 fpcf -w 44 0 >/dev/null #set seconds to 0 fpcf -w 45 0 >/dev/null #for now - start here (on port 81) #lighttpd -f /etc/lighttpd.conf -m /lib #exit 0; #program 10347/10359 FPGA if it is not a sensor board SENSOR_FPGA="" #line below identifies CMOS sensor (10318, 10338) attached directly to 353. It is still possible # to have it connected through 10359 if [ $(( $(echo "0x`fpcf -r 74`") & 0x10000)) -ne 0 ] ; then #looking for additional boards connected to the sensor port (currently - 10347, 10359) begin "Looking for sensor FPGA" SENSOR_FPGA=`php -q /usr/html/bdetect.php` # SENSOR_FPGA="10359" if [ "$?" = 0 ]; then echo -e "${OKPOS}${BRACKET}[ ${GOOD}$SENSOR_FPGA${BRACKET} ]${NORMAL}" case "$SENSOR_FPGA" in '10347') #program 10347 sensor #turn off clcock to sensor board (float the pin) before configuring as x347 # fpcf -c 13 2 #already # set 14-bit input pixel data # fpcf -c 14 2 #//PXD14 - 1 - 14-bit data from sensor ##define X353DCR1__PXD14__BITNM 6 ##define X353DCR1__PXD14__WIDTH 1 fpcf -w 4f c0 >/dev/null # set PXD14 (14-bit mode) on # set pixel clock source to external # fpcf -c 18 2 #// source of pixel clock. Now 0 - internal (CLK1), 1,2,3 - external (bpf) ##define X353DCR1__PCLKSRC__BITNM 11 ##define X353DCR1__PCLKSRC__WIDTH 2 fpcf -w 4f 280 >/dev/null # set clock source to "01" - external begin "Programming 10347 board FPGA with $FPGA_10347_IMAGE" cat $FPGA_10347_IMAGE >/dev/sfpgaconfjtag end $? begin "initializing 10347 registers" php -q /usr/html/init347.php >/dev/null end $? #reset sensor DCM # fpcf -w 8 f0 # not really needed #not understood so far, was not needed with older software revision begin "running idle CCD acquisition" fpcf -i2cw16 1014 0 end $? #make it so that that state file reflects success/failure echo "$FPGA_10347_IMAGE" > /var/state/$SENSOR_FPGA echo "ctype=\"CCD\"" > /var/state/ctype ;; '10359') #program 10359 fpga begin "Programming 10359 board FPGA with $FPGA_10359_IMAGE" cat $FPGA_10359_IMAGE >/dev/sfpgaconfjtag end $? echo "$FPGA_10359_IMAGE" > /var/state/$SENSOR_FPGA #reenable clock to sensor # fpcf -c 13 1 fpcf -w 4f 20 >/dev/null # set clock from FPGA to sensor echo "Setting temporary mode resetting DMA/compressor when detecting sensor" fpcf -gwpx 3 1; # setting bit 0 - controls reset during sensordetect #define G_DEBUG (FRAMEPAR_GLOBALS + 2) /// Each bit turns on/off some debug outputs #define G_TEST_CTL_BITS (FRAMEPAR_GLOBALS + 3) /// turn some features on/off in the drivers for debuggin purposes fpcf -gwpd 11 3800 >/dev/null; # output delay in 10359 board (clock to out) in ps, signed ->1ffd0 (need 1ffec) #10359 FPFGA internal delays, may depend on bitstream (x359.bit) file: fpcf -gwpd 12 3902 >/dev/null; # delay in 10359 board sensor port 1 (clock to sensor - clock to DCM) in ps, fpcf -gwpd 13 3836 >/dev/null; # delay in 10359 board sensor port 2 (clock to sensor - clock to DCM) in ps, fpcf -gwpd 14 4122 >/dev/null; # delay in 10359 board sensor port 3 (clock to sensor - clock to DCM) in ps, #cable dealys - approximately 12-15ps/mm fpcf -gwpd 15 1800 >/dev/null; # cable delay in sensor port 1 in ps, signed (120mm cable) fpcf -gwpd 16 1800 >/dev/null; # cable delay in sensor port 2 in ps, signed (120mm cable) fpcf -gwpd 17 1800 >/dev/null; # cable delay in sensor port 3 in ps, signed (120mm cable) #define G_DLY359_OUT (FRAMEPAR_GLOBALS + 11) /// output delay in 10359 board (clock to out) in ps, signed #define G_DLY359_P1 (FRAMEPAR_GLOBALS + 12) /// delay in 10359 board sensor port 1 (clock to sensor - clock to DCM) in ps, signed #define G_DLY359_P2 (FRAMEPAR_GLOBALS + 13) /// delay in 10359 board sensor port 2 (clock to sensor - clock to DCM) in ps, signed #define G_DLY359_P3 (FRAMEPAR_GLOBALS + 14) /// delay in 10359 board sensor port 3 (clock to sensor - clock to DCM) in ps, signed #define G_DLY359_C1 (FRAMEPAR_GLOBALS + 15) /// cable delay in sensor port 1 in ps, signed #define G_DLY359_C2 (FRAMEPAR_GLOBALS + 16) /// cable delay in sensor port 2 in ps, signed #define G_DLY359_C3 (FRAMEPAR_GLOBALS + 17) /// cable delay in sensor port 3 in ps, signed # fpcf -gwpx 17 2 >/dev/null; # +1 - use system clock, +2 - delay i2c to 10359, +4 - send i2c to 10359 before sensor (after frame sync) fpcf -gwpx 17 0 >/dev/null; # +1 - use system clock, +2 - delay i2c to 10359, +4 - send i2c to 10359 before sensor (after frame sync) #define G_MULTI_CFG (FRAMEPAR_GLOBALS + 23) /// Additional configuration options for 10359 board. #define G_MULTI_CFG_SYSCLK 0 /// Bit 0 - use 10353 system clock, not the local one (as on 10359 rev 0) #define G_MULTI_CFG_DLYI2C 1 /// Bit 1 - delay 10359 i2c commands with respect to sesnor ones (in multi_pgm_window) #define G_MULTI_CFG_BEFORE 2 /// Bit 2 - send 10359 i2c commands first (to be sent after frame sync, 0 - sesnor commands first) #uncomment next line to use CMOS+10359 # echo "ctype=CMOS" > /var/state/ctype echo "ctype=\"10359\"" > /var/state/ctype ;; *) echo "**** Other FPGA-based sensor board (should not get here) ****" ;; esac else echo -e "${FAILPOS}${BRACKET}[ ${BAD}none${BRACKET} ]${NORMAL}" echo "ctype=\"NONE\"" > /var/state/ctype fi else begin "Some CMOS-based sensor board attached" echo -e "${OKPOS}${BRACKET}[ ${WARN}assuming 10338${BRACKET} ]${NORMAL}" #enable clock to sensor # fpcf -c 13 1 fpcf -w 4f 20 >/dev/null # set clock from FPGA to sensor # end 1 "assuming 10338" # . /etc/init.d/conf_353.sh echo "ctype=\"CMOS\"" > /var/state/ctype # echo "starting autocampars daemon: /usr/local/sbin/autocampars &" # /usr/local/sbin/autocampars & # echo "starting autoexposure daemon: /usr/local/sbin/autoexposure &" # /usr/local/sbin/autoexposure & # echo "initializing camera/sensor parameters: /usr/html/autocampars.php --init" # /usr/html/autocampars.php --init #last thing - trying to start 354 camera if code available (later will fix that # begin "trying model 354" # php -q /usr/html/init354.php # end $? fi #for now - start here (on port 81) #moved to /usr/local to be able to modify just it # /usr/local/sbin/lighttpd -f /etc/lighttpd.conf -m /usr/local/lib # begin "Everything in /etc/init.d/fpga is done" # end 0 if [ `fpcf -req_io` != 1 ]; then echo "Disabling FPGA I/O pins conrol as there is no 10369 I/O board" fpcf -w 70 aa000000 fi sync exit 0
README.md +13 −64 Original line number Original line Diff line number Diff line Loading @@ -8,71 +8,20 @@ This repository is created as a reference for simulation of image acquisition, p in the new NC393 camera that includes functionality of the previous one, so the same input image (on one of in the new NC393 camera that includes functionality of the previous one, so the same input image (on one of the 4 channels) should generate the same intermediate and final compressed files on both cameras. the 4 channels) should generate the same intermediate and final compressed files on both cameras. We will also try to make it possible to generate functional bitstream files compatible with the existing Project is modified to work with the current (and the last!) version of Xilinx ISE - 14.7, NC353 camera (so others will be able to modify their camera code with the current version of Xilinx tools), not tested enough, but the generated bitstream proved to be operational on just one camera. It is not yet safe but we are not there yet - ***this project is valid for simulation only!*** to replace the x353.bit camera unless you have experience in reflashing "bricked" camera as described in [http://wiki.elphel.com/index.php?title=Netboot_firmware_upgrade] as it is easy to accidentally make a camera non-bootable. Here is what makes it difficult: **NC353_TESTING** sub-directory contains description how to make such testing reasonably safe, together with the 'fpga' init script (automatically executed at boot time) that should be replaced in the camera file system. 1. Xilinx abandoned support for the older devices in the current software called "Vivado". **ISE_10_1_03_files** directory contains files from the original design that relied on ancient ISE 10.1.03. 2. Last verion of the ISE (it is ISE 14.7) can not use the older code "as is" 3. We were able to modify the Verilog code to be parsed by the current XST, but it does not recognize some statements in the *.xcf constraints file (I had to rename original *.ucf to *.xcf). 4. Attempt to try old parser (suggested by XST itself as the new parser is not the default for the Spartan 3e): ``` WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution for the specified device family. You are free to use it in order to take advantage of its enhanced HDL parsing/elaboration capabilities. However, please be aware that you may be impacted by language support differences. This version may also result in circuit performance and device utilization differences for your particular design. You can always revert back to the default XST solution by setting the "use_new_parser" option to value "no" on the XST command line or in the XST process properties panel. ``` also failed. After I added recommended options: ``` **ISE_14_7_results** includes log and results from the current tools run -use_new_parser no -ifn x353.prj -ofn x353.ngc -top x353 -p xc3s1200eft256 -uc x353.xcf -opt_mode speed -opt_level 1 ``` and ISE noticed that: You may follow instructions in the README.md for the [VDT plugin](https://github.com/Elphel/vdt-plugin) , just use this (x353) project instead of the eddr3 mentioned in the documentation. And you will need to use Xilinx ISE (not Xilinx Vivado) for this Spartan3e FPGA. ``` WARNING:Xst:1583 - You are using an internal switch '-use_new_parser'. ``` It still repeated the same WARNING:Xst:3152 (see above) disregarding its own suggestion. So we will need to find a way how to replace lines in the *xst file that cause errors in XST: ``` 204 TIMEGRP "CPU_ADDR" = pads("A<*>"); 205 TIMEGRP "CPU_ADDRCE" = "CPU_ADDR" pads("CE*"); 206 TIMEGRP "CPU_DATA" = pads("D<*>"); 207 TIMEGRP "WE" = pads("WE"); 208 TIMEGRP "OE" = pads("OE"); 209 TIMEGRP "DACK_PAD"= pads("DACK*"); 209 TIMEGRP "DREQ_PAD"= pads("DREQ*"); 210 TIMEGRP "ALLPADS"= pads("*"); ``` ``` ERROR:Xst:1888 - Processing TIMEGRP CPU_ADDR: User group 'pads("A<*>")' defined from other user group pattern not supported. ``` Even Google does not know what to do about this Xilinx XST feature: > No results found for "ERROR:Xst:1888". > > Results for ERROR:Xst:1888 (without quotes): > > ... So we'try to find other ways to re-formulate old timing constraints preserving the same meaning and try again to run tools. Until then I'll have to mention again ***this project is valid for simulation only!*** Update: Not yet tested with the real hardware, but the project was modified to work with ISE 14.7 (physical constraints were changed to parameters from the old style synthesis attributes, and the tools genereted a bitfile and even original timing constraints (after changing to uppercase) were met.
