Loading .settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +6 −0 Original line number Diff line number Diff line FPGA_project_0_SimulationTopFile=x353_1.tf FPGA_project_1_SimulationTopModule=testbench353 FPGA_project_2_ImplementationTopFile=x353.v FPGA_project_4_part=xc3s1200eft256-4 com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_4_part<-@\#\#@-> eclipse.preferences.version=1 .settings/com.elphel.vdt.ISEMap.prefs 0 → 100644 +5 −0 Original line number Diff line number Diff line ISEMap_131_cover_mode=speed ISEMap_141_overall_effor_level=high ISEMap_96_speed_grade=4 com.elphel.store.context.ISEMap=ISEMap_96_speed_grade<-@\#\#@->ISEMap_131_cover_mode<-@\#\#@->ISEMap_141_overall_effor_level<-@\#\#@-> eclipse.preferences.version=1 .settings/com.elphel.vdt.ISENGDBuild.prefs 0 → 100644 +3 −0 Original line number Diff line number Diff line ISENGDBuild_96_speed_grade=4 com.elphel.store.context.ISENGDBuild=ISENGDBuild_96_speed_grade<-@\#\#@-> eclipse.preferences.version=1 .settings/com.elphel.vdt.ISEPAR.prefs 0 → 100644 +3 −0 Original line number Diff line number Diff line ISEPAR_96_speed_grade=4 com.elphel.store.context.ISEPAR=ISEPAR_96_speed_grade<-@\#\#@-> eclipse.preferences.version=1 .settings/com.elphel.vdt.ISEPartgen.prefs 0 → 100644 +7 −0 Original line number Diff line number Diff line ISEPartgen_123_p_option=false ISEPartgen_124_v_option=true ISEPartgen_127_info=false ISEPartgen_129_useRedirect=false ISEPartgen_96_speed_grade=4 com.elphel.store.context.ISEPartgen=ISEPartgen_123_p_option<-@\#\#@->ISEPartgen_124_v_option<-@\#\#@->ISEPartgen_127_info<-@\#\#@->ISEPartgen_129_useRedirect<-@\#\#@->ISEPartgen_96_speed_grade<-@\#\#@-> eclipse.preferences.version=1 Loading
.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +6 −0 Original line number Diff line number Diff line FPGA_project_0_SimulationTopFile=x353_1.tf FPGA_project_1_SimulationTopModule=testbench353 FPGA_project_2_ImplementationTopFile=x353.v FPGA_project_4_part=xc3s1200eft256-4 com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_4_part<-@\#\#@-> eclipse.preferences.version=1
.settings/com.elphel.vdt.ISEMap.prefs 0 → 100644 +5 −0 Original line number Diff line number Diff line ISEMap_131_cover_mode=speed ISEMap_141_overall_effor_level=high ISEMap_96_speed_grade=4 com.elphel.store.context.ISEMap=ISEMap_96_speed_grade<-@\#\#@->ISEMap_131_cover_mode<-@\#\#@->ISEMap_141_overall_effor_level<-@\#\#@-> eclipse.preferences.version=1
.settings/com.elphel.vdt.ISENGDBuild.prefs 0 → 100644 +3 −0 Original line number Diff line number Diff line ISENGDBuild_96_speed_grade=4 com.elphel.store.context.ISENGDBuild=ISENGDBuild_96_speed_grade<-@\#\#@-> eclipse.preferences.version=1
.settings/com.elphel.vdt.ISEPAR.prefs 0 → 100644 +3 −0 Original line number Diff line number Diff line ISEPAR_96_speed_grade=4 com.elphel.store.context.ISEPAR=ISEPAR_96_speed_grade<-@\#\#@-> eclipse.preferences.version=1
.settings/com.elphel.vdt.ISEPartgen.prefs 0 → 100644 +7 −0 Original line number Diff line number Diff line ISEPartgen_123_p_option=false ISEPartgen_124_v_option=true ISEPartgen_127_info=false ISEPartgen_129_useRedirect=false ISEPartgen_96_speed_grade=4 com.elphel.store.context.ISEPartgen=ISEPartgen_123_p_option<-@\#\#@->ISEPartgen_124_v_option<-@\#\#@->ISEPartgen_127_info<-@\#\#@->ISEPartgen_129_useRedirect<-@\#\#@->ISEPartgen_96_speed_grade<-@\#\#@-> eclipse.preferences.version=1