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Andrey Filippov authored06425a7a
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SimpleSamples | ||
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Xilinx | ||
BasicInterface.xml | ||
DesignMenu.xml | ||
FPGA_project.xml | ||
Installation.xml | ||
vdt_test.xml |
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Verilog | Loading commit data... | |
Xilinx | Loading commit data... | |
BasicInterface.xml | Loading commit data... | |
DesignMenu.xml | Loading commit data... | |
FPGA_project.xml | Loading commit data... | |
Installation.xml | Loading commit data... | |
vdt_test.xml | Loading commit data... |