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Andrey Filippov authoredimplemented some parsing of the ISE output
16c5f208
| Name |
Last commit
|
Last update |
|---|---|---|
| .. | ||
| SimpleSamples | ||
| Verilog | ||
| Xilinx_ISE | ||
| Xilinx_Vivado | ||
| BasicInterface.xml | ||
| DesignMenu.xml | ||
| FPGA_project.xml | ||
| Installation.xml | ||
| vdt_test.xml |
implemented some parsing of the ISE output
| Name |
Last commit
|
Last update |
|---|---|---|
| .. | ||
| SimpleSamples | ||
| Verilog | ||
| Xilinx_ISE | ||
| Xilinx_Vivado | ||
| BasicInterface.xml | ||
| DesignMenu.xml | ||
| FPGA_project.xml | ||
| Installation.xml | ||
| vdt_test.xml |