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Andrey Filippov authoredupdated in dialogs. Left some conditioned debug output behind.
1849246a
| Name |
Last commit
|
Last update |
|---|---|---|
| .. | ||
| SimpleSamples | ||
| Verilog | ||
| Xilinx | ||
| BasicInterface.xml | ||
| DesignMenu.xml | ||
| FPGA_project.xml | ||
| Installation.xml |
updated in dialogs. Left some conditioned debug output behind.
| Name |
Last commit
|
Last update |
|---|---|---|
| .. | ||
| SimpleSamples | ||
| Verilog | ||
| Xilinx | ||
| BasicInterface.xml | ||
| DesignMenu.xml | ||
| FPGA_project.xml | ||
| Installation.xml |