Added GPLv3 Verilog file template

templates/verilog.xml

@@ -140,4 +140,43 @@ endmodule
 
 </template>
 
+<template
+    autoinsert="false"
+    context="com.elphel.vdt.veditor.templates.verilog.context.newfile"
+    deleted="false"
+    description="This is a special template that is used to create new files."
+    enabled="true"
+    id="com.elphel.vdt.veditor.templates.verilog.newFile.GPL"
+    name="Verilog GPL File"
+>/*******************************************************************************
+ * Module: ${modulename}
+ * Date:${year}-${month}-${day}  
+ * Author: ${user}     
+ * Description: ${brief}
+ *
+ * Copyright (c) ${year} &lt;set up in Preferences-Verilog/VHDL Editor-Templates&gt; .
+ * ${modulename}.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  ${modulename}.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see &lt;http://www.gnu.org/licenses/&gt; .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  ${modulename}(
+);
+
+
+endmodule
+
+</template>
+
+
 </templates>