Commit b11069c2 authored by Andrey Filippov's avatar Andrey Filippov

fixed template

parent f64ed7ee
...@@ -148,7 +148,7 @@ endmodule ...@@ -148,7 +148,7 @@ endmodule
enabled="true" enabled="true"
id="com.elphel.vdt.veditor.templates.verilog.newFile.GPL" id="com.elphel.vdt.veditor.templates.verilog.newFile.GPL"
name="Verilog GPL File" name="Verilog GPL File"
>/! >/*!
* <b>Module:</b> ${modulename} * <b>Module:</b> ${modulename}
* @file ${modulename}.v * @file ${modulename}.v
* @date ${year}-${month}-${day} * @date ${year}-${month}-${day}
......
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