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Elphel
vdt-plugin
Commits
a3c8f614
Commit
a3c8f614
authored
Feb 01, 2014
by
Andrey Filippov
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Plain Diff
Added Vivado , removed some old tools
parent
b6bfc326
Changes
12
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12 changed files
with
71 additions
and
1414 deletions
+71
-1414
BasicInterface.xml
tools/BasicInterface.xml
+4
-0
DesignMenu.xml
tools/DesignMenu.xml
+35
-74
FPGA_project.xml
tools/FPGA_project.xml
+26
-7
Remote.xml
tools/SimpleSamples/Remote.xml
+1
-1
Tools.xml
tools/SimpleSamples/Tools.xml
+3
-3
CVer.xml.broken
tools/Verilog/CVer.xml.broken
+0
-0
IVerilog.xml
tools/Verilog/IVerilog.xml
+2
-2
IVerilogDebug.xml
tools/Verilog/IVerilogDebug.xml
+0
-370
ModelSIM.xml.broken
tools/Verilog/ModelSIM.xml.broken
+0
-0
XST.xml.broken
tools/Verilog/XST.xml.broken
+0
-0
XDS.xml
tools/XDS/XDS.xml
+0
-957
vivado.xml.do_not_use
tools/Xilinx/vivado.xml.do_not_use
+0
-0
No files found.
tools/BasicInterface.xml
View file @
a3c8f614
...
...
@@ -6,6 +6,10 @@
<interface
name =
"BasicInterface"
>
<!-- Basic types -->
<typedef
name =
"Boolean"
>
<paramtype
kind=
"bool"
formatTrue=
"true"
formatFalse=
"false"
/>
</typedef>
<typedef
name =
"BoolYesNo"
>
<paramtype
kind=
"bool"
formatTrue=
"YES"
formatFalse=
"NO"
/>
</typedef>
...
...
tools/DesignMenu.xml
View file @
a3c8f614
...
...
@@ -9,37 +9,20 @@
<menu
name=
"Verilog"
label=
"Verilog Development Tools"
icon=
"newmod_wiz.gif"
>
<menuitem
name=
"cver"
label=
"CVer simulator"
icon=
"cver.gif"
call=
"cver"
/>
<menuitem
name=
"modelsim"
label=
"ModelSIM simulator"
icon=
"modelsim.gif"
call=
"ModelSIM"
/>
<menuitem
name=
"xst"
label=
"XST (Synthesis)"
icon=
"xst.gif"
call=
"XST"
/>
<menuitem
name=
"IVerilog"
label=
"Icarus Verilog Simulator"
icon=
"iverilog.ico"
call=
"iverilog"
/>
<menuitem
name=
"IVerilog Debug"
label=
"Icarus Verilog (Debugging TSL)"
icon=
"iverilog.ico"
call=
"iverilog_dbg"
/>
<menuitem
name=
"GTKWave"
label=
"GTKWave (Waves viewer)"
icon=
"gtkwave.ico"
call=
"iverilog"
/>
</menu>
<menu
name=
"Python tests"
label=
"Tests with remote Python console"
icon=
"python.png"
>
<menuitem
name=
"RemotePython"
label=
"Run remote Python session"
icon=
"python.png"
...
...
@@ -48,8 +31,11 @@
label=
"Send a command to the remote Python session"
icon=
"my_tool.gif"
call=
"RemotePythonCommand"
/>
<menuitem
name=
"Vivado"
</menu>
<menu
name=
"Vivado"
label=
"Vivado Tools"
icon=
"xilinx.png"
>
<menuitem
name=
"Vivado Server"
label=
"Run remote Vivado session"
icon=
"xilinx.png"
call=
"Vivado"
/>
...
...
@@ -57,41 +43,18 @@
label=
"Send a command to the remote Vivado session"
icon=
"my_tool.gif"
call=
"VivadoTest"
/>
<menuitem
name=
"Vivado
LoadSource
"
label=
"
Load source files to Vivado
"
<menuitem
name=
"Vivado
Synthesis
"
label=
"
Run Vivado synthesis
"
icon=
"xilinx.png"
call=
"VivadoLoadSource"
/>
<menu
name=
"XDS"
label=
"Demo XDS Tools"
icon=
"xds.gif"
>
<menu
name=
"menuXC"
label=
"Native Complilation"
icon=
"xds.gif"
>
<menuitem
name=
"toolXDS-XC"
label=
"Run XDS Native Compiler"
icon=
"xds.gif"
call=
"toolXDS-XC"
/>
call=
"VivadoSynthesis"
/>
</menu>
<menu
name=
"menuXM"
label=
"Via C Complilation"
icon=
"xds.gif"
>
<menuitem
name=
"toolXDS-XM"
label=
"Run XDS Convertor"
visible=
"false"
icon=
"xds.gif"
call=
"toolXDS-XM"
/>
</menu>
<menuitem
name=
"toolXDS-XD
"
label=
"Run XDS Debugger
"
icon=
"xds
.gif"
call=
"toolXDS-XD"
/>
</menu
>
<menu
name=
"MainDesignMenu2
"
label=
"Design Menu 2
"
icon=
"sample
.gif"
tip=
"This is an user menu"
inherits=
"MainDesignMenu"
>
<menu
name=
"OtherStuff"
label=
"Various Sample Tools"
>
...
...
@@ -114,21 +77,6 @@
</menu>
<menu
name=
"MainDesignMenu2"
label=
"Design Menu 2"
icon=
"sample.gif"
tip=
"This is an user menu"
inherits=
"MainDesignMenu"
>
<menu
name=
"OtherStuff"
>
<menuitem
name=
"tool4"
label=
"Run My Tool (4)"
icon=
"my_tool.gif"
call=
"MyTool"
/>
</menu>
</menu>
<menu
name=
"MainDesignMenu3"
label=
"Design Menu 3"
icon=
"sample.gif"
...
...
@@ -139,11 +87,24 @@
label=
"Just Another Stuff"
icon=
"sample.gif"
inherits=
"MainDesignMenu2"
after=
"
XDS
"
/>
after=
"
Python tests
"
/>
<menuitem
name=
"GREP"
label=
"Run GREP"
call=
"grep"
/>
<menu
name=
"Python tests"
label=
"Tests with remote Python console"
icon=
"python.png"
>
<menuitem
name=
"RemotePython"
label=
"Run remote Python session"
icon=
"python.png"
call=
"RemotePython"
/>
<menuitem
name=
"RemotePythonCommand"
label=
"Send a command to the remote Python session"
icon=
"my_tool.gif"
call=
"RemotePythonCommand"
/>
</menu>
</menu>
...
...
tools/FPGA_project.xml
View file @
a3c8f614
...
...
@@ -4,7 +4,7 @@
<syntax
name=
"RemoteRootSyntax"
format=
"%%ParamValue/%%ProjectName"
/>
<syntax
name=
"SourceListSyntax"
format=
"%(%%SourceList%| %)"
/>
<syntax
name=
"FilteredSourceListSyntax"
format=
"%(%%FilteredSourceList%| %)"
/>
<!-- typedef -->
</interface>
<package
name=
"FPGA_package"
label=
"Common parameters for all FPGA projects"
...
...
@@ -38,7 +38,9 @@
<parameter
id=
"VivadoConsole"
default=
"Vivado"
label=
"Vivado console name"
type=
"String"
format=
"CopyValue"
visible=
"true"
readonly=
"false"
/>
<!--
-->
<input>
<group
name=
"VivadoServer"
label=
"Vivado server setup"
>
...
...
@@ -66,37 +68,54 @@
readonly=
"false"
/>
<parameter
id=
"SimulationTopModule"
label=
"Project top simulation module"
type=
"String"
default=
""
format=
"CopyValue"
readonly=
"false"
/>
<parameter
id=
"
BuildDir"
label=
"project build
directory"
<parameter
id=
"
SimulDir"
label=
"project simulation
directory"
type=
"Pathname"
default=
"simulation"
format=
"CopyValue"
readonly=
"false"
/>
<!-- Vivado parameters -->
<parameter
id=
"VivadoProjectRoot"
label=
"Relative (to user home directory) path of the workspace on Vivado server"
type=
"String"
default=
"vdt"
format=
"RemoteRootSyntax"
readonly=
"false"
/>
<parameter
id=
"VivadoLocalDir"
label=
"Project subdirectroy for Vivado files"
type=
"Pathname"
default=
"vivado"
format=
"CopyValue"
readonly=
"false"
/>
<parameter
id=
"VivadoIgnoreSource"
label=
"Ignore source files that match this regular expression"
type=
"String"
default=
".*unisims.*"
format=
"CopyValue"
readonly=
"false"
/>
<!-- Calculated -->
<parameter
id=
"VivadoProjectRoot"
label=
"Relative (to user home directory) path of the project on Vivado server"
type=
"String"
default=
"vdt"
format=
"RemoteRootSyntax"
readonly=
"false"
/>
<parameter
id=
"SnapshotSynth"
label=
"name of Vivado snapshot archive after synthesis"
default=
"%%ProjectName-synth.dcp"
type=
"String"
format=
"CopyValue"
/>
<!-- Invisible (calculated) project-wide parameters -->
<parameter
id=
"BuildDirSlash"
type=
"Pathname"
visible=
"false"
default=
"?%BuildDir=:,%BuildDir/"
format=
"CopyValue"
/>
<parameter
id=
"SimulDirSlash"
type=
"Pathname"
visible=
"false"
default=
"?%SimulDir=:,%SimulDir/"
format=
"CopyValue"
/>
<parameter
id=
"SedPaths"
type=
"String"
format=
"CopyValue"
label=
"Remote file prefix to be removed for the local error parser"
default=
"sed -u 's@/home/%RemoteUser/%VivadoProjectRoot/%%ProjectName/@@'"
/>
<input>
<group
name=
"Simulation"
label=
"Simulation properties"
>
"SimulationTopFile"
"SimulationTopModule"
"
Build
Dir"
"
Simul
Dir"
</group>
<group
name=
"Vivado"
label=
"Vivado general properties"
>
"VivadoProjectRoot"
"VivadoLocalDir"
"VivadoIgnoreSource"
"SedPaths"
</group>
<!-- TODO: make time-stamped and "latest" for snapshots -->
<group
name=
"VivadoSnapshots"
label=
"Vivado snapshot archive names"
>
"SnapshotSynth"
</group>
</input>
<output>
</output>
</project>
</vdt-project>
<!-- "| sed -u 's@/home/xilinx/vdt/npmtest/@@'" -->
\ No newline at end of file
tools/SimpleSamples/Remote.xml
View file @
a3c8f614
...
...
@@ -79,7 +79,7 @@
</tool>
<tool
name=
"RemotePythonCommand"
project=
"FPGA_project"
label=
"RemotePythonCommand"
package=
"FPGA_package"
shell=
"
/bin/
bash"
interface=
"RemoteInterface"
shell=
"bash"
interface=
"RemoteInterface"
description=
"Sending command to a ermote Python session"
errors=
"(.*):([0-9]+): [a-z ]*error: (.*)"
warnings=
"(.*):([0-9]+): warning: (.*)"
info=
"(.*):([0-9]+): info: (.*)"
>
<!--does not actually exist -->
<extensions-list>
...
...
tools/SimpleSamples/Tools.xml
View file @
a3c8f614
...
...
@@ -44,13 +44,13 @@
<item
value=
"25"
/>
</paramtype>
</typedef>
<!--
<typedef name="Boolean">
<paramtype kind="bool"
formatTrue="TRUE"
formatFalse="FALSE"/>
</typedef>
-->
<typedef
name=
"MyType4"
>
<paramtype
kind=
"string"
maxlength=
"40"
...
...
@@ -167,7 +167,7 @@
<tool
name =
"MyTool"
project =
"SampleProject"
label =
"My Tool"
shell =
"?%%OS: Windows=, Linux=
/bin/
bash"
shell =
"?%%OS: Windows=, Linux=bash"
interface =
"MyControlInterface"
description =
"Tool that does small minor things"
errors =
"(.*):([0-9]+): [a-z ]*error: (.*)"
...
...
tools/Verilog/CVer.xml
→
tools/Verilog/CVer.xml
.broken
View file @
a3c8f614
File moved
tools/Verilog/IVerilog.xml
View file @
a3c8f614
...
...
@@ -69,7 +69,7 @@
</interface>
<tool
name=
"iverilog"
project=
"FPGA_project"
label=
"Icarus Verilog compiler"
exe=
"iverilog"
shell=
"?%%OS: Windows=shell:, Linux=/bin/
bash"
shell=
"
bash"
package=
"FPGA_package"
interface=
"IVerilog"
errors=
"(.*):([0-9]+): [a-z_\- ]*error: (.*)"
warnings=
"(.*):([0-9]+): [a-z_\- ]*warning: (.*)"
info=
"(.*):([0-9]+): [a-z_\- ]*info: (.*)"
>
<!--do not actually exist -->
...
...
@@ -140,7 +140,7 @@
default=
"false"
label=
"Show output with no errors/warnings"
/>
<parameter
id=
"ShowWarnings"
type=
"BoolYesNo"
format=
"None"
default=
"
fals
e"
label=
"Show output warnings"
/>
default=
"
tru
e"
label=
"Show output warnings"
/>
<parameter
id=
"RemoveBugs"
type=
"BoolYesNo"
format=
"None"
default=
"false"
label=
"Remove buggy simulator output"
/>
...
...
tools/Verilog/IVerilogDebug.xml
deleted
100644 → 0
View file @
b6bfc326
This diff is collapsed.
Click to expand it.
tools/Verilog/ModelSIM.xml
→
tools/Verilog/ModelSIM.xml
.broken
View file @
a3c8f614
File moved
tools/Verilog/XST.xml
→
tools/Verilog/XST.xml
.broken
View file @
a3c8f614
File moved
tools/XDS/XDS.xml
deleted
100644 → 0
View file @
b6bfc326
This diff is collapsed.
Click to expand it.
tools/Xilinx/vivado.xml
→
tools/Xilinx/vivado.xml
.do_not_use
View file @
a3c8f614
File moved
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