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vdt-plugin
Commit 99776ee7 authored by Andrey Filippov's avatar Andrey Filippov
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updated template and design menu

parent a38e3161
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Showing with 71 additions and 66 deletions
templates/verilog.xml
View file @ 99776ee7
......@@ -148,19 +148,24 @@ endmodule
enabled="true"
id="com.elphel.vdt.veditor.templates.verilog.newFile.GPL"
name="Verilog GPL File"
>/*******************************************************************************
* Module: ${modulename}
* Date:${year}-${month}-${day}
* Author: ${user}
* Description: ${brief}
>/!
* <b>Module:</b> ${modulename}
* @file ${modulename}.v
* @date ${year}-${month}-${day}
* @author ${user}
*
* @brief ${brief}
*
* @copyright Copyright (c) ${year} <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* Copyright (c) ${year} <set up in Preferences-Verilog/VHDL Editor-Templates> .
* ${modulename}.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ${modulename}.v is distributed in the hope that it will be useful,
* ${modulename}.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
......@@ -180,7 +185,7 @@ endmodule
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ${modulename}(
......
tools/DesignMenu.xml
View file @ 99776ee7
......@@ -28,12 +28,11 @@
-->
<vdt-project>
<menu name="MainDesignMenu"
label="Design Menu"
icon="sample.gif"
tip="This is a common menu that contains common items">
label="Verilog Tools Menu"
icon="setup.png"
tip="Launch Verilog simulation and synthesis tools">
<menu name="Verilog"
label="Verilog Development Tools"
label="Simulation"
icon="newmod_wiz.gif">
<menuitem name="IVerilog"
label="Icarus Verilog Simulator"
......@@ -45,59 +44,6 @@
icon="gtkwave.ico"
call="iverilog"/>
</menu>
<menu name="ISE"
label="ISE Tools"
icon="ise_logo.png">
<menu name="ISE_utils"
label="ISE utilities"
icon="setup.png">
<menuitem name="ISECopyUnisims"
label="Copy Xilinx ISE primitives library to the local project"
icon="copy.png"
call="ISEUnisims"/>
<menuitem name="ISEPartgen"
label="Run ISE partgen"
icon="bitstream.png"
call="ISEPartgen"/>
</menu>
<menuitem name="ISE Server"
label="Start remote ISE session"
icon="door_in.png"
call="ISE"/>
<menuitem name="ISESynthesis"
label="Synthesize design"
icon="Retort.png"
call="ISExst"/>
<menuitem name="ISENGDBuild"
label="Run NGDBuild"
icon="opt_blue.png"
call="ISENGDBuild"/>
<menuitem name="ISEMap"
label="Map design"
icon="map_icon.png"
call="ISEMap"/>
<menuitem name="ISETraceMap"
label="Report post-map timing"
icon="clock.png"
call="ISETraceMap"/>
<menuitem name="ISEPAR"
label="Place &amp; route design" icon="route66.png"
call="ISEPAR"/>
<menuitem name="ISETracePAR"
label="Report post-implementation timing"
icon="clock.png"
call="ISETracePAR"/>
<menuitem name="ISEReportGen"
label="Generate reports"
icon="source_attach_attrib.gif"
call="ISEReportGen"/>
<menuitem name="ISEBitgen"
label="Generate bitstream file(s)n"
icon="bitstream.png"
call="ISEBitgen"/>
</menu>
<menu name="Vivado"
label="Vivado Tools"
icon="vivado_logo.png">
......@@ -182,6 +128,60 @@
icon="bitstream.png"
call="VivadoBitstream"/>
</menu>
<menu name="ISE"
label="ISE Tools"
icon="ise_logo.png">
<menu name="ISE_utils"
label="ISE utilities"
icon="setup.png">
<menuitem name="ISECopyUnisims"
label="Copy Xilinx ISE primitives library to the local project"
icon="copy.png"
call="ISEUnisims"/>
<menuitem name="ISEPartgen"
label="Run ISE partgen"
icon="bitstream.png"
call="ISEPartgen"/>
</menu>
<menuitem name="ISE Server"
label="Start remote ISE session"
icon="door_in.png"
call="ISE"/>
<menuitem name="ISESynthesis"
label="Synthesize design"
icon="Retort.png"
call="ISExst"/>
<menuitem name="ISENGDBuild"
label="Run NGDBuild"
icon="opt_blue.png"
call="ISENGDBuild"/>
<menuitem name="ISEMap"
label="Map design"
icon="map_icon.png"
call="ISEMap"/>
<menuitem name="ISETraceMap"
label="Report post-map timing"
icon="clock.png"
call="ISETraceMap"/>
<menuitem name="ISEPAR"
label="Place &amp; route design" icon="route66.png"
call="ISEPAR"/>
<menuitem name="ISETracePAR"
label="Report post-implementation timing"
icon="clock.png"
call="ISETracePAR"/>
<menuitem name="ISEReportGen"
label="Generate reports"
icon="source_attach_attrib.gif"
call="ISEReportGen"/>
<menuitem name="ISEBitgen"
label="Generate bitstream file(s)n"
icon="bitstream.png"
call="ISEBitgen"/>
</menu>
<menu name="Quartus"
label="Quartus tools"
icon="quartus16x16.png">
......
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