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Commit 97b1bfc2 authored by Mikhail Karpenko's avatar Mikhail Karpenko
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WIP: fitter interface

parent dcf0e089
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Showing with 59 additions and 40 deletions
tools/Altera_Quartus/quartus_interface.xml
View file @ 97b1bfc2
......@@ -70,15 +70,16 @@
<line name="quartus_restore"
dest="QuartusConsole"
mark="``"
sep=" "
sep="\n"
failure="ERROR"
prompt="@@FINISH@@"
log="">
"cd ~/%QuartusProjectRoot\n"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir\n"
"file mkdir $outputDir\n"
"open_checkpoint %QuartusRemoteDir/%%StateFile\n"
"puts \"@@FINISH@@\"\n"
"puts \"\Restoring snapshot %%StateFile""
"cd ~/%QuartusProjectRoot"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir"
"file mkdir $outputDir"
"project_restore %QuartusRemoteDir/%%StateFile"
"puts \"@@FINISH@@\""
</line>
</output>
</tool>
......@@ -95,15 +96,16 @@
<line name="quartus_save"
dest="QuartusConsole"
mark="``"
sep=" "
sep="\n"
prompt="@@FINISH@@"
failure="ERROR"
log="">
"cd ~/%QuartusProjectRoot\n"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir\n"
"file mkdir $outputDir\n"
"write_checkpoint -force %QuartusRemoteDir/%%StateFile\n"
"puts \"@@FINISH@@\"\n"
"puts \"Saving snapshot %%StateFile\""
"cd ~/%QuartusProjectRoot"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir"
"file mkdir $outputDir"
"project_archive -overwrite %QuartusRemoteDir/%%StateFile"
"puts \"@@FINISH@@\""
</line>
<line name="quartus_copy_after_save">
"-c"
......
tools/Altera_Quartus/quartus_synthesis.xml
View file @ 97b1bfc2
......@@ -74,6 +74,7 @@ may decrease as fast-synthesis netlists take longer to route."/>
restore="RestoreQuartusSynthesis"
disable="DisableQuartusSynth"
save="SaveQuartusSynthesis"
autosave="AutosaveQuartusSynthesis"
inherits="QuartusToolPrototype"
>
......@@ -94,7 +95,7 @@ semantec errors, and perform a netlist exraction."
default="auto" visible="true" readonly="false" omit="auto" type="SynthesisEffort" format="DoubleDash"/>
<parameter id="family" outid="family" label="Device family" tooltip= "Option to target the specified device family. The family name should not contain any
spaces. If you need to add space between words in the family name, make sure that you enclose the family name in double quotation marks."
default="Cyclone V" visible="true" readonly="false" omit="" type="String" format="DoubleDash"/>
default="CycloneV" visible="true" readonly="false" omit="" type="String" format="DoubleDash"/>
<parameter id="ignore_carry_buffers" label="Ignore CARRY_SUM buffers" tooltip="Ignore CARRY_SUM buffers that are instantiated in the design."
default="false" visible="true" omit="false" type="Bool_on_off" format="DoubleDash"/>
<parameter id="ignore_cascade_buffers" label="Ignore CASCADE buffers" tooltip="Ignore CASCADE buffers that are instantiated in the design."
......@@ -107,9 +108,9 @@ spaces. If you need to add space between words in the family name, make sure tha
minimum area usage or high speed performance with minimal area cost during synthesis."
default="balanced" visible="true" readonly="false" omit="balanced" type="OptimizeDesign" format="DoubleDash"/>
<parameter id="parallel" label="# of processors to use" tooltip="Controls parallel compilation. If 0 is specified, the Quartus software
uses all processors detected on the system. Otherwise, the software
attempts to use the specified number of processors."
default="0" visible="true" readonly="false" omit="0" type="Cardinal" format="DoubleDash"/>
uses all processors detected on the system. Otherwise, the software attempts to use the specified number of processors.
Note: this feature is not licenced for the Web Edition and this parameter should be set to 1"
default="1" visible="true" readonly="false" omit="0" type="Cardinal" format="DoubleDash"/>
<parameter id="part_synth" outid="part" label="Part (see Project)" tooltip="Altera device to use (configured in 'project' dialog)"
default="%part" visible="true" readonly="true" omit="" type="String" format="DoubleDash"/>
<parameter id="state_machine_encoding" label="FSM encoding" tooltip="Finite state machine encoding."
......@@ -129,8 +130,8 @@ attempts to use the specified number of processors."
default="" label="Constraints files" tooltip="Select constraint files to load to Quartus" readonly="false"
visible="true" />
<parameter id="SkipSnapshotSynth" label="Skip snapshot" tooltip="Do not create snapshot after synthesis"
default="false" type= "Boolean" format="None"/>
<parameter id="AutosaveQuartusSynthesis" label="Create snapshot" tooltip="Automatically create snapshot after successful synthesis"
default="true" type= "Boolean" format="None"/>
<parameter id="ResetProject" label="Reset project" tooltip="Reset project before loading source files"
default="true" type= "Boolean" format="None"/>
<parameter id="SkipPreSynth" label="Skip pre-synthesis" tooltip="Do not run pre-synthesis TCL commands"
......@@ -144,7 +145,7 @@ attempts to use the specified number of processors."
"FilteredSourceListPar"
"FilteredIncludesListPar"
"ConstraintsFiles"
"SkipSnapshotSynth"
"AutosaveQuartusSynthesis"
"QuartusSnapshotSynth" <!-- same as in project -->
"ResetProject"
"---"
......@@ -206,45 +207,52 @@ attempts to use the specified number of processors."
<line name="quartus_run_synth"
dest="QuartusConsole"
mark="``"
sep=" "
sep="\n"
prompt="@@FINISH@@"
success="@@FINISH@@"
log=""
stdout="parser_Quartus">
"cd ~/%QuartusProjectRoot\n"
"set projectName %%ProjectName\n"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir\n"
"cd ~/%QuartusProjectRoot"
"load_package flow"
"set projectName %%ProjectName"
"set outputDir ~/%QuartusProjectRoot/%QuartusRemoteDir"
"file mkdir $outputDir"
<!-- Load all project files -->
<if ResetProject="true">
<!-- "project_close" -->
"if [is_project_open] { project_close }"
</if>
"file mkdir $outputDir\n"
<!-- Load all project files -->
"foreach file [list %FilteredSourceListPar] {\n"
"puts \"Adding $file to project\"\n"
"set_global_assignment -name VERILOG_FILE $file }\n"
"if [project_exists $projectName] {"
"project_open $projectName"
"} else {"
"project_new $projectName }"
"foreach file [list %FilteredSourceListPar] {"
"puts \"Adding $file to project\""
"set_global_assignment -name VERILOG_FILE $file }"
<if QuartusSynthActionIndex="0">
<if ConstraintsFiles="">
"puts \"No constraints files specified, skipping read_qdc command\";\n"
"puts \"No constraints files specified, skipping read_qdc command\";"
</if>
<if-not ConstraintsFiles="">
"%read_qdc\n"
"%read_qdc"
</if-not>
</if>
<!-- Run pre-synthesis TCL commands (if specified) -->
<if SkipPreSynth="false">
<if-not PreTCL="">
"%PreTCL\n"
"%PreTCL"
</if-not>
<if PreTCL="">
"puts \"No pre-synthesis TCL commands specified\"\n"'
"puts \"No pre-synthesis TCL commands specified\""
</if>
</if>
<!--"if {[catch {execute_module -tool map -args $synth_args} result]} {\n"
"puts \"\nResult: $result\n\""
"puts \"ERROR: Analysis and Synthesis faild. See the report file.\n\""
"} else {\n"
"puts \"\nINFO: Analysis and Synthesis was successful. }\n\""-->
"puts \"@@FINISH@@\"\n"
<!-- Start synthesizer -->
"if {[catch {execute_module -tool map -args $synth_args} result]} {"
"puts \"Result: $result\""
"puts \"ERROR: Analysis and Synthesis faild. See the report file.\""
"} else {"
"puts \"INFO: Analysis and Synthesis was successful.\""
"}"
"puts \"@@FINISH@@\""
</line>
</output>
</tool>
......
tools/DesignMenu.xml
View file @ 97b1bfc2
......@@ -189,6 +189,10 @@
label="Synthesize design"
icon="Retort.png"
call="QuartusSynthesis"/>
<menuitem name="QuartusFitter"
label="Place and route design"
icon="route66.png"
call="QuartusPlace"/>
</menu>
......
tools/FPGA_project.xml
View file @ 97b1bfc2
......@@ -463,7 +463,12 @@
<parameter id="QuartusSnapshotSynth"
label="Synthesis snapshot" tooltip="Name of Quartus snapshot archive"
default="%%ProjectName.qar"
default="%%ProjectName-synth.qar"
type="String" format="CopyValue" />
<parameter id="QuartusSnapshotPlace"
label="Place and route snapshot" tooltip="Name of Quartus snapshot archive"
default="%%ProjectName-par.qar"
type="String" format="CopyValue" />
<input>
......
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