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vdt-plugin
Commit 71997eed authored by Andrey Filippov's avatar Andrey Filippov
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More on tool-specific closure, added support for parameters in functions/tasks

parent 1b185b7e
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Showing with 56 additions and 17 deletions
src/com/elphel/vdt/VerilogUtils.java
View file @ 71997eed
......@@ -31,6 +31,7 @@ import java.util.ArrayList;
import java.util.List;
//import java.util.Map;
import com.elphel.vdt.ui.variables.SelectedResourceManager;
import com.elphel.vdt.veditor.VerilogPlugin;
import com.elphel.vdt.veditor.document.HdlDocument;
......@@ -99,7 +100,8 @@ public class VerilogUtils {
if (SelectedResourceManager.getDefault().getChosenVerilogFile()==null) {
System.out.println("database is null, and no Verilog file is selected to create one.");
return null;
}
}
// getChosenVerilogFile() sometimes returns project (after switching projects)
hdlDocument=new VerilogDocument(project, (IFile) SelectedResourceManager.getDefault().getChosenVerilogFile());
return hdlDocument.getOutlineDatabase(); /* will create a new one if does not exist */
}
......@@ -156,7 +158,7 @@ public class VerilogUtils {
public static OutlineElement[] getTopModulesVeditor(IFile file) {
IProject project = file.getProject();
if (project==null){
System.out.println("getTopModulesVeditor(): Projectis null for file="+file.getFullPath());
System.out.println("getTopModulesVeditor(): Project is null for file="+file.getFullPath());
return null;
}
OutlineDatabase outlineDatabase=getVeditorOutlineDatabase(project);
......@@ -193,14 +195,18 @@ public class VerilogUtils {
if (toolDefine != null) {
OutlineDatabase outlineDatabase=new OutlineDatabase(project); // new OutlineDatabase just for this scan
outlineDatabase.scanFilesWithDefine(topFile,toolDefine);
// System.out.println("-->>>VerilogUtils.getDependencies number of files="+outlineDatabase.getDatabaseFileList().length);
// for (int i=0; i<outlineDatabase.getDatabaseFileList().length; i++){
// System.out.println(i+": "+outlineDatabase.getDatabaseFileList()[i]);
// }
if (VerilogPlugin.getPreferenceBoolean(PreferenceStrings.DEBUG_CLOSURE)) {
System.out.println("-->>>VerilogUtils.getDependencies number of files="+outlineDatabase.getDatabaseFileList().length);
for (int i=0; i<outlineDatabase.getDatabaseFileList().length; i++){
System.out.println(i+": "+outlineDatabase.getDatabaseFileList()[i]);
}
}
IFile[] topFiles = {topFile};
return outlineDatabase.getClosureSorted(topFiles);
} else {
// System.out.println("===---VerilogUtils.getDependencies("+topFile+") - using editor depends");
if (VerilogPlugin.getPreferenceBoolean(PreferenceStrings.DEBUG_CLOSURE)) {
System.out.println("===---VerilogUtils.getDependencies("+topFile+") - using editor depends");
}
return getDependencies(new IFile [] {topFile});
}
}
......
src/com/elphel/vdt/core/tools/generators/FilteredSourceListGenerator.java
View file @ 71997eed
......@@ -41,6 +41,7 @@ import org.eclipse.core.resources.IResource;
//import com.elphel.vdt.VDT;
import com.elphel.vdt.VerilogUtils;
import com.elphel.vdt.core.tools.params.FormatProcessor;
......@@ -48,6 +49,8 @@ import com.elphel.vdt.core.tools.params.Tool;
import com.elphel.vdt.ui.MessageUI;
//import com.elphel.vdt.core.verilog.VerilogUtils;
import com.elphel.vdt.ui.variables.SelectedResourceManager;
import com.elphel.vdt.veditor.VerilogPlugin;
import com.elphel.vdt.veditor.preference.PreferenceStrings;
/**
* Generate the file name list of dependency closure for last selected
......@@ -84,7 +87,9 @@ public class FilteredSourceListGenerator extends AbstractGenerator {
// System.out.println(", tool="+tool+" tool name="+((tool!=null)?tool.getName():null));
if (tool != null) {
ignoreFilter=tool.getIgnoreFilter();
// System.out.println("FilteredSourceListGenerator().getStringValue(): tool="+tool.getName()+", ignoreFilter="+ignoreFilter);
if (VerilogPlugin.getPreferenceBoolean(PreferenceStrings.DEBUG_CLOSURE)) {
System.out.println("FilteredSourceListGenerator().getStringValue(): tool="+tool.getName()+", ignoreFilter="+ignoreFilter);
}
topFile = tool.getTopFile();
toolDefine = tool.getDefine();
if ((toolDefine == null) || (toolDefine == "")) {
......@@ -92,7 +97,9 @@ public class FilteredSourceListGenerator extends AbstractGenerator {
else toolDefine = ""; // reparse for this tool - top file may have different defines
}
if (!tool.needsTreeReparse()) toolDefine = null;
// System.out.println("topFile="+topFile+ " toolDefine="+toolDefine);
if (VerilogPlugin.getPreferenceBoolean(PreferenceStrings.DEBUG_CLOSURE)) {
System.out.println("topFile="+topFile+ " toolDefine="+toolDefine);
}
} else {
System.out.println("FilteredSourceListGenerator(): topProcessor.getCurrentTool() is null");
}
......@@ -121,16 +128,29 @@ public class FilteredSourceListGenerator extends AbstractGenerator {
if (resource != null && resource.getType() == IResource.FILE) {
IFile[] files = VerilogUtils.getDependencies((IFile)resource, toolDefine); // returned just the same x353_1.tf
// System.out.println("FilteredSourceListGenerator(): resource = "+resource);
if (VerilogPlugin.getPreferenceBoolean(PreferenceStrings.DEBUG_CLOSURE)) {
for (IFile fl: files) {
System.out.println("FilteredSourceListGenerator()"+fl);
}
System.out.println("FilteredSourceListGenerator(): resource = "+resource);
}
List<String> fileList=new ArrayList<String>();
for (int i=0; i < files.length; i++) {
String fileName=files[i].getProjectRelativePath().toOSString(); //.getName();
if ((ignorePattern!=null) &&ignorePattern.matcher(fileName).matches()) {
// System.out.println("FilteredSourceListGenerator() IGNORE "+fileName+" ("+files[i]+")");
continue;
}
fileList.add(fileName);
// System.out.println("FilteredSourceListGenerator() ADDED "+fileName+" ("+files[i]+")");
}
file_names=fileList.toArray(new String[0]);
if (VerilogPlugin.getPreferenceBoolean(PreferenceStrings.DEBUG_CLOSURE)) {
for (String fn: file_names) {
System.out.println(String.format("FilteredSourceListGenerator() %s ",fn));
}
}
} else {
// fault("There is no selected project");
System.out.println(getName()+": no project selected");
......
src/com/elphel/vdt/core/tools/params/ToolSequence.java
View file @ 71997eed
......@@ -53,6 +53,7 @@ import com.elphel.vdt.ui.options.FilteredFileSelector;
import com.elphel.vdt.ui.variables.SelectedResourceManager;
import com.elphel.vdt.ui.views.DesignFlowView;
import com.elphel.vdt.veditor.VerilogPlugin;
import com.elphel.vdt.veditor.parser.OutlineDatabase;
import com.elphel.vdt.veditor.preference.PreferenceStrings;
import java.io.File;
......@@ -734,9 +735,13 @@ java.lang.NullPointerException
String fullPath,
String ignoreFilter) throws CoreException {
if (!okToRun()) return;
// Just testing://
// OutlineDatabase.getProjectsDatabase(SelectedResourceManager.getDefault().getSelectedProject()).invalidateToolCache();
// Set this tool dirty (not to try reports on this tool before it ran)
DEBUG_PRINT("launchToolSequence("+tool.getName()+", setting its state to \"Dirty\"");
tool.setDirty(true);
setStateProvides(); // just testing
// tool.setDesignFlowView(designFlowView);
......
src/com/elphel/vdt/ui/variables/SelectedResourceManager.java
View file @ 71997eed
......@@ -363,7 +363,8 @@ public class SelectedResourceManager implements IWindowListener, ISelectionListe
if (project.getFullPath().toPortableString().equals(rslt.getProject().getFullPath().toPortableString())){
return (fChosenVerilogFile!=null)?fChosenVerilogFile:fSelectedVerilogFile;
} else {
System.out.println("Wrong getChosenVerilogFile="+rslt+" for project "+project);
System.out.println("Wrong getChosenVerilogFile="+rslt+" for project "+project);
fChosenVerilogFile = null; // invalidate
if (fSelectedVerilogFile==null) return null;
if (project.getFullPath().toPortableString().equals(fSelectedVerilogFile.getProject().getFullPath().toPortableString())){
System.out.println("Using: "+fSelectedVerilogFile);
......
src/com/elphel/vdt/ui/views/DesignFlowView.java
View file @ 71997eed
......@@ -1270,8 +1270,15 @@ public class DesignFlowView extends ViewPart implements ISelectionListener {
toggleLinkedTools.setChecked(!SelectedResourceManager.getDefault().isToolsLinked());
// Initialize VEditor database build
IResource HDLFile=SelectedResourceManager.getDefault().getChosenVerilogFile();
// restore properties from the project, overwrite global ones
restoreCurrentState(selectedResource.getProject()); // null OK
// restore properties from the project, overwrite global ones
IProject project;
if (selectedResource == null) {
project = SelectedResourceManager.getDefault().getSelectedProject();
} else {
project = HDLFile.getProject();
}
// restoreCurrentState(selectedResource.getProject()); // null OK
restoreCurrentState(project); // null OK
if ((HDLFile!=null) && HDLFile.exists()){
toolSequence.setUnfinishedBoot(memento,true);
......
tools/Verilog/IVerilog.xml
View file @ 71997eed
......@@ -226,7 +226,7 @@
visible="true" />
<parameter id="GrepFindErrWarn" label="Grep pattern for both errors and warnings"
type="String" format="GrepFindSyntax" default="error|warning"
type="String" format="GrepFindSyntax" default="error|warning|sorry"
readonly="false" visible="true" />
<parameter id="GrepSkip1" label="Grep skip pattern" type="String"
......@@ -361,7 +361,7 @@
<if-not IVerilogActionIndex="2">
"%OutFileFull"
</if-not>
" -D IVERILOG"
" -DIVERILOG"
"%IVerilogOther"
"%Param_TopModule"
"%TopModulesOther"
......
tools/Xilinx_Vivado/vivado_bitstream.xml
View file @ 71997eed
......@@ -59,7 +59,7 @@
<parameter id="rawfile" label="Bitstream filename" tooltip= "Bitstream file name (will add *.bit extension)."
default="%%ProjectName" visible="true" omit="" type="String" format="CopyValue"/>
<parameter id="force" label="Force (overwrite)" tooltip= "Overwrite existent files."
default="false" visible="true" omit="false" type="Boolean" format="DashName"/>
default="true" visible="true" omit="false" type="Boolean" format="DashName"/>
<parameter id="raw_bitfile" label="Write raw bitfile" tooltip= "Write bitfile in ASCII (*.rbt)."
default="false" visible="true" omit="false" type="Boolean" format="DashName"/>
<parameter id="no_binary_bitfile" label="Do not write .bit" tooltip= "Do not write to binary bitfile (*.bit)."
......
vdt-veditor.patch
View file @ 71997eed
......@@ -75506,7 +75506,7 @@ diff -U 3 -dHrN -- vdt-veditor/src/com/elphel/vdt/veditor/parser/verilog/Verilog
-}
-
+/*******************************************************************************
+ * Notice: this progam DOES NOT have a valid distribution license and has to be
+ * Notice: This program DOES NOT have a valid distribution license and has to be
+ * re-generated by a user.
+ *
+ * This program is made of the original VEditor code released under Eclipse Public
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