Continue implementation of the Xilinx tools settings control.

tools/DesignMenu.xml

@@ -52,6 +52,13 @@
                           label="Run Vivado synthesis"
                           icon="xilinx.png"
                           call="VivadoSynthesis"/>
+                <menuitem name="VivadoOptPlace"
+                          label="Optimize and place design"
+                          icon="xilinx.png"
+                          call="VivadoOptPlace"/>
+                          
+                          
+                          
         </menu>                  
     </menu>
     

tools/FPGA_project.xml

@@ -123,6 +123,15 @@
 	        default="%%ProjectName-synth.dcp"
 			type="String" format="CopyValue" />
 
+	 	    <parameter id="SnapshotOptPlace"
+	        label="name of Vivado snapshot archive after optimization/placement"
+	        default="%%ProjectName-opt-pace.dcp"
+			type="String" format="CopyValue" />
+
+ 				"" <!--  same as in project -->
+
+
+
 <!-- Invisible (calculated) project-wide parameters -->			
 		<parameter id="SimulDirSlash" type="Pathname" visible="false"
 		 default="?%SimulDir=:,%SimulDir/" format="CopyValue"/>
@@ -148,6 +157,7 @@
 			<!--  TODO: make time-stamped and "latest" for snapshots -->
 			<group name="VivadoSnapshots" label="Vivado snapshot archive names">
 				"SnapshotSynth"
+				"SnapshotOptPlace"
 			</group>
 		</input>
 		<output>

tools/Xilinx/vivado_interface.xml

@@ -2,6 +2,11 @@
 
 <vdt-project>
 	<interface name="VivadoInterface" extends="FPGAPprojectInterface">
+		<syntax name="QuietSyntax"     format=" -quiet" />
+		<syntax name="VerboseSyntax"   format=" -verbose" />
+		<syntax name="DirectiveSyntax" format=" -directive %%ParamValue" />
+		
+	
 	<!-- 
 		<syntax name="ProgramSyntax" format="%(%%ParamValue%|\n%)" />
 		<syntax name="read_xdc_syntax" format="%(read_xdc %%ParamValue%|\n%)" /> -->

tools/Xilinx/vivado_synthesis.xml

@@ -49,7 +49,7 @@
     	</typedef>
 	</interface>
 
-	<tool name="VivadoSynthesis" label="Load Source files to Vivado"
+	<tool name="VivadoSynthesis" label="Load Source files to Vivado and Synthesise"
 	    project="FPGA_project"
 		interface="VivadoSynthesisInterface"
 		package="FPGA_package"