Commit 05b23006 authored by Andrey Filippov's avatar Andrey Filippov

Changed TopModule<s> generators to use tool's top file if available

parent 6a465d09
...@@ -29,7 +29,8 @@ package com.elphel.vdt.core.tools.generators; ...@@ -29,7 +29,8 @@ package com.elphel.vdt.core.tools.generators;
import org.eclipse.core.resources.IFile; import org.eclipse.core.resources.IFile;
import org.eclipse.core.resources.IResource; import org.eclipse.core.resources.IResource;
import com.elphel.vdt.VDT; import com.elphel.vdt.VDT;
import com.elphel.vdt.VerilogUtils; import com.elphel.vdt.VerilogUtils;
import com.elphel.vdt.core.tools.params.Tool;
import com.elphel.vdt.ui.variables.SelectedResourceManager; import com.elphel.vdt.ui.variables.SelectedResourceManager;
/** /**
...@@ -50,8 +51,24 @@ public class TopModuleNameGenerator extends AbstractGenerator { ...@@ -50,8 +51,24 @@ public class TopModuleNameGenerator extends AbstractGenerator {
return NAME; return NAME;
} }
protected String[] getStringValues() { protected String[] getStringValues() {
// IResource resource = SelectedResourceManager.getDefault().getSelectedVerilogFile(); IResource resource = SelectedResourceManager.getDefault().getChosenVerilogFile();
IResource resource = SelectedResourceManager.getDefault().getChosenVerilogFile(); // Use tool top file if available, otherwise use getChosenVerilogFile() as before
String topFile = null;
if (topProcessor!=null){
Tool tool=topProcessor.getCurrentTool();
if (tool != null) {
topFile=tool.getTopFile();
} else {
System.out.println("ToolNameGenerator(): topProcessor.getCurrentTool() is null");
}
if ((topFile != null) && (topFile !="") && (resource !=null)) {
IResource resource1 = resource.getProject().getFile(topFile);
if ((resource1 != null) && (resource1.getType() == IResource.FILE)){
resource = resource1;
}
}
}
if ((resource != null) && (resource.getType() == IResource.FILE)) { if ((resource != null) && (resource.getType() == IResource.FILE)) {
String[] outlineElementsNames= VerilogUtils.getTopModuleNames((IFile)resource); String[] outlineElementsNames= VerilogUtils.getTopModuleNames((IFile)resource);
if ((outlineElementsNames!=null) && (outlineElementsNames.length>0)) return new String[] {outlineElementsNames[0]}; if ((outlineElementsNames!=null) && (outlineElementsNames.length>0)) return new String[] {outlineElementsNames[0]};
......
...@@ -30,7 +30,8 @@ import org.eclipse.core.resources.IFile; ...@@ -30,7 +30,8 @@ import org.eclipse.core.resources.IFile;
import org.eclipse.core.resources.IResource; import org.eclipse.core.resources.IResource;
//import com.elphel.vdt.VDT; //import com.elphel.vdt.VDT;
import com.elphel.vdt.VerilogUtils; import com.elphel.vdt.VerilogUtils;
import com.elphel.vdt.core.tools.params.Tool;
import com.elphel.vdt.ui.variables.SelectedResourceManager; import com.elphel.vdt.ui.variables.SelectedResourceManager;
/** /**
...@@ -54,8 +55,24 @@ public class TopModulesNameGenerator extends AbstractGenerator { ...@@ -54,8 +55,24 @@ public class TopModulesNameGenerator extends AbstractGenerator {
return NAME; return NAME;
} }
protected String[] getStringValues() { protected String[] getStringValues() {
// IResource resource = SelectedResourceManager.getDefault().getSelectedVerilogFile(); IResource resource = SelectedResourceManager.getDefault().getChosenVerilogFile();
IResource resource = SelectedResourceManager.getDefault().getChosenVerilogFile(); // Use tool top file if available, otherwise use getChosenVerilogFile() as before
String topFile = null;
if (topProcessor!=null){
Tool tool=topProcessor.getCurrentTool();
if (tool != null) {
topFile=tool.getTopFile();
} else {
System.out.println("ToolNameGenerator(): topProcessor.getCurrentTool() is null");
}
if ((topFile != null) && (topFile !="") && (resource !=null)) {
IResource resource1 = resource.getProject().getFile(topFile);
if ((resource1 != null) && (resource1.getType() == IResource.FILE)){
resource = resource1;
}
}
}
if ((resource != null) && (resource.getType() == IResource.FILE)) { if ((resource != null) && (resource.getType() == IResource.FILE)) {
String[] outlineElementsNames= VerilogUtils.getTopModuleNames((IFile)resource); String[] outlineElementsNames= VerilogUtils.getTopModuleNames((IFile)resource);
if ((outlineElementsNames!=null) && (outlineElementsNames.length>0)) return outlineElementsNames; if ((outlineElementsNames!=null) && (outlineElementsNames.length>0)) return outlineElementsNames;
......
...@@ -338,7 +338,9 @@ ...@@ -338,7 +338,9 @@
</if> </if>
"%MaxMsg\n" "%MaxMsg\n"
"synth_design" "synth_design"
"%top" "%top"
<!-- "-top"
"%%TopModule" -->
<if VivadoSynthActionIndex="0"> <if VivadoSynthActionIndex="0">
"%name" "%name"
<!-- "%part" --> <!-- "%part" -->
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment