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Elphel
vdt-plugin
Commits
056edc94
Commit
056edc94
authored
Jun 18, 2016
by
Andrey Filippov
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Changed TopModule<s> generators to use tool's top file if available
parent
99776ee7
Changes
2
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2 changed files
with
40 additions
and
6 deletions
+40
-6
TopModuleNameGenerator.java
...hel/vdt/core/tools/generators/TopModuleNameGenerator.java
+20
-3
TopModulesNameGenerator.java
...el/vdt/core/tools/generators/TopModulesNameGenerator.java
+20
-3
No files found.
src/com/elphel/vdt/core/tools/generators/TopModuleNameGenerator.java
View file @
056edc94
...
@@ -30,6 +30,7 @@ import org.eclipse.core.resources.IFile;
...
@@ -30,6 +30,7 @@ import org.eclipse.core.resources.IFile;
import
org.eclipse.core.resources.IResource
;
import
org.eclipse.core.resources.IResource
;
import
com.elphel.vdt.VDT
;
import
com.elphel.vdt.VDT
;
import
com.elphel.vdt.VerilogUtils
;
import
com.elphel.vdt.VerilogUtils
;
import
com.elphel.vdt.core.tools.params.Tool
;
import
com.elphel.vdt.ui.variables.SelectedResourceManager
;
import
com.elphel.vdt.ui.variables.SelectedResourceManager
;
/**
/**
...
@@ -50,8 +51,24 @@ public class TopModuleNameGenerator extends AbstractGenerator {
...
@@ -50,8 +51,24 @@ public class TopModuleNameGenerator extends AbstractGenerator {
return
NAME
;
return
NAME
;
}
}
protected
String
[]
getStringValues
()
{
protected
String
[]
getStringValues
()
{
// IResource resource = SelectedResourceManager.getDefault().getSelectedVerilogFile();
IResource
resource
=
SelectedResourceManager
.
getDefault
().
getChosenVerilogFile
();
IResource
resource
=
SelectedResourceManager
.
getDefault
().
getChosenVerilogFile
();
// Use tool top file if available, otherwise use getChosenVerilogFile() as before
String
topFile
=
null
;
if
(
topProcessor
!=
null
){
Tool
tool
=
topProcessor
.
getCurrentTool
();
if
(
tool
!=
null
)
{
topFile
=
tool
.
getTopFile
();
}
else
{
System
.
out
.
println
(
"ToolNameGenerator(): topProcessor.getCurrentTool() is null"
);
}
if
((
topFile
!=
null
)
&&
(
topFile
!=
""
)
&&
(
resource
!=
null
))
{
IResource
resource1
=
resource
.
getProject
().
getFile
(
topFile
);
if
((
resource1
!=
null
)
&&
(
resource1
.
getType
()
==
IResource
.
FILE
)){
resource
=
resource1
;
}
}
}
if
((
resource
!=
null
)
&&
(
resource
.
getType
()
==
IResource
.
FILE
))
{
if
((
resource
!=
null
)
&&
(
resource
.
getType
()
==
IResource
.
FILE
))
{
String
[]
outlineElementsNames
=
VerilogUtils
.
getTopModuleNames
((
IFile
)
resource
);
String
[]
outlineElementsNames
=
VerilogUtils
.
getTopModuleNames
((
IFile
)
resource
);
if
((
outlineElementsNames
!=
null
)
&&
(
outlineElementsNames
.
length
>
0
))
return
new
String
[]
{
outlineElementsNames
[
0
]};
if
((
outlineElementsNames
!=
null
)
&&
(
outlineElementsNames
.
length
>
0
))
return
new
String
[]
{
outlineElementsNames
[
0
]};
...
...
src/com/elphel/vdt/core/tools/generators/TopModulesNameGenerator.java
View file @
056edc94
...
@@ -31,6 +31,7 @@ import org.eclipse.core.resources.IResource;
...
@@ -31,6 +31,7 @@ import org.eclipse.core.resources.IResource;
//import com.elphel.vdt.VDT;
//import com.elphel.vdt.VDT;
import
com.elphel.vdt.VerilogUtils
;
import
com.elphel.vdt.VerilogUtils
;
import
com.elphel.vdt.core.tools.params.Tool
;
import
com.elphel.vdt.ui.variables.SelectedResourceManager
;
import
com.elphel.vdt.ui.variables.SelectedResourceManager
;
/**
/**
...
@@ -54,8 +55,24 @@ public class TopModulesNameGenerator extends AbstractGenerator {
...
@@ -54,8 +55,24 @@ public class TopModulesNameGenerator extends AbstractGenerator {
return
NAME
;
return
NAME
;
}
}
protected
String
[]
getStringValues
()
{
protected
String
[]
getStringValues
()
{
// IResource resource = SelectedResourceManager.getDefault().getSelectedVerilogFile();
IResource
resource
=
SelectedResourceManager
.
getDefault
().
getChosenVerilogFile
();
IResource
resource
=
SelectedResourceManager
.
getDefault
().
getChosenVerilogFile
();
// Use tool top file if available, otherwise use getChosenVerilogFile() as before
String
topFile
=
null
;
if
(
topProcessor
!=
null
){
Tool
tool
=
topProcessor
.
getCurrentTool
();
if
(
tool
!=
null
)
{
topFile
=
tool
.
getTopFile
();
}
else
{
System
.
out
.
println
(
"ToolNameGenerator(): topProcessor.getCurrentTool() is null"
);
}
if
((
topFile
!=
null
)
&&
(
topFile
!=
""
)
&&
(
resource
!=
null
))
{
IResource
resource1
=
resource
.
getProject
().
getFile
(
topFile
);
if
((
resource1
!=
null
)
&&
(
resource1
.
getType
()
==
IResource
.
FILE
)){
resource
=
resource1
;
}
}
}
if
((
resource
!=
null
)
&&
(
resource
.
getType
()
==
IResource
.
FILE
))
{
if
((
resource
!=
null
)
&&
(
resource
.
getType
()
==
IResource
.
FILE
))
{
String
[]
outlineElementsNames
=
VerilogUtils
.
getTopModuleNames
((
IFile
)
resource
);
String
[]
outlineElementsNames
=
VerilogUtils
.
getTopModuleNames
((
IFile
)
resource
);
if
((
outlineElementsNames
!=
null
)
&&
(
outlineElementsNames
.
length
>
0
))
return
outlineElementsNames
;
if
((
outlineElementsNames
!=
null
)
&&
(
outlineElementsNames
.
length
>
0
))
return
outlineElementsNames
;
...
...
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