pose_scene_dp: ONE device entry per scene. Self-chaining launchers (D1
pattern): pose_measure_dp (D2, payload unchanged; its tail launcher now
chains onward via a new PoseMeasureChain.scene back-pointer) ->
pose_scene_dp_lma (per-cycle prepare from LIVE corr-row count; full mode
= production per-cycle conditioning re-derivation with clears/assemble/
norm/fx/finish, light mode = the D1 frozen body) -> pose_scene_dp_step
(full-mode pure_weight read LIVE from prep_result - it changes every
cycle; the six validated spike stages) -> pose_scene_dp_commit (anchor
update on accept, 25-float trace + 5-int measure-stats trace rows,
self-chains the next cycle's measure). Fixed-K, no device early exit;
guard/invalid-prepare failures stop the chain fail-safe with
cycles-completed visible to the host.

Wrapper tp_proc_exec_pose_scene_dp: C2 nullable uploads + per-scene
policy/pull/reg/anchor, full provisioning (D2 measure provision + the
prepare/step scratch blocks), B4 bayer fence, ONE launch, ONE
end-of-scene readback (scene status + measure status + traces + final
packed + final anchor + compact prep); peaks/indices stay resident for
the unchanged fetch calls. D2 entry refactored onto shared
pose_measure_provision/pose_mchain_fill (same bytes).

GATE (cases.list scene_dp): test_pose_scene_dp_jna rides the captured
pose_corr case at the production 5120/150 LMA shape (full-grid centers
scattered by task txy - corr indices carry full-grid tile numbers).
Four chains vs the host-driven B3 loop (measure -> prepare_resident ->
resident step, host anchor bookkeeping): full accept K=3, full reject
K=2, full post-reject K=2, light K=2 riding the conditioning frozen by
the preceding full chain. Per-cycle trace rows, measure stats, final
packed/anchor/prep, and last-cycle corr rows keyed by packed index ALL
bit-identical; the measure<->LMA interleave is real (accepts move the
pose the next cycle measures at). run_cases.sh ALL PASS incl. pose_corr
@tol 0 + dp_cycles + measure_dp; DP spike PASS; sanitizer-12.8 memcheck
0 errors. Native-test timing is A==B by construction (no JNA in either
arm); the production win - killing the per-cycle Java/JNA round trips -
lands at rung D4.
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>