Loading .eclipse_project_setup/.project 0 → 100644 +17 −0 Original line number Original line Diff line number Diff line <?xml version="1.0" encoding="UTF-8"?> <projectDescription> <name>oc_jpegencode</name> <comment></comment> <projects> </projects> <buildSpec> <buildCommand> <name>org.python.pydev.PyDevBuilder</name> <arguments> </arguments> </buildCommand> </buildSpec> <natures> <nature>org.python.pydev.pythonNature</nature> </natures> </projectDescription> .eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +8 −0 Original line number Original line Diff line number Diff line FPGA_project_0_SimulationTopFile=code/jpeg_top_TB.v FPGA_project_1_SimulationTopModule=UUT FPGA_project_2_DUTTopFile=code/jpeg_top.v FPGA_project_2_ImplementationTopFile=code/jpeg_top.v FPGA_project_3_DUTTopModule=jpeg_top FPGA_project_3_ImplementationTopModule=jpeg_top com.elphel.store.context.FPGA_project=FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@-> eclipse.preferences.version=1 .eclipse_project_setup/.settings/com.elphel.vdt.cocotb.prefs 0 → 100644 +9 −0 Original line number Original line Diff line number Diff line cocotb_105_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@-> cocotb_110_COCOTB_ANSI_OUTPUT=true cocotb_111_CocotbMODULE=test_jpeg_top<-@\#\#@-> cocotb_113_MakeCleanPatterns=*.pyc results.xml<-@\#\#@->*.jpg<-@\#\#@-> cocotb_116_GTKWaveSavFile=jpeg_top_01.sav cocotb_117_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@-> cocotb_120_GTKWaveSavFile=jpeg_top_01.gtkw com.elphel.store.context.cocotb=cocotb_120_GTKWaveSavFile<-@\#\#@->cocotb_113_MakeCleanPatterns<-@\#\#@->cocotb_117_CocotbIncludeDir<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_105_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->cocotb_110_COCOTB_ANSI_OUTPUT<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@-> eclipse.preferences.version=1 .eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs 0 → 100644 +4 −0 Original line number Original line Diff line number Diff line com.elphel.store.context.iverilog=iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@-> eclipse.preferences.version=1 iverilog_120_GTKWaveSavFile=jpeg_top_01.gtkw iverilog_123_GTKWaveSavFile=jpegencode_01.sav .eclipse_project_setup/.settings/com.elphel.vdt.prefs 0 → 100644 +3 −0 Original line number Original line Diff line number Diff line com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@-> com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu eclipse.preferences.version=1 Loading
.eclipse_project_setup/.project 0 → 100644 +17 −0 Original line number Original line Diff line number Diff line <?xml version="1.0" encoding="UTF-8"?> <projectDescription> <name>oc_jpegencode</name> <comment></comment> <projects> </projects> <buildSpec> <buildCommand> <name>org.python.pydev.PyDevBuilder</name> <arguments> </arguments> </buildCommand> </buildSpec> <natures> <nature>org.python.pydev.pythonNature</nature> </natures> </projectDescription>
.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644 +8 −0 Original line number Original line Diff line number Diff line FPGA_project_0_SimulationTopFile=code/jpeg_top_TB.v FPGA_project_1_SimulationTopModule=UUT FPGA_project_2_DUTTopFile=code/jpeg_top.v FPGA_project_2_ImplementationTopFile=code/jpeg_top.v FPGA_project_3_DUTTopModule=jpeg_top FPGA_project_3_ImplementationTopModule=jpeg_top com.elphel.store.context.FPGA_project=FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@-> eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.cocotb.prefs 0 → 100644 +9 −0 Original line number Original line Diff line number Diff line cocotb_105_CocotbCUSTOM_COMPILE_DEPS=IVERILOG_INCLUDE.v<-@\#\#@-> cocotb_110_COCOTB_ANSI_OUTPUT=true cocotb_111_CocotbMODULE=test_jpeg_top<-@\#\#@-> cocotb_113_MakeCleanPatterns=*.pyc results.xml<-@\#\#@->*.jpg<-@\#\#@-> cocotb_116_GTKWaveSavFile=jpeg_top_01.sav cocotb_117_CocotbIncludeDir=${verilog_project_loc}<-@\#\#@-> cocotb_120_GTKWaveSavFile=jpeg_top_01.gtkw com.elphel.store.context.cocotb=cocotb_120_GTKWaveSavFile<-@\#\#@->cocotb_113_MakeCleanPatterns<-@\#\#@->cocotb_117_CocotbIncludeDir<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_105_CocotbCUSTOM_COMPILE_DEPS<-@\#\#@->cocotb_110_COCOTB_ANSI_OUTPUT<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@-> eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs 0 → 100644 +4 −0 Original line number Original line Diff line number Diff line com.elphel.store.context.iverilog=iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@-> eclipse.preferences.version=1 iverilog_120_GTKWaveSavFile=jpeg_top_01.gtkw iverilog_123_GTKWaveSavFile=jpegencode_01.sav
.eclipse_project_setup/.settings/com.elphel.vdt.prefs 0 → 100644 +3 −0 Original line number Original line Diff line number Diff line com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@-> com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu eclipse.preferences.version=1