Commit ecc6fb79 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev
Browse files

merged from rocko branch, updated rootfs flash partition size to 320MB

parent cedb06fe

src/arch/arm/boot/dts/elphel393-bootargs-nand.dtsi

+1 −1
Original line number Diff line number Diff line 
/**/

/ {

	chosen {

		bootargs = "earlycon cma=336M root=ubi0:elphel393-rootfs rootwait rootfstype=ubifs ubi.mtd=4,512";

		bootargs = "earlycon cma=336M root=ubi0:elphel393-rootfs rootwait rootfstype=ubifs ubi.mtd=4,2048";

		stdout-path = "serial0:115200n8";

	};

};

src/arch/arm/boot/dts/elphel393_4_mt9p006_revB.dts→src/arch/arm/boot/dts/elphel393-common.dtsi

+18 −11
Original line number Diff line number Diff line 
/* welcome to elphel393 device tree */

/include/ "elphel393-zynq-base.dtsi"

/include/ "elphel393-bootargs.dtsi"

/* elphel393 device tree */





/ {

	model = "Elphel 10393";
@@ -114,17 +113,26 @@ 
					device_type = "ethernet-phy";

					/* rev0 - revB: reg = <0x3> */

					/* revC:        reg = <0x0> */

					reg = <0x3>;

					reg = <0x0>;

				};

			};

		};



		smcc: memory-controller@e000e000 {

			nand0: flash@e1000000 {

				partitions {

					compatible = "fixed-partitions";

					#address-cells = <1>;

					#size-cells = <1>;

		ps7_smcc_0: ps7-smcc@e000e000 {

			ps7_nand_0: ps7-nand@e1000000 {

				compatible = "arm,pl353-nand-r2p1";

				reg = < 0xe1000000 0x1000000 >;

				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/

				arm,nand-width = <0x8>;

				arm,nand-cycle-t0 = <0x4>;

				arm,nand-cycle-t1 = <0x4>;

				arm,nand-cycle-t2 = <0x1>;

				arm,nand-cycle-t3 = <0x2>;

				arm,nand-cycle-t4 = <0x2>;

				arm,nand-cycle-t5 = <0x2>;

				arm,nand-cycle-t6 = <0x4>;

				#address-cells = <0x1>;

				#size-cells = <0x1>;

				partition@0 {

					label = "u-boot-spl";

					reg = <0x0 0x100000>;/*1MB for backup spl image(s)*/
@@ -148,7 +156,6 @@ 
				};

			} ;

		} ;

		};



		elphel_ahci: elphel-ahci@80000000 {

			compatible = "elphel,elphel-ahci";

src/arch/arm/boot/dts/elphel393-revision-rev0-B.dtsi

0 → 100644
+23 −0
Original line number Diff line number Diff line 
/ {

    ps7_axi_interconnect_0: amba@0 {

        ps7_ethernet_0: ps7-ethernet@e000b000 {

            local-mac-address = [00 0e 64 10 00 00];

            phy-handle = <&phy3>;

            phy-mode = "rgmii-id";

            mdio {

                #address-cells = <1>;

                #size-cells = <0>;

                phy3: phy@3 {

                        /* Atheros 8035 */

                        compatible = "ethernet-phy-id004d.d072";

                        /* compatible = "ethernet-phy-ieee802.3-c22";*/

                        device_type = "ethernet-phy";

                        /* rev0 - revB: reg = <0x3> */

                        /* revC:        reg = <0x0> */

                        reg = <0x3>;

                };

            };

        };

    };



};
 
 No newline at end of file

src/arch/arm/boot/dts/elphel393-revision-revC.dtsi

0 → 100644
+23 −0
Original line number Diff line number Diff line 
/ {

    ps7_axi_interconnect_0: amba@0 {

        ps7_ethernet_0: ps7-ethernet@e000b000 {

            local-mac-address = [00 0e 64 10 00 00];

            phy-handle = <&phy3>;

            phy-mode = "rgmii-id";

            mdio {

                #address-cells = <1>;

                #size-cells = <0>;

                phy3: phy@3 {

                        /* Atheros 8035 */

                        compatible = "ethernet-phy-id004d.d072";

                        /* compatible = "ethernet-phy-ieee802.3-c22";*/

                        device_type = "ethernet-phy";

                        /* rev0 - revB: reg = <0x3> */

                        /* revC:        reg = <0x0> */

                        reg = <0x0>;

                };

            };

        };

    };



};
 
 No newline at end of file

src/arch/arm/boot/dts/elphel393-zynq-base.dtsi

+13 −12
Original line number Diff line number Diff line
@@ -296,23 +296,24 @@ 
			reg = <0xf8001000 0x1000>;

		} ;



		smcc: memory-controller@e000e000 {

			#address-cells = <2>;

		ps7_smcc_0: ps7-smcc@e000e000 {

			#address-cells = <1>;

			#size-cells = <1>;

		  	clock-names = "memclk", "apb_pclk";

		  	clock-names = "memclk", "aclk";

			clocks = <&clkc 11>, <&clkc 44>;

			compatible = "arm,pl353-smc-r2p1", "arm,primecell";

			compatible = "arm,pl353-smc-r2p1";

			interrupt-parent = <&ps7_scugic_0>;

			interrupts = < 0 18 4 >;

			ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region

				  0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region

				  0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region



			ranges ;

			reg = < 0xe000e000 0x1000 >;

			nand0: flash@e1000000 {

			arm,addr25 = <0x0>;

			arm,nor-chip-sel0 = <0x0>;

			arm,nor-chip-sel1 = <0x0>;

			arm,sram-chip-sel0 = <0x0>;

			arm,sram-chip-sel1 = <0x0>;

			ps7_nand_0: ps7-nand@e1000000 {

				compatible = "arm,pl353-nand-r2p1";

				reg = <0 0 0x1000000>;

                                nand-ecc-mode = "on-die";

				reg = < 0xe1000000 0x1000000 >;

				/*arm,nand-clk-freq-hz = <0x5f5e100>;*/

				arm,nand-width = <0x8>;

				arm,nand-cycle-t0 = <0x4>;